From 18976e2ce433db91d25c14d1a5c6b036f273b147 Mon Sep 17 00:00:00 2001
From: eyck <eyck@minres.com>
Date: Mon, 22 Jun 2020 08:45:12 +0200
Subject: [PATCH] adapt to newer gdb protocol

---
 gen_input/minres_rv.core_desc            |  4 +--
 incl/iss/debugger/riscv_target_adapter.h | 35 ++++++++++--------------
 2 files changed, 17 insertions(+), 22 deletions(-)

diff --git a/gen_input/minres_rv.core_desc b/gen_input/minres_rv.core_desc
index 5596bd2..b4246ce 100644
--- a/gen_input/minres_rv.core_desc
+++ b/gen_input/minres_rv.core_desc
@@ -6,7 +6,7 @@ import "RVC.core_desc"
 import "RVF.core_desc"
 import "RVD.core_desc"
 
-/*
+
 Core MNRV32 provides RV32I, RV32IC {
     constants {
         XLEN:=32;
@@ -57,7 +57,7 @@ Core RV64I provides RV64I {
         PGMASK := 0xfff; //PGSIZE-1
     }
 }
-*/
+
 Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
     constants {
         XLEN:=64;
diff --git a/incl/iss/debugger/riscv_target_adapter.h b/incl/iss/debugger/riscv_target_adapter.h
index 32cded0..6d33e01 100644
--- a/incl/iss/debugger/riscv_target_adapter.h
+++ b/incl/iss/debugger/riscv_target_adapter.h
@@ -184,33 +184,28 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
     avail.clear();
     const uint8_t *reg_base = core->get_regs_base_ptr();
     for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
-        auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
+        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
         unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
         for (size_t j = 0; j < reg_width; ++j) {
             data.push_back(*(reg_base + offset + j));
             avail.push_back(0xff);
         }
-        // if(arch::traits<ARCH>::XLEN < 64)
-        //     for(unsigned j=0; j<4; ++j){
-        //         data.push_back(0);
-        //         avail.push_back(0xff);
-        //     }
     }
     // work around fill with F type registers
-    if (arch::traits<ARCH>::NUM_REGS < 65) {
-        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
-        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
-            for (size_t j = 0; j < reg_width; ++j) {
-                data.push_back(0x0);
-                avail.push_back(0x00);
-            }
-            // if(arch::traits<ARCH>::XLEN < 64)
-            //     for(unsigned j=0; j<4; ++j){
-            //         data.push_back(0x0);
-            //         avail.push_back(0x00);
-            //     }
-        }
-    }
+//    if (arch::traits<ARCH>::NUM_REGS < 65) {
+//        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
+//        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
+//            for (size_t j = 0; j < reg_width; ++j) {
+//                data.push_back(0x0);
+//                avail.push_back(0x00);
+//            }
+//            // if(arch::traits<ARCH>::XLEN < 64)
+//            //     for(unsigned j=0; j<4; ++j){
+//            //         data.push_back(0x0);
+//            //         avail.push_back(0x00);
+//            //     }
+//        }
+//    }
     return Ok;
 }