DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

Implement MHARTID register

Browse Source
This commit is contained in:
Stanislaw Kaushanski
2020-09-04 15:37:21 +02:00
parent 886b8f5716
commit 969b408288
4 changed files with 30 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
incl/iss/arch/riscv_hart_m_p.h
View File

@ -43,9 +43,9 @@
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <elfio/elfio.hpp>
#include <fmt/format.h>
#include <iomanip>
#include <sstream>
#include <type_traits>
@ -266,7 +266,7 @@ public:
trap_store_page_fault(uint64_t badaddr)
: trap_access(15 << 16, badaddr) {}
};
}
} // namespace
template <typename BASE> class riscv_hart_m_p : public BASE {
public:
@ -392,6 +392,9 @@ public:
virtual uint64_t leave_trap(uint64_t flags) override;
void wait_until(uint64_t flags) override;
const reg_t& get_mhartid() const { return mhartid_reg; }
void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
void disass_output(uint64_t pc, const std::string instr) override {
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]",
pc, instr, lvl[this->reg.machine_state], (reg_t)state.mstatus, this->reg.icount);
@ -464,6 +467,9 @@ private:
iss::status write_satp(unsigned addr, reg_t val);
iss::status read_fcsr(unsigned addr, reg_t &val);
iss::status write_fcsr(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
reg_t mhartid_reg{0xF};
protected:
void check_interrupt();
@ -507,14 +513,7 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
csr_wr_cb[sie] = &riscv_hart_m_p<BASE>::write_ie;
csr_rd_cb[uie] = &riscv_hart_m_p<BASE>::read_ie;
csr_wr_cb[uie] = &riscv_hart_m_p<BASE>::write_ie;
csr_rd_cb[satp] = &riscv_hart_m_p<BASE>::read_satp;
csr_wr_cb[satp] = &riscv_hart_m_p<BASE>::write_satp;
csr_rd_cb[fcsr] = &riscv_hart_m_p<BASE>::read_fcsr;
csr_wr_cb[fcsr] = &riscv_hart_m_p<BASE>::write_fcsr;
csr_rd_cb[fflags] = &riscv_hart_m_p<BASE>::read_fcsr;
csr_wr_cb[fflags] = &riscv_hart_m_p<BASE>::write_fcsr;
csr_rd_cb[frm] = &riscv_hart_m_p<BASE>::read_fcsr;
csr_wr_cb[frm] = &riscv_hart_m_p<BASE>::write_fcsr;
csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
}
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
@ -838,6 +837,11 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
val = mhartid_reg;
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
auto req_priv_lvl = (addr >> 8) & 0x3;
auto mask = get_irq_mask(req_priv_lvl);
@ -1281,7 +1285,7 @@ template <typename BASE> void riscv_hart_m_p<BASE>::wait_until(uint64_t flags) {
this->fault_data = this->reg.PC;
}
}
}
}
} // namespace arch
} // namespace iss
#endif /* _RISCV_CORE_H_ */

4
incl/sysc/core_complex.h
View File

@ -56,7 +56,7 @@ template <typename BASE> class riscv_hart_m_p;
namespace debugger {
class target_adapter_if;
}
}
} // namespace iss
namespace sysc {
@ -103,6 +103,8 @@ public:
cci::cci_param<bool> dump_ir{"dump_ir", false};
cci::cci_param<uint32_t> mhartid{"mhartid", 0};
core_complex(sc_core::sc_module_name name);
~core_complex();