DBT-RISE/DBT-RISE-TGC
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adapt to newer gdb protocol

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This commit is contained in:
Eyck Jentzsch
2020-06-22 08:45:12 +02:00
parent 71b976811b
commit 18976e2ce4
2 changed files with 17 additions and 22 deletions
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35
incl/iss/debugger/riscv_target_adapter.h
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@ -184,33 +184,28 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
avail.clear();
const uint8_t *reg_base = core->get_regs_base_ptr();
for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
for (size_t j = 0; j < reg_width; ++j) {
data.push_back(*(reg_base + offset + j));
avail.push_back(0xff);
}
// if(arch::traits<ARCH>::XLEN < 64)
// for(unsigned j=0; j<4; ++j){
// data.push_back(0);
// avail.push_back(0xff);
// }
}
// work around fill with F type registers
if (arch::traits<ARCH>::NUM_REGS < 65) {
auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
for (size_t j = 0; j < reg_width; ++j) {
data.push_back(0x0);
avail.push_back(0x00);
}
// if(arch::traits<ARCH>::XLEN < 64)
// for(unsigned j=0; j<4; ++j){
// data.push_back(0x0);
// avail.push_back(0x00);
// }
}
}
// if (arch::traits<ARCH>::NUM_REGS < 65) {
// auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
// for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
// for (size_t j = 0; j < reg_width; ++j) {
// data.push_back(0x0);
// avail.push_back(0x00);
// }
// // if(arch::traits<ARCH>::XLEN < 64)
// // for(unsigned j=0; j<4; ++j){
// // data.push_back(0x0);
// // avail.push_back(0x00);
// // }
// }
// }
return Ok;
}