Fixed time csr handling

This commit is contained in:
Eyck Jentzsch 2019-06-28 20:58:02 +02:00
parent d93c2feec4
commit 7f06bba239
6 changed files with 26 additions and 5 deletions

View File

@ -103,7 +103,7 @@ void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
reg.machine_state=0x3;
reg.icount=0;
}

View File

@ -39,6 +39,7 @@
#include "scv4tlm/tlm_rec_initiator_socket.h"
#include <cci_configuration>
#include <tlm>
#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
#include <tlm_utils/tlm_quantumkeeper.h>
#include <util/range_lut.h>
@ -90,6 +91,8 @@ public:
sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i;
sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
cci::cci_param<std::string> elf_file;
cci::cci_param<bool> enable_disass;

View File

@ -66,7 +66,7 @@ void rv32gc::reset(uint64_t address) {
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
reg.machine_state=0x3;
reg.icount=0;
}

View File

@ -67,7 +67,7 @@ void rv64gc::reset(uint64_t address) {
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
reg.machine_state=0x3;
reg.icount=0;
}

View File

@ -65,7 +65,7 @@ void rv64i::reset(uint64_t address) {
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
reg.machine_state=0x3;
reg.icount=0;
}

View File

@ -93,7 +93,9 @@ public:
using base_type = arch::riscv_hart_msu_vp<arch::rv32imac>;
using phys_addr_t = typename arch::traits<arch::rv32imac>::phys_addr_t;
core_wrapper(core_complex *owner)
: owner(owner) {}
: owner(owner)
{
}
uint32_t get_mode() { return this->reg.machine_state; }
@ -144,6 +146,22 @@ public:
}
}
status read_csr(unsigned addr, reg_t &val) override {
if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
uint64_t time_val;
bool ret = owner->mtime_o->nb_peek(time_val);
if (addr == iss::arch::time) {
val = static_cast<reg_t>(time_val);
} else if (addr == iss::arch::timeh) {
if (sizeof(reg_t) != 4) return iss::Err;
val = static_cast<reg_t>(time_val >> 32);
}
return ret?Ok:Err;
} else {
return base_type::read_csr(addr, val);
}
}
void wait_until(uint64_t flags) override {
SCDEBUG(owner->name()) << "Sleeping until interrupt";
do {