diff --git a/gen_input/templates/src-CORENAME.cpp.gtl b/gen_input/templates/src-CORENAME.cpp.gtl
index ee9641b..6dee5fc 100644
--- a/gen_input/templates/src-CORENAME.cpp.gtl
+++ b/gen_input/templates/src-CORENAME.cpp.gtl
@@ -103,7 +103,7 @@ void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.trap_state=0;
-    reg.machine_state=0x0;
+    reg.machine_state=0x3;
     reg.icount=0;
 }
 
diff --git a/incl/sysc/core_complex.h b/incl/sysc/core_complex.h
index 99e22f0..047f897 100644
--- a/incl/sysc/core_complex.h
+++ b/incl/sysc/core_complex.h
@@ -39,6 +39,7 @@
 #include "scv4tlm/tlm_rec_initiator_socket.h"
 #include <cci_configuration>
 #include <tlm>
+#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
 #include <tlm_utils/tlm_quantumkeeper.h>
 #include <util/range_lut.h>
 
@@ -90,6 +91,8 @@ public:
 
     sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i;
 
+    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
+
     cci::cci_param<std::string> elf_file;
 
     cci::cci_param<bool> enable_disass;
diff --git a/src/iss/rv32gc.cpp b/src/iss/rv32gc.cpp
index a5f3ce7..4149503 100644
--- a/src/iss/rv32gc.cpp
+++ b/src/iss/rv32gc.cpp
@@ -66,7 +66,7 @@ void rv32gc::reset(uint64_t address) {
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.trap_state=0;
-    reg.machine_state=0x0;
+    reg.machine_state=0x3;
     reg.icount=0;
 }
 
diff --git a/src/iss/rv64gc.cpp b/src/iss/rv64gc.cpp
index 8d27912..7353643 100644
--- a/src/iss/rv64gc.cpp
+++ b/src/iss/rv64gc.cpp
@@ -67,7 +67,7 @@ void rv64gc::reset(uint64_t address) {
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.trap_state=0;
-    reg.machine_state=0x0;
+    reg.machine_state=0x3;
     reg.icount=0;
 }
 
diff --git a/src/iss/rv64i.cpp b/src/iss/rv64i.cpp
index 0d09f20..b3b875c 100644
--- a/src/iss/rv64i.cpp
+++ b/src/iss/rv64i.cpp
@@ -65,7 +65,7 @@ void rv64i::reset(uint64_t address) {
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.trap_state=0;
-    reg.machine_state=0x0;
+    reg.machine_state=0x3;
     reg.icount=0;
 }
 
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 16166b3..ff53186 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -93,7 +93,9 @@ public:
     using base_type = arch::riscv_hart_msu_vp<arch::rv32imac>;
     using phys_addr_t = typename arch::traits<arch::rv32imac>::phys_addr_t;
     core_wrapper(core_complex *owner)
-    : owner(owner) {}
+    : owner(owner) 
+    {
+    }
 
     uint32_t get_mode() { return this->reg.machine_state; }
 
@@ -144,6 +146,22 @@ public:
         }
     }
 
+    status read_csr(unsigned addr, reg_t &val) override {
+        if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
+            uint64_t time_val;
+            bool ret = owner->mtime_o->nb_peek(time_val);
+            if (addr == iss::arch::time) {
+                val = static_cast<reg_t>(time_val);
+            } else if (addr == iss::arch::timeh) {
+                if (sizeof(reg_t) != 4) return iss::Err;
+                val = static_cast<reg_t>(time_val >> 32);
+            }
+            return ret?Ok:Err;
+        } else {
+            return base_type::read_csr(addr, val);
+        }
+    }
+
     void wait_until(uint64_t flags) override {
         SCDEBUG(owner->name()) << "Sleeping until interrupt";
         do {