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afe8905ac9
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fix else-ambiguity in CoreDSL description
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2022-01-31 20:30:46 +01:00 |
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3563ba80d0
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add spawn blocks
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2022-01-12 07:21:16 +01:00 |
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07d5af1dde
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fix stand-alone ISS compilation to include all generated cores
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2021-11-26 17:56:40 +01:00 |
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965929d1eb
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remove descriptions
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2021-11-15 09:30:16 +01:00 |
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d31b4ef5a8
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fix MISA val
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2021-11-11 12:58:57 +01:00 |
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7452c5df43
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add TGC_D_XRB_NN definition
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2021-11-11 12:16:35 +01:00 |
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fd98ad95f6
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rework PMP check and fix MISA for TGC_D
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2021-11-09 15:55:22 +01:00 |
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c42e336509
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fix proper debug mode handling (#267 & #268)
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2021-11-07 17:48:44 +01:00 |
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8b6e3abd23
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fix hard-code arch in templates
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2021-10-30 13:37:17 +02:00 |
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1616f0ac90
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remove deprecated functions
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2021-10-30 12:57:08 +02:00 |
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a20f39e847
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update core definitions to include Zicsr and Zifencei (#276)
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2021-10-30 12:56:31 +02:00 |
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334d3fb296
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adapt to SCC changes
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2021-10-21 22:53:16 +02:00 |
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1d13c8196e
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fix wrong PGMASK usage
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2021-10-11 10:40:01 +02:00 |
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b17682e50e
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fix YAML template
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2021-10-01 23:49:04 +02:00 |
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6acf73a40f
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add template to generate instruction YAML
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2021-10-01 13:05:36 +02:00 |
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2f15d9676e
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fix unaligned instr fetch behavior
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2021-09-30 19:27:46 +02:00 |
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4186723d37
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add marchid setting to CoreDSL description
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2021-09-30 19:26:21 +02:00 |
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aa84a27a5b
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fix JALR alignment in description
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2021-09-29 00:43:42 +02:00 |
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438e598a4a
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remove clutter from core descriptions, added instr alignment setting
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2021-09-29 00:03:11 +02:00 |
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174259155d
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add support for non-compressed ISA
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2021-09-23 21:09:52 +02:00 |
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a3084456fd
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rework core definitions
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2021-09-04 12:47:07 +02:00 |
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adeffe47ad
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fix behavior of riscv_hart_mu_p to match TGC_D
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2021-08-12 20:34:10 +02:00 |
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d95846a849
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fix trap handling if illegal fetch (PMP) and U-mode CSRs
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2021-08-01 17:23:22 +02:00 |
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e68918c2e8
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fix instruction decode
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2021-07-09 07:37:12 +02:00 |
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2f4b5bd9b2
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fix detailed behavior of TGC_C
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2021-07-06 21:19:36 +02:00 |
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23b9741adf
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refine and fix TGC_C iss to becoem compliant
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2021-06-29 11:51:30 +02:00 |
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e432dd8208
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fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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cf7b62a3f9
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update names
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2021-05-13 15:54:48 +02:00 |
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32e4aa83b8
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use extracted variables
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2021-03-27 09:36:52 +00:00 |
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78c7064295
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update groovy template to extract used registers
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2021-03-26 08:24:45 +00:00 |
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b0bcb7febb
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small fixes for robustness and readability
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2021-03-22 22:47:30 +00:00 |
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4e0f20eba0
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rework abort conditions
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2021-03-17 19:32:57 +00:00 |
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ff3fa19208
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fix RVM description bugs
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2021-03-13 10:46:41 +00:00 |
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80057eef32
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fix RVC description bugs, remove paged fetch
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2021-03-13 10:46:41 +00:00 |
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f4ec21007b
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fix signedness issues
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2021-03-11 16:12:28 +00:00 |
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ac8eab6e25
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update RISC-V desciptions
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2021-03-10 17:31:10 +00:00 |
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bea0dcc387
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update missing XLEN
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2021-03-09 11:03:37 +00:00 |
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a6691bcd3c
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update generated code with correct sign extension
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2021-03-09 10:21:36 +00:00 |
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c171e3c1ba
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update CoreDSL descriptions
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2021-03-07 10:51:15 +00:00 |
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c251fe15d5
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fix desscriptions to conform to ISA spec version 20191213 and TGF-C
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2021-03-07 10:51:00 +00:00 |
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dae8acb8a3
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checkpoint before refactor
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2021-03-06 07:17:42 +00:00 |
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be0e7db185
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fix templates to comply with CoreDSL2
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2021-03-01 21:07:20 +00:00 |
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9534d58d01
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regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
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1668df0531
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regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
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d8e009c72b
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update CoreDSL decriptions
|
2021-02-15 18:15:13 +00:00 |
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72b09472d5
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update RISC-V descriptions
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2021-02-15 18:01:33 +00:00 |
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3261055871
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update description to latest CoreDSL2
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2021-02-15 11:35:56 +00:00 |
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34bb8e62ae
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generate working ISS from CoreDSL 2.0
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2021-02-06 14:47:06 +00:00 |
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da7e29fbb7
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update definitions of derived constants
|
2021-01-01 09:19:48 +00:00 |
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