DBT-RISE/DBT-RISE-TGC
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remove clutter from core descriptions, added instr alignment setting

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This commit is contained in:
Eyck Jentzsch
2021-09-29 00:03:11 +02:00
parent 174259155d
commit 438e598a4a
7 changed files with 57 additions and 25 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

Submodule gen_input/CoreDSL-Instruction-Set-Description updated: 8d9a0fb149...89dabd00e3

5
gen_input/TGC_B.core_desc
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@ -4,13 +4,10 @@ import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_B provides RV32I {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000000000100000000;
unsigned PGSIZE = 0x1000; //1 << 12;
unsigned PGMASK = 0xfff; //PGSIZE-1
}
}

5
gen_input/TGC_C.core_desc
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@ -4,12 +4,9 @@ import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_C provides RV32I, RV32M, RV32IC {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned PGSIZE = 0x1000; //1 << 12;
unsigned PGMASK = 0xfff; //PGSIZE-1
}
}

3
gen_input/TGC_D.core_desc
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@ -4,8 +4,7 @@ import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_D provides RV32I, RV32M, RV32IC {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;

3
gen_input/TGC_D_XRB_MAC.core_desc
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@ -64,8 +64,7 @@ InstructionSet X_RB_MAC extends RISCVBase {
Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;