fix stand-alone ISS compilation to include all generated cores

2021-11-26 17:56:40 +01:00
parent 6f8595759e
commit 07d5af1dde
3 changed files with 16 additions and 12 deletions
--- a/gen_input/templates/CORENAME_cyles.txt.gtl
+++ b/gen_input/templates/CORENAME_cyles.txt.gtl
@ -1,9 +1,9 @@
-{ 
+{
 	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
 		{
 			"name"  : "${instr.name}",
 			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+			"delay" : ${instr.isConditional?"[1,1]":"1"}
 		}<%}%>
 	]
 }