DBT-RISE/DBT-RISE-TGC
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small fixes for robustness and readability

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This commit is contained in:
Eyck Jentzsch
2021-03-22 22:47:30 +00:00
parent 51fbc34fb3
commit b0bcb7febb
4 changed files with 11 additions and 5 deletions
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7
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -272,6 +272,9 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
}
}
inline bool is_count_limit_enabled(finish_cond_e cond){
return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
}
template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
// we fetch at max 4 byte, alignment is 2
@ -279,8 +282,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
code_word_t insn = 0;
auto *const data = (uint8_t *)&insn;
auto pc=start;
while(!core.should_stop() &&
!((cond & finish_cond_e::COUNT_LIMIT) && core.get_icount() < icount)){
while(!this->core.should_stop() &&
!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
auto res = fetch_ins(pc, data);
if(res!=iss::Ok){
auto new_pc = super::core.enter_trap(TRAP_ID, pc.val);