Eyck Jentzsch 07d5af1dde fix stand-alone ISS compilation to include all generated cores		2021-11-26 17:56:40 +01:00
..
CoreDSL-Instruction-Set-Description@b005607fc3	fix proper debug mode handling (#267 & #268)	2021-11-07 17:48:44 +01:00
templates	fix stand-alone ISS compilation to include all generated cores	2021-11-26 17:56:40 +01:00
.gitignore	reorganized layout to only contain risc-v stuff	2019-06-11 16:49:37 +00:00
TGC_C.core_desc	update core definitions to include Zicsr and Zifencei (#276)	2021-10-30 12:56:31 +02:00