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Trace_enhancement

develop

feature/core_factory

feature/htif

feature/interpreter

feature/iss_factory

feature/reduced_output

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msvc_compat

#3

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• a977200284 cleans up priv wrappers Eyck Jentzsch 2022-10-05 08:58:57 +0200
• b20fd3eba5 fix static build Eyck Jentzsch 2022-09-28 19:37:47 +0200
• b20daa1ac2 fixes wrong path in install Eyck Jentzsch 2022-09-27 09:11:41 +0200
• b1a18459e7 adds more flexible use of availabel targets Eyck Jentzsch 2022-09-26 13:57:24 +0200
• 6ba7c82f80 fixes wrapper definitions for hwl cores Eyck Jentzsch 2022-09-26 13:31:36 +0200
• ad7bb28b4c fixes write mask of clic memory mapped registers Eyck Jentzsch 2022-09-17 12:14:03 +0200
• fa7eda0889 fixes wrong check for exception Eyck Jentzsch 2022-08-31 11:45:53 +0200
• 00e02bf565 adds support for different branch types in tracing Eyck Jentzsch 2022-08-08 06:30:37 +0200
• 1ad66a71d8 extends supported break point types Eyck Jentzsch 2022-08-06 09:53:24 +0200
• e60fa3d5e6 adaptes to changes in dbt-rise-core Eyck Jentzsch 2022-08-06 09:49:32 +0200
• 8407f6287f replaces core_complex socket Eyck Jentzsch 2022-07-24 20:52:16 +0200
• 0833198d34 aads missing windows compat firx to template Eyck Jentzsch 2022-07-23 14:36:23 +0200
• 57347ae4d9 fixes cppcheck flagged issues Eyck Jentzsch 2022-07-23 13:48:55 +0200
• 4876f18ba9 adds windows compatibility fixes Eyck Jentzsch 2022-07-18 11:02:17 +0200
• a53ee42e13 updates TGC_C according to CoreDSL description update Eyck Jentzsch 2022-07-12 22:34:22 +0200
• 12ccfc055a updates generate tgc_c definition Eyck Jentzsch 2022-07-11 22:58:10 +0200
• feaa49d367 removes decoder again as there is some issue Eyck Jentzsch 2022-06-20 00:39:11 +0200
• 18f33b4a68 fixes ordering of instructions for decoding Eyck Jentzsch 2022-06-19 16:52:29 +0200
• f096b15dbd factors decoder into separate component Eyck Jentzsch 2022-06-19 12:45:34 +0200
• cb5375258a removes compilatioon of unneeded files Eyck Jentzsch 2022-06-10 07:19:46 +0200
• 076b5a39ad fix class naming Eyck Jentzsch 2022-06-02 08:30:49 +0200
• f40ab41899 fix left-over from layout refactoring Eyck Jentzsch 2022-06-02 08:30:02 +0200
• e8fd5143bc fix build options for standalone ISS Eyck Jentzsch 2022-05-31 11:05:26 +0200
• 31fb51de95 update tgc_c generated code Eyck Jentzsch 2022-05-30 22:15:44 +0200
• 5d481eb79d fix generation of non-exception code Eyck Jentzsch 2022-05-30 22:04:16 +0200
• 1c90fe765d Merge remote-tracking branch 'origin/Trace_enhancement' into develop Eyck Jentzsch 2022-05-30 14:18:09 +0200
• 52ed8b81a6 fixed template to work with previous code generator Eyck Jentzsch 2022-05-30 14:08:02 +0200
• 0703a0a845 update tgc-mapper Eyck Jentzsch 2022-05-30 07:45:32 +0200
• 0c542d42aa separate generated sources Eyck Jentzsch 2022-05-21 12:27:13 +0200
• 966d1616c5 change source code to unified layout Eyck Jentzsch 2022-05-21 11:55:24 +0200
• 1720bd4aaa adds support for compressed instructions Trace_enhancement Eyck-Alexander Jentzsch 2022-05-20 15:17:58 +0200
• df16378605 update template for changed code generator Eyck Jentzsch 2022-05-18 19:10:34 +0200
• 1438f0f373 add backannotation to pc trace plugin Eyck Jentzsch 2022-05-17 15:29:04 +0200
• 766f3ba9ee fix assertion in compressed pctrace writer Eyck Jentzsch 2022-05-13 12:38:12 +0200
• 5da4e6b424 fix alignment check for unaligned debugger accesses Eyck Jentzsch 2022-05-13 12:37:47 +0200
• e382217e04 update vm_tgc_c due reworked CoreDSL generator Eyck Jentzsch 2022-05-11 18:52:15 +0200
• 9db4e3fd87 fix assertion Eyck Jentzsch 2022-05-10 16:13:21 +0200
• bb658be3b4 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop Eyck-Alexander Jentzsch 2022-05-08 15:25:56 +0200
• 6579780dc9 add call column in output Eyck-Alexander Jentzsch 2022-05-08 15:24:26 +0200
• e56bc12788 fix non-lz4 build of plugin Eyck Jentzsch 2022-05-07 17:25:11 +0200
• e88f309ea2 add lz4 compression to pctrace Eyck Jentzsch 2022-05-07 17:22:06 +0200
• 03bec27376 implement extended instrumentation interface Eyck Jentzsch 2022-04-26 17:14:33 +0200
• 9d9008a3a2 fix pointer mess Eyck Jentzsch 2022-04-26 15:11:57 +0200
• 5f6d462973 check that no interrupts are pending before entering the wfi wait Stanislaw Kaushanski 2022-04-26 13:58:20 +0200
• a92b84bef4 add code word access for ISS plugins Eyck Jentzsch 2022-04-25 14:18:19 +0200
• b6824e68e9 Merge branch 'master' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git Eyck Jentzsch 2022-04-23 17:08:05 +0200
• 1196424e39 Merge branch 'develop' Eyck Jentzsch 2022-04-23 17:06:52 +0200
• 477c530847 extend debug mode handling Eyck Jentzsch 2022-04-13 11:41:01 +0200
• c054d75717 update to latest coredsl description Eyck Jentzsch 2022-04-10 18:55:44 +0200
• 15cd26f800 remove CoreDSL ISA repo Eyck Jentzsch 2022-04-10 12:15:40 +0200
• 9465cffe79 adapt to change in dbt-rise-core Eyck Jentzsch 2022-04-09 14:55:36 +0200
• 126fdc7e63 update coredsl descriptions to match latest syntax Eyck Jentzsch 2022-04-07 11:04:18 +0200
• 00d2d06cbd adapt to privileged spec Eyck Jentzsch 2022-03-31 20:33:12 +0200
• 8e4e702cb9 Merge remote-tracking branch 'origin/feature/reduced_output' into develop Eyck Jentzsch 2022-03-28 14:09:06 +0200
• 58311b37db Merge branch 'feature/reduced_output' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into feature/reduced_output feature/reduced_output Eyck-Alexander Jentzsch 2022-03-28 11:16:09 +0200
• ad8dc09bee Merge branch 'feature/reduced_output' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into feature/reduced_output Eyck-Alexander Jentzsch 2022-03-28 11:15:45 +0200
• 49be143588 make features configurable Eyck Jentzsch 2022-03-27 17:54:08 +0200
• 0aea1d0177 remove mcounteren in M-mode only wrapper Eyck Jentzsch 2022-03-27 17:21:46 +0200
• 6ea7721961 add TCM Eyck Jentzsch 2022-03-27 15:38:18 +0200
• b0cb997009 add TGC_X with DMR Eyck Jentzsch 2022-03-26 10:48:21 +0100
• 9dfca612b7 add hardware loop CSR access Eyck Jentzsch 2022-03-25 11:33:44 +0100
• 30ae743361 add pctrace plugin to iss Eyck Jentzsch 2022-03-20 17:39:44 +0100
• d91f5f9df4 fix compiler warning for reduced number of registers Eyck Jentzsch 2022-03-14 15:37:01 +0100
• 5ec457c76b build pctrace plugin only if RapidJSON target is availble Stanislaw Kaushanski 2022-03-08 11:23:07 +0100
• 2e670c4d03 change interpreter structure Eyck Jentzsch 2022-03-06 15:11:38 +0100
• 3d32c33333 update gitignore Eyck Jentzsch 2022-03-05 20:59:45 +0100
• 521f40a3d6 refactored interpreter backend structure Eyck Jentzsch 2022-03-05 20:59:17 +0100
• 2bba5645c3 adds functionality to reduce the output Eyck-Alexander Jentzsch 2022-02-16 10:12:45 +0100
• bf0a5a80de adds functionality to reduce the output Eyck-Alexander Jentzsch 2022-02-16 10:12:45 +0100
• b37ef973de clean up Eyck Jentzsch 2022-02-14 20:36:12 +0100
• 4c363f4073 adds additional functionality by fetching delay information Eyck-Alexander Jentzsch 2022-02-11 11:28:00 +0100
• b8fa5fbbda adapt to extended instrumentation interface Eyck Jentzsch 2022-02-09 21:01:17 +0100
• ac86f14a54 add tgc_c_xrb_nn to tgc-sim Eyck Jentzsch 2022-02-02 21:33:42 +0100
• 68b5697c8f Fix cycles JSON template Eyck Jentzsch 2022-02-01 21:48:56 +0100
• 09b0f0d0c8 fix cycle estimation plugin Eyck Jentzsch 2022-02-01 21:14:50 +0100
• 98b418ff43 fix JSON reading Eyck Jentzsch 2022-02-01 19:28:11 +0100
• 059bd0d371 rework cycle estimation Eyck Jentzsch 2022-02-01 19:03:45 +0100
• ef2a4df925 simplify spawn block handling Eyck Jentzsch 2022-01-31 23:40:19 +0100
• 7578906310 adds coverage plugin Eyck-Alexander Jentzsch 2022-01-31 21:38:18 +0100
• afe8905ac9 fix else-ambiguity in CoreDSL description Eyck Jentzsch 2022-01-31 20:06:12 +0100
• ecc6091d1e cleans up source code to remove clang compiler warnings Eyck-Alexander Jentzsch 2022-01-19 08:01:15 +0100
• 3563ba80d0 add spawn blocks Eyck Jentzsch 2022-01-12 07:21:16 +0100
• 09955be90f update gitignore Eyck Jentzsch 2021-12-05 08:41:29 +0100
• dd4c19a15c add option to configure number of irq Eyck Jentzsch 2021-12-01 12:56:36 +0100
• 07d5af1dde fix stand-alone ISS compilation to include all generated cores Eyck Jentzsch 2021-11-26 17:56:40 +0100
• 6f8595759e make tgc-sim include all available ISS Eyck Jentzsch 2021-11-25 19:59:50 +0100
• 86da31033c correct size usage in pmp addr checks Maribel 2021-11-22 15:15:47 +0100
• 974d103381 fix pmpcfg register write Maribel 2021-11-22 10:49:29 +0100
• 309758b994 fix clic_cfg access scheme Eyck Jentzsch 2021-11-17 07:59:02 +0100
• 965929d1eb remove descriptions Eyck Jentzsch 2021-11-15 09:30:16 +0100
• d47375a70e fix ebreak CSR update Eyck Jentzsch 2021-11-13 12:47:23 +0100
• d5fa47ef7f Merge branch 'develop' Eyck Jentzsch 2021-11-11 19:34:21 +0100
• d31b4ef5a8 fix MISA val Eyck Jentzsch 2021-11-11 12:58:57 +0100
• 7452c5df43 add TGC_D_XRB_NN definition Eyck Jentzsch 2021-11-11 12:16:35 +0100
• 43d7b99905 revert pmp check implementation Eyck Jentzsch 2021-11-11 09:58:19 +0100
• f90c48e881 adapt to changed define names Eyck Jentzsch 2021-11-11 08:33:35 +0100
• 2d7973520b fix mip handling Eyck Jentzsch 2021-11-09 19:47:34 +0100
• fd98ad95f6 rework PMP check and fix MISA for TGC_D Eyck Jentzsch 2021-11-09 15:55:22 +0100
• bfa8166223 fix wrong template class name Eyck Jentzsch 2021-11-08 10:44:33 +0100
• c42e336509 fix proper debug mode handling (#267 & #268) Eyck Jentzsch 2021-11-07 17:48:44 +0100