Commit Graph

78 Commits

Author SHA1 Message Date
Eyck Jentzsch 521f40a3d6 refactored interpreter backend structure 2022-03-05 20:59:17 +01:00
Eyck Jentzsch b8fa5fbbda adapt to extended instrumentation interface 2022-02-09 21:01:17 +01:00
Eyck Jentzsch 68b5697c8f Fix cycles JSON template 2022-02-01 21:48:56 +01:00
Eyck Jentzsch 059bd0d371 rework cycle estimation 2022-02-01 19:03:45 +01:00
Eyck Jentzsch ef2a4df925 simplify spawn block handling 2022-01-31 23:40:31 +01:00
Eyck Jentzsch afe8905ac9 fix else-ambiguity in CoreDSL description 2022-01-31 20:30:46 +01:00
Eyck Jentzsch 3563ba80d0 add spawn blocks 2022-01-12 07:21:16 +01:00
Eyck Jentzsch 07d5af1dde fix stand-alone ISS compilation to include all generated cores 2021-11-26 17:56:40 +01:00
Eyck Jentzsch 965929d1eb remove descriptions 2021-11-15 09:30:16 +01:00
Eyck Jentzsch d31b4ef5a8 fix MISA val 2021-11-11 12:58:57 +01:00
Eyck Jentzsch 7452c5df43 add TGC_D_XRB_NN definition 2021-11-11 12:16:35 +01:00
Eyck Jentzsch fd98ad95f6 rework PMP check and fix MISA for TGC_D 2021-11-09 15:55:22 +01:00
Eyck Jentzsch c42e336509 fix proper debug mode handling (#267 & #268) 2021-11-07 17:48:44 +01:00
Eyck Jentzsch 8b6e3abd23 fix hard-code arch in templates 2021-10-30 13:37:17 +02:00
Eyck Jentzsch 1616f0ac90 remove deprecated functions 2021-10-30 12:57:08 +02:00
Eyck Jentzsch a20f39e847 update core definitions to include Zicsr and Zifencei (#276) 2021-10-30 12:56:31 +02:00
Eyck Jentzsch 334d3fb296 adapt to SCC changes 2021-10-21 22:53:16 +02:00
Eyck Jentzsch 1d13c8196e fix wrong PGMASK usage 2021-10-11 10:40:01 +02:00
Eyck Jentzsch b17682e50e fix YAML template 2021-10-01 23:49:04 +02:00
Eyck Jentzsch 6acf73a40f add template to generate instruction YAML 2021-10-01 13:05:36 +02:00
Eyck Jentzsch 2f15d9676e fix unaligned instr fetch behavior 2021-09-30 19:27:46 +02:00
Eyck Jentzsch 4186723d37 add marchid setting to CoreDSL description 2021-09-30 19:26:21 +02:00
Eyck Jentzsch aa84a27a5b fix JALR alignment in description 2021-09-29 00:43:42 +02:00
Eyck Jentzsch 438e598a4a remove clutter from core descriptions, added instr alignment setting 2021-09-29 00:03:11 +02:00
Eyck Jentzsch 174259155d add support for non-compressed ISA 2021-09-23 21:09:52 +02:00
Eyck Jentzsch a3084456fd rework core definitions 2021-09-04 12:47:07 +02:00
Eyck Jentzsch adeffe47ad fix behavior of riscv_hart_mu_p to match TGC_D 2021-08-12 20:34:10 +02:00
Eyck Jentzsch d95846a849 fix trap handling if illegal fetch (PMP) and U-mode CSRs 2021-08-01 17:23:22 +02:00
Eyck Jentzsch e68918c2e8 fix instruction decode 2021-07-09 07:37:12 +02:00
Eyck Jentzsch 2f4b5bd9b2 fix detailed behavior of TGC_C 2021-07-06 21:19:36 +02:00
Eyck Jentzsch 23b9741adf refine and fix TGC_C iss to becoem compliant 2021-06-29 11:51:30 +02:00
Eyck Jentzsch e432dd8208 fix handling of exceptions while accessing address spaces 2021-06-07 22:22:36 +02:00
Eyck Jentzsch aaceecd5dc fix mu_p platform features and CSRs 2021-05-17 09:20:09 +02:00
Eyck Jentzsch cf7b62a3f9 update names 2021-05-13 15:54:48 +02:00
Eyck Jentzsch 32e4aa83b8 use extracted variables 2021-03-27 09:36:52 +00:00
Eyck Jentzsch 78c7064295 update groovy template to extract used registers 2021-03-26 08:24:45 +00:00
Eyck Jentzsch b0bcb7febb small fixes for robustness and readability 2021-03-22 22:47:30 +00:00
Eyck Jentzsch 4e0f20eba0 rework abort conditions 2021-03-17 19:32:57 +00:00
Eyck Jentzsch ff3fa19208 fix RVM description bugs 2021-03-13 10:46:41 +00:00
Eyck Jentzsch 80057eef32 fix RVC description bugs, remove paged fetch 2021-03-13 10:46:41 +00:00
Eyck Jentzsch f4ec21007b fix signedness issues 2021-03-11 16:12:28 +00:00
Eyck Jentzsch ac8eab6e25 update RISC-V desciptions 2021-03-10 17:31:10 +00:00
Eyck Jentzsch bea0dcc387 update missing XLEN 2021-03-09 11:03:37 +00:00
Eyck Jentzsch a6691bcd3c update generated code with correct sign extension 2021-03-09 10:21:36 +00:00
Eyck Jentzsch c171e3c1ba update CoreDSL descriptions 2021-03-07 10:51:15 +00:00
Eyck Jentzsch c251fe15d5 fix desscriptions to conform to ISA spec version 20191213 and TGF-C 2021-03-07 10:51:00 +00:00
Eyck Jentzsch dae8acb8a3 checkpoint before refactor 2021-03-06 07:17:42 +00:00
Eyck Jentzsch be0e7db185 fix templates to comply with CoreDSL2 2021-03-01 21:07:20 +00:00
Eyck Jentzsch 9534d58d01 regenerated sources and and add opcode enum to headers
Conflicts:
	gen_input/CoreDSL-Instruction-Set-Description
2021-03-01 06:26:33 +00:00
Eyck Jentzsch 1668df0531 regenerated sources and and add opcode enum to headers 2021-02-23 08:29:31 +00:00