|
|
17ee7b138d
|
update generated TGC-C VM
|
2021-09-29 00:44:17 +02:00 |
|
|
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438e598a4a
|
remove clutter from core descriptions, added instr alignment setting
|
2021-09-29 00:03:11 +02:00 |
|
|
|
174259155d
|
add support for non-compressed ISA
|
2021-09-23 21:09:52 +02:00 |
|
|
|
65b4db5eca
|
remove mcounteren in M-mode only platform
|
2021-09-18 11:40:00 +02:00 |
|
|
|
0fd82f1f3c
|
add tgc_d_xrb_mac to SC and C++ ISS
|
2021-09-04 13:04:34 +02:00 |
|
|
|
09b01af3fa
|
fix find_package use and debug access alignment check
|
2021-08-26 22:10:27 +02:00 |
|
|
|
2f05083cf0
|
fix elf loader and pmp check for debug accesses
|
2021-08-19 10:50:25 +02:00 |
|
|
|
e934049dd4
|
fix inconsistency due to PA adaptation
|
2021-08-16 17:55:14 +02:00 |
|
Eyck Jentzsch
|
94f796ebdb
|
add install target and PA compatibility
|
2021-08-16 17:02:31 +02:00 |
|
|
|
c8681096be
|
update vm_tgfs_c to match CoreDSL
|
2021-08-14 10:57:36 +02:00 |
|
|
|
15f46a87db
|
adapt core_complex to use scv-tr (scc commit id a3cde47)
|
2021-07-27 09:38:05 +02:00 |
|
|
|
e68918c2e8
|
fix instruction decode
|
2021-07-09 07:37:12 +02:00 |
|
|
|
2f4b5bd9b2
|
fix detailed behavior of TGC_C
|
2021-07-06 21:19:36 +02:00 |
|
|
|
23b9741adf
|
refine and fix TGC_C iss to becoem compliant
|
2021-06-29 11:51:30 +02:00 |
|
|
|
5d8da08ce5
|
fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
|
2021-06-26 14:30:36 +02:00 |
|
|
|
a249aea703
|
getting rid of the error: reference to 'wait' is ambiguous
|
2021-06-25 13:35:42 +02:00 |
|
|
|
e432dd8208
|
fix handling of exceptions while accessing address spaces
|
2021-06-07 22:22:36 +02:00 |
|
|
|
8c385647dd
|
remove redundant code from checked in generated sources
|
2021-05-26 23:06:31 +02:00 |
|
|
|
aaceecd5dc
|
fix mu_p platform features and CSRs
|
2021-05-17 09:20:09 +02:00 |
|
|
|
4b3f5a6b0c
|
add missing change
|
2021-05-16 16:44:30 +02:00 |
|
|
|
d41e1d816a
|
add factory for ISS and use it in main.cpp
|
2021-05-16 16:44:14 +02:00 |
|
|
|
a35974c9f5
|
make cpu type in core_complex configurable
|
2021-05-16 15:06:42 +02:00 |
|
|
|
9c456ba8f2
|
initial version of MU hart
|
2021-05-14 13:29:39 +02:00 |
|
|
|
c57884caee
|
small fix
|
2021-05-13 16:01:04 +02:00 |
|
|
|
cf7b62a3f9
|
update names
|
2021-05-13 15:54:48 +02:00 |
|
|
|
2f4cfb68dc
|
update to latest SCC
|
2021-04-07 18:56:46 +02:00 |
|
|
|
7009943106
|
fix wait for interrupt. Adapt for new SCC structure
|
2021-04-07 17:42:08 +02:00 |
|
|
|
32e4aa83b8
|
use extracted variables
|
2021-03-27 09:36:52 +00:00 |
|
|
|
78c7064295
|
update groovy template to extract used registers
|
2021-03-26 08:24:45 +00:00 |
|
|
|
ea3ff3c0cd
|
build with SCV lib
|
2021-03-23 11:57:47 +01:00 |
|
|
|
b0bcb7febb
|
small fixes for robustness and readability
|
2021-03-22 22:47:30 +00:00 |
|
|
|
51fbc34fb3
|
change namespace of core complex
|
2021-03-22 11:57:40 +00:00 |
|
|
|
4e0f20eba0
|
rework abort conditions
|
2021-03-17 19:32:57 +00:00 |
|
|
|
ff3fa19208
|
fix RVM description bugs
|
2021-03-13 10:46:41 +00:00 |
|
|
|
80057eef32
|
fix RVC description bugs, remove paged fetch
|
2021-03-13 10:46:41 +00:00 |
|
|
|
a5186ff88d
|
optional dependency to TGF_B_src target
|
2021-03-12 11:16:24 +01:00 |
|
|
|
f4ec21007b
|
fix signedness issues
|
2021-03-11 16:12:28 +00:00 |
|
|
|
768716b064
|
fix another missing XLEN
|
2021-03-09 11:07:56 +00:00 |
|
|
|
bea0dcc387
|
update missing XLEN
|
2021-03-09 11:03:37 +00:00 |
|
|
|
a6691bcd3c
|
update generated code with correct sign extension
|
2021-03-09 10:21:36 +00:00 |
|
|
|
40db74ce02
|
remove tgf_b code generation
|
2021-03-07 16:26:14 +00:00 |
|
|
|
c251fe15d5
|
fix desscriptions to conform to ISA spec version 20191213 and TGF-C
|
2021-03-07 10:51:00 +00:00 |
|
|
|
dae8acb8a3
|
checkpoint before refactor
|
2021-03-06 07:17:42 +00:00 |
|
|
|
f7cec99fa6
|
adapt to changes in SCC
|
2021-03-01 21:08:18 +00:00 |
|
|
|
be0e7db185
|
fix templates to comply with CoreDSL2
|
2021-03-01 21:07:20 +00:00 |
|
|
|
9534d58d01
|
regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
|
|
|
1668df0531
|
regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
|
|
|
337f1634c0
|
add mssing change
|
2021-02-15 18:01:46 +00:00 |
|
|
|
72b09472d5
|
update RISC-V descriptions
|
2021-02-15 18:01:33 +00:00 |
|
|
|
34bb8e62ae
|
generate working ISS from CoreDSL 2.0
|
2021-02-06 14:47:06 +00:00 |
|
|
|
c4da47cedd
|
integrate code generation into build process (first attempt)
|
2020-12-30 07:29:52 +00:00 |
|
|
|
ab554539e3
|
first version of tgf_c based on CoreDSL 2.0
|
2020-12-29 08:48:22 +00:00 |
|
|
|
43488676dd
|
Update TGF naming convention
|
2020-09-11 10:45:44 +02:00 |
|
|
|
969b408288
|
Implement MHARTID register
|
2020-09-04 15:37:21 +02:00 |
|
|
|
886b8f5716
|
TGF02 is a default core
|
2020-08-31 14:20:13 +02:00 |
|
|
|
9754e3953f
|
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
|
2020-08-24 15:01:54 +02:00 |
|
|
|
8fce0c4759
|
Generate TGF01 and TGF02 cores
|
2020-08-20 17:29:36 +02:00 |
|
|
|
71b976811b
|
add backend selection
|
2020-06-18 09:58:43 +02:00 |
|
|
|
edeff7add8
|
update log macros
|
2020-06-18 07:38:56 +02:00 |
|
|
|
e902936931
|
make interpreter default
|
2020-06-18 07:22:50 +02:00 |
|
|
|
55450f4900
|
[WIP] update dependencies in core desc
|
2020-06-18 06:18:59 +02:00 |
|
|
|
c619194465
|
[WIP] rework generator
|
2020-06-05 07:25:40 +02:00 |
|
|
|
abcfb75011
|
[WIP]
|
2020-05-31 16:41:04 +02:00 |
|
|
|
10797a473d
|
modernize build system and cleanup dependencies
|
2020-05-30 14:16:10 +02:00 |
|
|
|
0ff6ccf9e2
|
get all compile clean
|
2020-05-30 11:27:44 +02:00 |
|
|
|
0698b604fd
|
add TCC backend
|
2020-05-29 08:52:55 +02:00 |
|
|
|
264053a8d6
|
[WIP] add next increment for TCC
|
2020-04-17 19:23:43 +02:00 |
|
|
|
ae1c0b99fe
|
[WIP] basic infrastructure working
|
2020-04-13 17:03:50 +02:00 |
|
|
|
8cdf50d69e
|
[WIP] implement basic infrastructure
|
2020-04-12 12:44:30 +02:00 |
|
|
|
50663a2fbc
|
[WIP] integrate tcc conan package
|
2020-04-10 17:14:04 +02:00 |
|
|
|
15f4c059e6
|
[WIP] first working version
|
2020-01-12 18:19:48 +01:00 |
|
|
|
e483887c43
|
[WIP] Cleanup of namespaces etc to get compile clean
|
2020-01-10 11:12:20 +01:00 |
|
|
|
fd2e40bfd2
|
Initial setup
|
2020-01-10 07:24:00 +01:00 |
|
|
|
116ed9bb5c
|
[WIP] started to add TinyCC backend
|
2020-01-09 19:43:17 +01:00 |
|
|
|
8b9775e06b
|
Changed namespaces for LLVM related stuff
|
2020-01-07 16:38:31 +01:00 |
|
|
|
d037141d98
|
Fixed C++11 compatibility
|
2019-07-16 15:52:34 +02:00 |
|
|
|
1947a2114f
|
Fixed FMT header define
|
2019-07-14 16:51:14 +02:00 |
|
|
|
7f06bba239
|
Fixed time csr handling
|
2019-06-28 20:58:02 +02:00 |
|
|
|
2758933c16
|
Modernized CMake
|
2019-06-11 19:22:07 +00:00 |
|
|
|
67d9beb7bd
|
reorganized layout to only contain risc-v stuff
|
2019-06-11 16:49:37 +00:00 |
|
