DBT-RISE/DBT-RISE-TGC
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add install target and PA compatibility

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This commit is contained in:
Eyck Jentzsch
2021-08-16 16:59:23 +02:00
parent 836ba269e3
commit 94f796ebdb
6 changed files with 254 additions and 51 deletions
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85
src/sysc/core_complex.cpp
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@ -66,6 +66,12 @@ if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend
using namespace scv_tr;
#endif
#ifndef CWR_SYSTEMC
#define GET_PROP_VALUE(P) P.get_value()
#else
#define GET_PROP_VALUE(P) P.getValue()
#endif
namespace sysc {
namespace tgfs {
using namespace std;
@ -137,6 +143,7 @@ public:
}
status read_csr(unsigned addr, reg_t &val) override {
#ifndef CWR_SYSTEMC
if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){
uint64_t time_val;
bool ret = owner->mtime_o->nb_peek(time_val);
@ -147,6 +154,17 @@ public:
val = static_cast<reg_t>(time_val >> 32);
}
return ret?Ok:Err;
#else
if((addr==arch::time || addr==arch::timeh)){
uint64_t time_val = owner->mtime_i.read();
if (addr == iss::arch::time) {
val = static_cast<reg_t>(time_val);
} else if (addr == iss::arch::timeh) {
if (sizeof(reg_t) != 4) return iss::Err;
val = static_cast<reg_t>(time_val >> 32);
}
return Ok;
#endif
} else {
return PLAT::read_csr(addr, val);
}
@ -297,13 +315,19 @@ struct core_trace {
scv_tr_handle tr_handle;
};
SC_HAS_PROCESS(core_complex);// NOLINT
#ifndef CWR_SYSTEMC
core_complex::core_complex(sc_module_name name)
: sc_module(name)
, read_lut(tlm_dmi_ext())
, write_lut(tlm_dmi_ext())
, trc(new core_trace)
{
SC_HAS_PROCESS(core_complex);// NOLINT
init();
}
#endif
void core_complex::init(){
trc=new core_trace();
initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
auto lut_entry = read_lut.getEntry(start);
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
@ -316,8 +340,6 @@ core_complex::core_complex(sc_module_name name)
});
SC_THREAD(run);
SC_METHOD(clk_cb);
sensitive << clk_i;
SC_METHOD(rst_cb);
sensitive << rst_i;
SC_METHOD(sw_irq_cb);
@ -327,29 +349,48 @@ core_complex::core_complex(sc_module_name name)
SC_METHOD(global_irq_cb);
sensitive << global_irq_i;
trc->m_db=scv_tr_db::get_default_db();
SC_METHOD(forward);
#ifndef CWR_SYSTEMC
sensitive<<clk_i;
#else
sensitive<<curr_clk;
t2t.reset(new scc::tick2time{"t2t"});
t2t->clk_i(clk_i);
t2t->clk_o(curr_clk);
#endif
}
core_complex::~core_complex() = default;
core_complex::~core_complex(){
delete cpu;
delete trc;
}
void core_complex::trace(sc_trace_file *trf) const {}
void core_complex::before_end_of_elaboration() {
SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<backend.get_value()<<" backend";
cpu = scc::make_unique<core_wrapper>(this);
cpu->create_cpu(core_type.get_value(), backend.get_value(), gdb_server_port.get_value(), mhartid.get_value());
SCCDEBUG(SCMOD)<<"instantiating iss::arch::tgf with "<<GET_PROP_VALUE(backend)<<" backend";
// cpu = scc::make_unique<core_wrapper>(this);
cpu = new core_wrapper(this);
cpu->create_cpu(GET_PROP_VALUE(core_type), GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
sc_assert(cpu->vm!=nullptr);
cpu->vm->setDisassEnabled(enable_disass.get_value() || trc->m_db != nullptr);
cpu->vm->setDisassEnabled(GET_PROP_VALUE(enable_disass) || trc->m_db != nullptr);
}
void core_complex::start_of_simulation() {
quantum_keeper.reset();
if (elf_file.get_value().size() > 0) {
istringstream is(elf_file.get_value());
if (GET_PROP_VALUE(elf_file).size() > 0) {
istringstream is(GET_PROP_VALUE(elf_file));
string s;
while (getline(is, s, ',')) {
std::pair<uint64_t, bool> start_addr = cpu->load_file(s);
#ifndef CWR_SYSTEMC
if (reset_address.is_default_value() && start_addr.second == true)
reset_address.set_value(start_addr.first);
#else
if (start_addr.second == true)
reset_address=start_addr.first;
#endif
}
}
if (trc->m_db != nullptr && trc->stream_handle == nullptr) {
@ -371,9 +412,18 @@ bool core_complex::disass_output(uint64_t pc, const std::string instr_str) {
return true;
}
void core_complex::clk_cb() {
curr_clk = clk_i.read();
if (curr_clk == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
void core_complex::forward() {
#ifndef CWR_SYSTEMC
set_clock_period(clk_i.read());
#else
set_clock_period(curr_clk.read());
#endif
}
void core_complex::set_clock_period(sc_core::sc_time period) {
curr_clk = period;
if (period == SC_ZERO_TIME) cpu->set_interrupt_execution(true);
}
void core_complex::rst_cb() {
@ -390,11 +440,11 @@ void core_complex::run() {
wait(SC_ZERO_TIME); // separate from elaboration phase
do {
if (rst_i.read()) {
cpu->reset(reset_address.get_value());
cpu->reset(GET_PROP_VALUE(reset_address));
wait(rst_i.negedge_event());
}
while (clk_i.read() == SC_ZERO_TIME) {
wait(clk_i.value_changed_event());
while (curr_clk.read() == SC_ZERO_TIME) {
wait(curr_clk.value_changed_event());
}
cpu->set_interrupt_execution(false);
cpu->start();
@ -531,6 +581,5 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
return initiator->transport_dbg(gp) == length;
}
}
} /* namespace SiFive */
} /* namespace sysc */