DBT-RISE/DBT-RISE-TGC
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remove clutter from core descriptions, added instr alignment setting

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This commit is contained in:
Eyck Jentzsch
2021-09-29 00:03:11 +02:00
parent 174259155d
commit 438e598a4a
7 changed files with 57 additions and 25 deletions
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60
src/vm/interp/vm_tgc_c.cpp
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@ -467,8 +467,13 @@ private:
// execute instruction
try {
{
if(rd != 0) *(X+rd) = *PC + 4;
pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = *PC + 4;
pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
}
}
} catch(...){}
// post execution stuff
@ -513,8 +518,13 @@ private:
try {
{
int32_t new_pc = *(X+rs1) + (int16_t)sext<12>(imm);
if(rd != 0) *(X+rd) = *PC + 4;
pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
if(new_pc % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = *PC + 4;
pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
}
}
} catch(...){}
// post execution stuff
@ -557,7 +567,12 @@ private:
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
{
if(*(X+rs1) == *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
}
} catch(...){}
// post execution stuff
if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0, 0);
@ -599,7 +614,12 @@ private:
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
{
if(*(X+rs1) != *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
}
} catch(...){}
// post execution stuff
if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0, 0);
@ -641,7 +661,12 @@ private:
*NEXT_PC = *PC + 4;
// execute instruction
try {
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
{
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
}
} catch(...){}
// post execution stuff
if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0, 0);
@ -683,7 +708,12 @@ private:
*NEXT_PC = *PC + 4;
// execute instruction
try {
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
{
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
}
} catch(...){}
// post execution stuff
if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0, 0);
@ -725,7 +755,12 @@ private:
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
{
if(*(X+rs1) < *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
}
} catch(...){}
// post execution stuff
if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0, 0);
@ -767,7 +802,12 @@ private:
*NEXT_PC = *PC + 4;
// execute instruction
try {
if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
{
if(*(X+rs1) >= *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
}
} catch(...){}
// post execution stuff
if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0, 0);