 Eyck Jentzsch
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98b418ff43
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fix JSON reading
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2022-02-01 19:28:11 +01:00 |
|
Eyck Jentzsch
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059bd0d371
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rework cycle estimation
|
2022-02-01 19:03:45 +01:00 |
|
Eyck Jentzsch
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ef2a4df925
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simplify spawn block handling
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2022-01-31 23:40:31 +01:00 |
 Eyck-Alexander Jentzsch
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7578906310
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adds coverage plugin
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2022-01-31 21:38:18 +01:00 |
|
Eyck Jentzsch
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afe8905ac9
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fix else-ambiguity in CoreDSL description
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2022-01-31 20:30:46 +01:00 |
|
Eyck-Alexander Jentzsch
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ecc6091d1e
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cleans up source code to remove clang compiler warnings
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2022-01-19 08:01:15 +01:00 |
|
Eyck Jentzsch
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3563ba80d0
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add spawn blocks
|
2022-01-12 07:21:16 +01:00 |
|
Eyck Jentzsch
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09955be90f
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update gitignore
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2021-12-05 08:45:49 +01:00 |
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Eyck Jentzsch
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dd4c19a15c
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add option to configure number of irq
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2021-12-01 12:56:36 +01:00 |
|
Eyck Jentzsch
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07d5af1dde
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fix stand-alone ISS compilation to include all generated cores
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2021-11-26 17:56:40 +01:00 |
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Eyck Jentzsch
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6f8595759e
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make tgc-sim include all available ISS
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2021-11-25 20:00:27 +01:00 |
 Maribel Gomez
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86da31033c
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correct size usage in pmp addr checks
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2021-11-22 15:15:47 +01:00 |
|
Maribel Gomez
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974d103381
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fix pmpcfg register write
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2021-11-22 10:49:29 +01:00 |
|
Eyck Jentzsch
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309758b994
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fix clic_cfg access scheme
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2021-11-17 07:59:02 +01:00 |
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Eyck Jentzsch
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965929d1eb
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remove descriptions
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2021-11-15 09:30:16 +01:00 |
|
Eyck Jentzsch
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d47375a70e
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fix ebreak CSR update
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2021-11-13 12:47:23 +01:00 |
|
Eyck Jentzsch
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d31b4ef5a8
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fix MISA val
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2021-11-11 12:58:57 +01:00 |
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Eyck Jentzsch
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7452c5df43
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add TGC_D_XRB_NN definition
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2021-11-11 12:16:35 +01:00 |
|
Eyck Jentzsch
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43d7b99905
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revert pmp check implementation
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2021-11-11 09:58:19 +01:00 |
|
Eyck Jentzsch
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f90c48e881
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adapt to changed define names
|
2021-11-11 08:33:35 +01:00 |
|
Eyck Jentzsch
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2d7973520b
|
fix mip handling
|
2021-11-09 19:47:34 +01:00 |
|
Eyck Jentzsch
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fd98ad95f6
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rework PMP check and fix MISA for TGC_D
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2021-11-09 15:55:22 +01:00 |
|
Eyck Jentzsch
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bfa8166223
|
fix wrong template class name
|
2021-11-08 10:44:33 +01:00 |
|
Eyck Jentzsch
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c42e336509
|
fix proper debug mode handling (#267 & #268)
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2021-11-07 17:48:44 +01:00 |
|
Eyck Jentzsch
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49d09a05d7
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fix access rights to debug CSR register (#268)
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2021-11-07 16:45:10 +01:00 |
|
Eyck Jentzsch
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459794b863
|
add proper handling of store access fault (hart_mu_p)
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2021-11-06 13:29:11 +01:00 |
|
Eyck Jentzsch
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039746112b
|
fix exception behavior
|
2021-11-02 15:10:20 +01:00 |
|
Eyck Jentzsch
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ac6d7ea5d4
|
add debug feature to platform
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2021-11-02 11:13:29 +01:00 |
 Stanislaw Kaushanski
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a89f00da19
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fix plugins parameter utilization
|
2021-11-02 11:03:17 +01:00 |
|
Stanislaw Kaushanski
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ff04ee7807
|
get rid of the Boost::thread linking
|
2021-11-02 10:24:34 +01:00 |
|
Eyck Jentzsch
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8b6e3abd23
|
fix hard-code arch in templates
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2021-10-30 13:37:17 +02:00 |
|
Eyck Jentzsch
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1616f0ac90
|
remove deprecated functions
|
2021-10-30 12:57:08 +02:00 |
|
Eyck Jentzsch
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a20f39e847
|
update core definitions to include Zicsr and Zifencei (#276)
|
2021-10-30 12:56:31 +02:00 |
|
Eyck Jentzsch
|
334d3fb296
|
adapt to SCC changes
|
2021-10-21 22:53:16 +02:00 |
|
Eyck Jentzsch
|
eb2ca33e5a
|
remove unused sources
|
2021-10-12 15:17:56 +02:00 |
|
Eyck Jentzsch
|
0ea4cba1ca
|
add dynamic plugin loading
|
2021-10-12 14:24:55 +02:00 |
|
Eyck Jentzsch
|
1d13c8196e
|
fix wrong PGMASK usage
|
2021-10-11 10:40:01 +02:00 |
|
Eyck Jentzsch
|
ee6e1d4092
|
Merge remote-tracking branch 'origin/msvc_compat' into develop
Conflicts:
src/sysc/core_complex.cpp
|
2021-10-11 09:42:40 +02:00 |
|
Eyck Jentzsch
|
c8679fca85
|
remove MSVC warning
|
2021-10-10 19:56:33 +02:00 |
|
Eyck Jentzsch
|
f0ada1ba8c
|
add MSVC 16 compatibility
|
2021-10-10 19:06:41 +02:00 |
|
Eyck Jentzsch
|
b17682e50e
|
fix YAML template
|
2021-10-01 23:49:04 +02:00 |
|
Eyck Jentzsch
|
5866acf565
|
update .gitignore
|
2021-10-01 13:06:10 +02:00 |
|
Eyck Jentzsch
|
6acf73a40f
|
add template to generate instruction YAML
|
2021-10-01 13:05:36 +02:00 |
|
Eyck Jentzsch
|
2f15d9676e
|
fix unaligned instr fetch behavior
|
2021-09-30 19:27:46 +02:00 |
|
Eyck Jentzsch
|
d78fcc48e5
|
use marchid in platform
|
2021-09-30 19:27:03 +02:00 |
|
Eyck Jentzsch
|
4186723d37
|
add marchid setting to CoreDSL description
|
2021-09-30 19:26:21 +02:00 |
|
Eyck Jentzsch
|
17ee7b138d
|
update generated TGC-C VM
|
2021-09-29 00:44:17 +02:00 |
|
Eyck Jentzsch
|
aa84a27a5b
|
fix JALR alignment in description
|
2021-09-29 00:43:42 +02:00 |
|
Eyck Jentzsch
|
438e598a4a
|
remove clutter from core descriptions, added instr alignment setting
|
2021-09-29 00:03:11 +02:00 |
|
Eyck Jentzsch
|
174259155d
|
add support for non-compressed ISA
|
2021-09-23 21:09:52 +02:00 |