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ee2ded931d
|
adds remaining register offsets
|
2023-05-14 17:16:42 +02:00 |
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|
95ba5c901a
|
re-introduces last_branch register
|
2023-05-14 17:00:37 +02:00 |
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|
|
00b0f101ac
|
adapts to changes of instrumentation interface in dbt-rise-core
|
2023-04-28 20:38:07 +02:00 |
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|
d881cb6e63
|
fix data width of generated code
|
2023-03-26 12:12:34 +02:00 |
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|
207dbf1071
|
fixes out of range access for register alias names
|
2023-02-17 06:28:30 +01:00 |
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|
|
65dca13b42
|
fixes WFI miss of interrupt
|
2023-01-14 17:40:21 +01:00 |
|
|
|
7113683ee0
|
moves pending interrupt check before handling trap thus saving 1 cycle
|
2022-10-15 10:47:35 +02:00 |
|
|
|
00e02bf565
|
adds support for different branch types in tracing
|
2022-08-08 06:30:37 +02:00 |
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|
|
0833198d34
|
aads missing windows compat firx to template
|
2022-07-23 14:36:23 +02:00 |
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|
|
4876f18ba9
|
adds windows compatibility fixes
|
2022-07-18 11:43:42 +02:00 |
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|
feaa49d367
|
removes decoder again as there is some issue
|
2022-06-20 00:39:11 +02:00 |
|
|
|
18f33b4a68
|
fixes ordering of instructions for decoding
|
2022-06-19 16:52:29 +02:00 |
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|
|
f096b15dbd
|
factors decoder into separate component
|
2022-06-19 13:17:31 +02:00 |
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|
|
5d481eb79d
|
fix generation of non-exception code
|
2022-05-30 22:04:16 +02:00 |
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|
|
52ed8b81a6
|
fixed template to work with previous code generator
|
2022-05-30 14:08:02 +02:00 |
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|
|
0c542d42aa
|
separate generated sources
|
2022-05-21 12:48:28 +02:00 |
|
|
|
df16378605
|
update template for changed code generator
|
2022-05-18 19:10:34 +02:00 |
|
|
|
e88f309ea2
|
add lz4 compression to pctrace
|
2022-05-07 17:22:06 +02:00 |
|
|
|
9d9008a3a2
|
fix pointer mess
|
2022-04-26 15:35:17 +02:00 |
|
|
|
a92b84bef4
|
add code word access for ISS plugins
|
2022-04-25 14:18:19 +02:00 |
|
|
|
2e670c4d03
|
change interpreter structure
|
2022-03-06 15:11:38 +01:00 |
|
|
|
3d32c33333
|
update gitignore
|
2022-03-05 20:59:45 +01:00 |
|
|
|
521f40a3d6
|
refactored interpreter backend structure
|
2022-03-05 20:59:17 +01:00 |
|
|
|
b8fa5fbbda
|
adapt to extended instrumentation interface
|
2022-02-09 21:01:17 +01:00 |
|
|
|
68b5697c8f
|
Fix cycles JSON template
|
2022-02-01 21:48:56 +01:00 |
|
|
|
059bd0d371
|
rework cycle estimation
|
2022-02-01 19:03:45 +01:00 |
|
|
|
ef2a4df925
|
simplify spawn block handling
|
2022-01-31 23:40:31 +01:00 |
|
|
|
afe8905ac9
|
fix else-ambiguity in CoreDSL description
|
2022-01-31 20:30:46 +01:00 |
|
|
|
3563ba80d0
|
add spawn blocks
|
2022-01-12 07:21:16 +01:00 |
|
|
|
07d5af1dde
|
fix stand-alone ISS compilation to include all generated cores
|
2021-11-26 17:56:40 +01:00 |
|
|
|
965929d1eb
|
remove descriptions
|
2021-11-15 09:30:16 +01:00 |
|
|
|
d31b4ef5a8
|
fix MISA val
|
2021-11-11 12:58:57 +01:00 |
|
|
|
7452c5df43
|
add TGC_D_XRB_NN definition
|
2021-11-11 12:16:35 +01:00 |
|
|
|
fd98ad95f6
|
rework PMP check and fix MISA for TGC_D
|
2021-11-09 15:55:22 +01:00 |
|
|
|
c42e336509
|
fix proper debug mode handling (#267 & #268)
|
2021-11-07 17:48:44 +01:00 |
|
|
|
8b6e3abd23
|
fix hard-code arch in templates
|
2021-10-30 13:37:17 +02:00 |
|
|
|
1616f0ac90
|
remove deprecated functions
|
2021-10-30 12:57:08 +02:00 |
|
|
|
a20f39e847
|
update core definitions to include Zicsr and Zifencei (#276)
|
2021-10-30 12:56:31 +02:00 |
|
|
|
334d3fb296
|
adapt to SCC changes
|
2021-10-21 22:53:16 +02:00 |
|
|
|
1d13c8196e
|
fix wrong PGMASK usage
|
2021-10-11 10:40:01 +02:00 |
|
|
|
b17682e50e
|
fix YAML template
|
2021-10-01 23:49:04 +02:00 |
|
|
|
6acf73a40f
|
add template to generate instruction YAML
|
2021-10-01 13:05:36 +02:00 |
|
|
|
2f15d9676e
|
fix unaligned instr fetch behavior
|
2021-09-30 19:27:46 +02:00 |
|
|
|
4186723d37
|
add marchid setting to CoreDSL description
|
2021-09-30 19:26:21 +02:00 |
|
|
|
aa84a27a5b
|
fix JALR alignment in description
|
2021-09-29 00:43:42 +02:00 |
|
|
|
438e598a4a
|
remove clutter from core descriptions, added instr alignment setting
|
2021-09-29 00:03:11 +02:00 |
|
|
|
174259155d
|
add support for non-compressed ISA
|
2021-09-23 21:09:52 +02:00 |
|
|
|
a3084456fd
|
rework core definitions
|
2021-09-04 12:47:07 +02:00 |
|
|
|
adeffe47ad
|
fix behavior of riscv_hart_mu_p to match TGC_D
|
2021-08-12 20:34:10 +02:00 |
|
|
|
d95846a849
|
fix trap handling if illegal fetch (PMP) and U-mode CSRs
|
2021-08-01 17:23:22 +02:00 |
|
