DBT-RISE/DBT-RISE-TGC
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add code word access for ISS plugins

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Eyck Jentzsch
2022-04-25 14:18:19 +02:00
parent 477c530847
commit a92b84bef4
9 changed files with 42 additions and 33 deletions
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6
gen_input/TGC_C.core_desc
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@ -1,6 +1,6 @@
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
import "RV32I.core_desc"
import "RVM.core_desc"
import "RVC.core_desc"
Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {

2
gen_input/templates/CORENAME.cpp.gtl
View File

@ -33,7 +33,7 @@
def getRegisterSizes(){
def regs = registers.collect{it.size}
regs[-1]=64 // correct for NEXT_PC
regs+=[32, 32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
return regs
}
%>

6
gen_input/templates/CORENAME.h.gtl
View File

@ -37,7 +37,7 @@ def nativeTypeSize(int size){
}
def getRegisterSizes(){
def regs = registers.collect{nativeTypeSize(it.size)}
regs+=[32,32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
return regs
}
def getRegisterOffsets(){
@ -96,7 +96,8 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
PENDING_TRAP,
ICOUNT,
CYCLE,
INSTRET
INSTRET,
INSTRUCTION
};
using reg_t = uint${addrDataWidth}_t;
@ -170,6 +171,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t instret = 0;
uint32_t instruction = 0;
uint32_t last_branch;
} reg;
#pragma pack(pop)

7
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -277,9 +277,6 @@ typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t
template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
// we fetch at max 4 byte, alignment is 2
code_word_t instr = 0;
auto *const data = (uint8_t *)&instr;
auto pc=start;
auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@ -287,6 +284,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
auto* icount = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]);
auto* instret = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]);
auto *const instruction = reinterpret_cast<code_word_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRUCTION]);
// we fetch at max 4 byte, alignment is 2
auto *const data = reinterpret_cast<uint8_t*>(instruction);
auto& instr = *instruction;
while(!this->core.should_stop() &&
!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){