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d95846a849
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fix trap handling if illegal fetch (PMP) and U-mode CSRs
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2021-08-01 17:23:22 +02:00 |
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af887c286f
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fix for #2
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2021-07-28 09:09:08 +02:00 |
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d7bddd825c
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add clic CSRs
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2021-07-27 10:47:48 +02:00 |
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d0f3a120fd
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fix naming in MU wrapper
|
2021-07-19 16:26:23 +02:00 |
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c592a26346
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fix mepc mask
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2021-07-09 13:01:22 +02:00 |
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e68918c2e8
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fix instruction decode
|
2021-07-09 07:37:12 +02:00 |
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473f8a5a17
|
fix privilege behavior
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2021-07-07 11:30:00 +02:00 |
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2f4b5bd9b2
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fix detailed behavior of TGC_C
|
2021-07-06 21:19:36 +02:00 |
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23b9741adf
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refine and fix TGC_C iss to becoem compliant
|
2021-06-29 11:51:30 +02:00 |
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5d8da08ce5
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fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
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2021-06-26 14:30:36 +02:00 |
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e432dd8208
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fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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a35974c9f5
|
make cpu type in core_complex configurable
|
2021-05-16 15:06:42 +02:00 |
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9c456ba8f2
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initial version of MU hart
|
2021-05-14 13:29:39 +02:00 |
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cf7b62a3f9
|
update names
|
2021-05-13 15:54:48 +02:00 |
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391f9bb808
|
remove unneeded constants
|
2021-05-08 15:14:19 +02:00 |
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ef02dba8c5
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add read misa callback
|
2021-04-09 11:20:51 +02:00 |
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7009943106
|
fix wait for interrupt. Adapt for new SCC structure
|
2021-04-07 17:42:08 +02:00 |
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f4ec21007b
|
fix signedness issues
|
2021-03-11 16:12:28 +00:00 |
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40db74ce02
|
remove tgf_b code generation
|
2021-03-07 16:26:14 +00:00 |
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c251fe15d5
|
fix desscriptions to conform to ISA spec version 20191213 and TGF-C
|
2021-03-07 10:51:00 +00:00 |
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dae8acb8a3
|
checkpoint before refactor
|
2021-03-06 07:17:42 +00:00 |
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be0e7db185
|
fix templates to comply with CoreDSL2
|
2021-03-01 21:07:20 +00:00 |
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4aa26b85a0
|
adapt to change in SCC
|
2021-03-01 06:36:27 +00:00 |
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9534d58d01
|
regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
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1668df0531
|
regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
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d07c8679ed
|
update core definition
|
2021-02-15 18:14:52 +00:00 |
|
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72b09472d5
|
update RISC-V descriptions
|
2021-02-15 18:01:33 +00:00 |
|
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|
34bb8e62ae
|
generate working ISS from CoreDSL 2.0
|
2021-02-06 14:47:06 +00:00 |
|
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|
da7e29fbb7
|
update definitions of derived constants
|
2021-01-01 09:19:48 +00:00 |
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c4da47cedd
|
integrate code generation into build process (first attempt)
|
2020-12-30 07:29:52 +00:00 |
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ab554539e3
|
first version of tgf_c based on CoreDSL 2.0
|
2020-12-29 08:48:22 +00:00 |
|
|
|
43488676dd
|
Update TGF naming convention
|
2020-09-11 10:45:44 +02:00 |
|
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|
f3d578f050
|
Remove 64bit support
|
2020-09-07 14:30:19 +02:00 |
|
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|
293c396a0d
|
update core wrapper: remove virtual memory support
|
2020-09-07 13:29:45 +02:00 |
|
|
|
6f3963a473
|
Strip down privileged modes. Only machine mode is supported
|
2020-09-07 11:54:45 +02:00 |
|
|
|
969b408288
|
Implement MHARTID register
|
2020-09-04 15:37:21 +02:00 |
|
|
|
9754e3953f
|
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
|
2020-08-24 15:01:54 +02:00 |
|
|
|
8fce0c4759
|
Generate TGF01 and TGF02 cores
|
2020-08-20 17:29:36 +02:00 |
|
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|
abcfb75011
|
[WIP]
|
2020-05-31 16:41:04 +02:00 |
|
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|
0ff6ccf9e2
|
get all compile clean
|
2020-05-30 11:27:44 +02:00 |
|
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|
0698b604fd
|
add TCC backend
|
2020-05-29 08:52:55 +02:00 |
|
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264053a8d6
|
[WIP] add next increment for TCC
|
2020-04-17 19:23:43 +02:00 |
|
|
|
15f4c059e6
|
[WIP] first working version
|
2020-01-12 18:19:48 +01:00 |
|
|
|
116ed9bb5c
|
[WIP] started to add TinyCC backend
|
2020-01-09 19:43:17 +01:00 |
|
|
|
d037141d98
|
Fixed C++11 compatibility
|
2019-07-16 15:52:34 +02:00 |
|
|
|
1947a2114f
|
Fixed FMT header define
|
2019-07-14 16:51:14 +02:00 |
|
|
|
67d9beb7bd
|
reorganized layout to only contain risc-v stuff
|
2019-06-11 16:49:37 +00:00 |
|
