Commit Graph

197 Commits

Author SHA1 Message Date
c15cdb0955 expands return values of jit creating functions to inhibit endless trapping 2024-08-14 11:49:59 +02:00
b5341700aa updates template and adds braces when using conditions 2024-08-13 08:55:14 +02:00
0b5062d21c adds fp_functions here to remove dependencies in dbt-rise-core 2024-08-09 11:56:32 +02:00
fbca690b3b replaces gen_wait, updates template to include fp_functions when necessary 2024-08-08 12:57:08 +02:00
235a7e6e24 updates template 2024-08-08 11:08:28 +02:00
9c51d6eade improves interp, only calls decode once per instr 2024-08-07 09:20:11 +02:00
2878dca6b5 updates templates 2024-08-06 08:32:05 +02:00
933f08494c removes C++17 dependency from asmjit backend 2024-08-04 17:41:49 +02:00
39d2518fdd checkin: tgc5f builds and runs through 2024-07-31 12:30:41 +02:00
04b7a09b19 updates date in templates 2024-07-25 17:25:12 +02:00
72b11beac5 moves decoder to dbt-rise-core 2024-07-25 10:13:38 +02:00
c6b99cd155 introduces new decoder to interp backend 2024-07-24 12:28:35 +02:00
0d6bf924ed changes jh.globals from map to vector 2024-07-23 15:45:51 +02:00
86de536c8f changes jh globals to seperate riscv specifics 2024-07-23 14:35:31 +02:00
051dd5e2d3 updates templates for decoder in seperate class, adds again generated templates 2024-07-23 13:46:10 +02:00
60808c8649 corrects template since util fns are no longer vm_base members 2024-07-23 11:29:56 +02:00
0432803d82 updates templates and vm impls for better LAST_BRANCH handling 2024-07-22 09:04:17 +02:00
d42d2ce533 corrects illegal instruction for llvm 2024-07-18 14:04:23 +02:00
e1b6cab890 removes setting of NEXT_PC to max when trapping in llvm and asmjit, adds default disass to llvm 2024-07-18 12:02:40 +02:00
8361f88718 removes setting of NEXT_PC to max if trap 2024-07-18 11:37:53 +02:00
2ec7ea4b41 removes leftover gen_sync in asmjit 2024-07-17 22:39:12 +02:00
b24965d321 corrects gen_sync update order, improves illegal instruction 2024-07-17 20:52:01 +02:00
244bf6d2f2 corrects gen_sync before trap check, improves illegal_instruction 2024-07-17 20:25:49 +02:00
1a4465a371 changes template: adds correct illegal instruction, reorders gen_sync to allow correct instr id eve when trapping, adds newly generated vm 2024-07-17 19:59:01 +02:00
fa82a50824 fixes typo in templates 2024-07-17 17:24:17 +02:00
6dc17857da updates template 2024-07-17 15:36:08 +02:00
ac1a26a10c integrates new tval changes into llvm 2024-07-17 14:17:02 +02:00
7a199e122d integrates new tval changes into asmjit 2024-07-17 09:42:12 +02:00
d8c3d2e19c integrates new tval changes into tcc 2024-07-16 17:35:23 +02:00
375755999a integrates new tval changes 2024-07-16 15:32:35 +02:00
55b0cea94f changes vm_base util API 2024-07-10 12:51:59 +02:00
5b17599aa2 allows usage of std::variants 2024-07-10 12:51:59 +02:00
4cfb15c7cd Asmjit and interp working 2024-07-10 12:51:31 +02:00
fd303c8343 fixes asmjit deprecation warning 2024-07-05 07:51:37 +02:00
346b177a87 extends finishing conditions 2024-07-05 05:52:29 +02:00
d4ec131fa7 change COUNT_LIMIT to ICOUNT_LIMIT 2024-07-04 10:46:24 +02:00
36b076774e Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2024-06-21 13:35:30 +02:00
482a4ec253 fixes semihosting callbacks in templates 2024-06-21 13:35:25 +02:00
2fb28364c5 fixes remaining templates 2024-06-21 10:49:36 +02:00
8460f4ab7f updates templates to re-enable interactive debugging of generator 2024-06-21 10:46:11 +02:00
3fd51cc68c fixes templates 2024-06-14 19:54:33 +02:00
e2da306eee fixes semihosting cb registration 2024-05-31 10:45:28 +02:00
58fb815f32 fixes gen_raise in tcc 2024-05-20 10:34:23 +02:00
a27850f841 adds verilog literal and illegal_instr to asmjit 2024-05-18 21:00:21 +02:00
fb330cddea llvm passes act 2024-05-18 19:33:57 +02:00
ee6a11dae6 fixes typo 2024-05-09 20:54:30 +02:00
2e27b025cc improves dump-ir comments 2024-05-09 13:47:36 +02:00
3422c7cd5c optimizes writebacks 2024-05-08 15:18:38 +02:00
ad79a28705 wip checkin 2024-04-30 19:21:27 +02:00
1e6a0086e9 adds disass functionality 2024-03-07 13:58:08 +01:00