DBT-RISE/DBT-RISE-TGC
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updates templates

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This commit is contained in:
Eyck-Alexander Jentzsch 2024-08-06 08:31:28 +02:00
parent c28e8fd00c
commit 2878dca6b5
2 changed files with 10 additions and 1 deletions
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1
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -279,6 +279,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */<%instr.disass.eachLine{%>
${it}<%}%>
this->core.disass_output(pc.val, mnemonic);
}
// used registers<%instr.usedVariables.each{ k,v->
if(v.isArray) {%>

10
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -85,7 +85,11 @@ protected:
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%
def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
<%}%>
void setup_module(std::string m) override {
super::setup_module(m);
}
@ -133,6 +137,9 @@ protected:
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
@ -163,6 +170,7 @@ private:
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */<%instr.disass.eachLine{%>
${it}<%}%>
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
}
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
pc=pc+ ${instr.length/8};