updates templates
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c28e8fd00c
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@ -279,6 +279,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */<%instr.disass.eachLine{%>
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${it}<%}%>
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this->core.disass_output(pc.val, mnemonic);
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}
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// used registers<%instr.usedVariables.each{ k,v->
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if(v.isArray) {%>
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@ -85,7 +85,11 @@ protected:
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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<%
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def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
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<%}%>
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void setup_module(std::string m) override {
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super::setup_module(m);
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}
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@ -133,6 +137,9 @@ protected:
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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<%functions.each{ it.eachLine { %>
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${it}<%}%>
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<%}%>
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private:
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/****************************************************************************
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* start opcode definitions
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@ -163,6 +170,7 @@ private:
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */<%instr.disass.eachLine{%>
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${it}<%}%>
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tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
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}
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auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
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pc=pc+ ${instr.length/8};
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