DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

optimizes writebacks

Browse Source
This commit is contained in:
Eyck-Alexander Jentzsch
2024-05-08 15:18:38 +02:00
parent ad79a28705
commit 3422c7cd5c
2 changed files with 9 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
gen_input/templates/asmjit/CORENAME.cpp.gtl
View File

@ -284,11 +284,6 @@ void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
cc.cmp(current_trap_state, 0);
cc.jne(jh.trap_entry);
// TODO: Does not need to be done for every instruction, only when needed (by plugin)
cc.comment("//write back regs to mem");
write_reg_to_mem(jh, jh.pc, traits::PC);
write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
}
template <typename ARCH>
void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
@ -304,10 +299,7 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
cc.bind(jh.trap_entry);
cc.comment("//Prepare for enter_trap;");
// Make sure cached values are written back
cc.comment("//write back regs to mem");
write_reg_to_mem(jh, jh.pc, traits::PC);
write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
this->write_back(jh);
this->gen_sync(jh, POST_SYNC, -1);
x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);