Commit Graph

265 Commits

Author SHA1 Message Date
d0f3a120fd fix naming in MU wrapper 2021-07-19 16:26:23 +02:00
c592a26346 fix mepc mask 2021-07-09 13:01:22 +02:00
e68918c2e8 fix instruction decode 2021-07-09 07:37:12 +02:00
473f8a5a17 fix privilege behavior 2021-07-07 11:30:00 +02:00
2f4b5bd9b2 fix detailed behavior of TGC_C 2021-07-06 21:19:36 +02:00
23b9741adf refine and fix TGC_C iss to becoem compliant 2021-06-29 11:51:30 +02:00
5d8da08ce5 fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
2021-06-26 14:30:36 +02:00
a249aea703 getting rid of the error: reference to 'wait' is ambiguous 2021-06-25 13:35:42 +02:00
e432dd8208 fix handling of exceptions while accessing address spaces 2021-06-07 22:22:36 +02:00
8c385647dd remove redundant code from checked in generated sources 2021-05-26 23:06:31 +02:00
aaceecd5dc fix mu_p platform features and CSRs 2021-05-17 09:20:09 +02:00
4b3f5a6b0c add missing change 2021-05-16 16:44:30 +02:00
d41e1d816a add factory for ISS and use it in main.cpp 2021-05-16 16:44:14 +02:00
a35974c9f5 make cpu type in core_complex configurable 2021-05-16 15:06:42 +02:00
9c456ba8f2 initial version of MU hart 2021-05-14 13:29:39 +02:00
c57884caee small fix 2021-05-13 16:01:04 +02:00
cf7b62a3f9 update names 2021-05-13 15:54:48 +02:00
f2bf6d682a fix build setup 2021-05-13 14:03:10 +02:00
a1fa8877f7 make core name a cmake option 2021-05-13 09:32:38 +02:00
391f9bb808 remove unneeded constants 2021-05-08 15:14:19 +02:00
ef02dba8c5 add read misa callback 2021-04-09 11:20:51 +02:00
2f4cfb68dc update to latest SCC 2021-04-07 18:56:46 +02:00
7009943106 fix wait for interrupt. Adapt for new SCC structure 2021-04-07 17:42:08 +02:00
0a76ccbdac make RSP register response independend of register definition 2021-03-31 07:48:46 +00:00
32e4aa83b8 use extracted variables 2021-03-27 09:36:52 +00:00
78c7064295 update groovy template to extract used registers 2021-03-26 08:24:45 +00:00
412a4bd9bb update name 2021-03-23 17:13:32 +00:00
ea3ff3c0cd build with SCV lib 2021-03-23 11:57:47 +01:00
b0bcb7febb small fixes for robustness and readability 2021-03-22 22:47:30 +00:00
c941890901 SCC refactoring 2021-03-22 14:50:53 +01:00
51fbc34fb3 change namespace of core complex 2021-03-22 11:57:40 +00:00
4e0f20eba0 rework abort conditions 2021-03-17 19:32:57 +00:00
ff3fa19208 fix RVM description bugs 2021-03-13 10:46:41 +00:00
80057eef32 fix RVC description bugs, remove paged fetch 2021-03-13 10:46:41 +00:00
a5186ff88d optional dependency to TGF_B_src target 2021-03-12 11:16:24 +01:00
f4ec21007b fix signedness issues 2021-03-11 16:12:28 +00:00
ac8eab6e25 update RISC-V desciptions 2021-03-10 17:31:10 +00:00
b7c0fb2b1c fix bitfield structure 2021-03-10 12:40:06 +01:00
768716b064 fix another missing XLEN 2021-03-09 11:07:56 +00:00
bea0dcc387 update missing XLEN 2021-03-09 11:03:37 +00:00
a6691bcd3c update generated code with correct sign extension 2021-03-09 10:21:36 +00:00
40db74ce02 remove tgf_b code generation 2021-03-07 16:26:14 +00:00
c171e3c1ba update CoreDSL descriptions 2021-03-07 10:51:15 +00:00
c251fe15d5 fix desscriptions to conform to ISA spec version 20191213 and TGF-C 2021-03-07 10:51:00 +00:00
dae8acb8a3 checkpoint before refactor 2021-03-06 07:17:42 +00:00
f7cec99fa6 adapt to changes in SCC 2021-03-01 21:08:18 +00:00
be0e7db185 fix templates to comply with CoreDSL2 2021-03-01 21:07:20 +00:00
4aa26b85a0 adapt to change in SCC 2021-03-01 06:36:27 +00:00
9534d58d01 regenerated sources and and add opcode enum to headers
Conflicts:
	gen_input/CoreDSL-Instruction-Set-Description
2021-03-01 06:26:33 +00:00
1668df0531 regenerated sources and and add opcode enum to headers 2021-02-23 08:29:31 +00:00