|
|
c42e336509
|
fix proper debug mode handling (#267 & #268)
|
2021-11-07 17:48:44 +01:00 |
|
|
|
49d09a05d7
|
fix access rights to debug CSR register (#268)
|
2021-11-07 16:45:10 +01:00 |
|
|
|
459794b863
|
add proper handling of store access fault (hart_mu_p)
|
2021-11-06 13:29:11 +01:00 |
|
|
|
039746112b
|
fix exception behavior
|
2021-11-02 15:10:20 +01:00 |
|
|
|
ac6d7ea5d4
|
add debug feature to platform
|
2021-11-02 11:13:29 +01:00 |
|
|
|
1616f0ac90
|
remove deprecated functions
|
2021-10-30 12:57:08 +02:00 |
|
|
|
334d3fb296
|
adapt to SCC changes
|
2021-10-21 22:53:16 +02:00 |
|
|
|
ee6e1d4092
|
Merge remote-tracking branch 'origin/msvc_compat' into develop
Conflicts:
src/sysc/core_complex.cpp
|
2021-10-11 09:42:40 +02:00 |
|
|
|
f0ada1ba8c
|
add MSVC 16 compatibility
|
2021-10-10 19:06:41 +02:00 |
|
|
|
2f15d9676e
|
fix unaligned instr fetch behavior
|
2021-09-30 19:27:46 +02:00 |
|
|
|
d78fcc48e5
|
use marchid in platform
|
2021-09-30 19:27:03 +02:00 |
|
|
|
438e598a4a
|
remove clutter from core descriptions, added instr alignment setting
|
2021-09-29 00:03:11 +02:00 |
|
|
|
174259155d
|
add support for non-compressed ISA
|
2021-09-23 21:09:52 +02:00 |
|
|
|
ba9339a50d
|
fix MPP reset value, PMP inactive in U-mode handling and MRET in U-mode
|
2021-09-21 16:52:40 +02:00 |
|
|
|
65b4db5eca
|
remove mcounteren in M-mode only platform
|
2021-09-18 11:40:00 +02:00 |
|
|
|
09b01af3fa
|
fix find_package use and debug access alignment check
|
2021-08-26 22:10:27 +02:00 |
|
|
|
9c8b72693e
|
correct trap ids of access faults
|
2021-08-20 09:02:56 +02:00 |
|
|
|
2f05083cf0
|
fix elf loader and pmp check for debug accesses
|
2021-08-19 10:50:25 +02:00 |
|
|
|
836ba269e3
|
fix clic reset values
|
2021-08-16 15:05:05 +02:00 |
|
|
|
adeffe47ad
|
fix behavior of riscv_hart_mu_p to match TGC_D
|
2021-08-12 20:34:10 +02:00 |
|
|
|
d95846a849
|
fix trap handling if illegal fetch (PMP) and U-mode CSRs
|
2021-08-01 17:23:22 +02:00 |
|
|
|
af887c286f
|
fix for #2
|
2021-07-28 09:09:08 +02:00 |
|
|
|
d7bddd825c
|
add clic CSRs
|
2021-07-27 10:47:48 +02:00 |
|
|
|
d0f3a120fd
|
fix naming in MU wrapper
|
2021-07-19 16:26:23 +02:00 |
|
|
|
c592a26346
|
fix mepc mask
|
2021-07-09 13:01:22 +02:00 |
|
|
|
e68918c2e8
|
fix instruction decode
|
2021-07-09 07:37:12 +02:00 |
|
|
|
473f8a5a17
|
fix privilege behavior
|
2021-07-07 11:30:00 +02:00 |
|
|
|
2f4b5bd9b2
|
fix detailed behavior of TGC_C
|
2021-07-06 21:19:36 +02:00 |
|
|
|
23b9741adf
|
refine and fix TGC_C iss to becoem compliant
|
2021-06-29 11:51:30 +02:00 |
|
|
|
5d8da08ce5
|
fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
|
2021-06-26 14:30:36 +02:00 |
|
|
|
e432dd8208
|
fix handling of exceptions while accessing address spaces
|
2021-06-07 22:22:36 +02:00 |
|
|
|
aaceecd5dc
|
fix mu_p platform features and CSRs
|
2021-05-17 09:20:09 +02:00 |
|
|
|
d41e1d816a
|
add factory for ISS and use it in main.cpp
|
2021-05-16 16:44:14 +02:00 |
|
|
|
a35974c9f5
|
make cpu type in core_complex configurable
|
2021-05-16 15:06:42 +02:00 |
|
|
|
9c456ba8f2
|
initial version of MU hart
|
2021-05-14 13:29:39 +02:00 |
|
|
|
cf7b62a3f9
|
update names
|
2021-05-13 15:54:48 +02:00 |
|
|
|
391f9bb808
|
remove unneeded constants
|
2021-05-08 15:14:19 +02:00 |
|
|
|
ef02dba8c5
|
add read misa callback
|
2021-04-09 11:20:51 +02:00 |
|
|
|
7009943106
|
fix wait for interrupt. Adapt for new SCC structure
|
2021-04-07 17:42:08 +02:00 |
|
|
|
0a76ccbdac
|
make RSP register response independend of register definition
|
2021-03-31 07:48:46 +00:00 |
|
|
|
f4ec21007b
|
fix signedness issues
|
2021-03-11 16:12:28 +00:00 |
|
|
|
40db74ce02
|
remove tgf_b code generation
|
2021-03-07 16:26:14 +00:00 |
|
|
|
c251fe15d5
|
fix desscriptions to conform to ISA spec version 20191213 and TGF-C
|
2021-03-07 10:51:00 +00:00 |
|
|
|
dae8acb8a3
|
checkpoint before refactor
|
2021-03-06 07:17:42 +00:00 |
|
|
|
be0e7db185
|
fix templates to comply with CoreDSL2
|
2021-03-01 21:07:20 +00:00 |
|
|
|
4aa26b85a0
|
adapt to change in SCC
|
2021-03-01 06:36:27 +00:00 |
|
|
|
9534d58d01
|
regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
|
|
|
1668df0531
|
regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
|
|
|
d07c8679ed
|
update core definition
|
2021-02-15 18:14:52 +00:00 |
|
|
|
72b09472d5
|
update RISC-V descriptions
|
2021-02-15 18:01:33 +00:00 |
|
