 Eyck Jentzsch
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a3084456fd
|
rework core definitions
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2021-09-04 12:47:07 +02:00 |
|
Eyck Jentzsch
|
adeffe47ad
|
fix behavior of riscv_hart_mu_p to match TGC_D
|
2021-08-12 20:34:10 +02:00 |
|
Eyck Jentzsch
|
d95846a849
|
fix trap handling if illegal fetch (PMP) and U-mode CSRs
|
2021-08-01 17:23:22 +02:00 |
|
Eyck Jentzsch
|
e68918c2e8
|
fix instruction decode
|
2021-07-09 07:37:12 +02:00 |
|
Eyck Jentzsch
|
2f4b5bd9b2
|
fix detailed behavior of TGC_C
|
2021-07-06 21:19:36 +02:00 |
|
Eyck Jentzsch
|
23b9741adf
|
refine and fix TGC_C iss to becoem compliant
|
2021-06-29 11:51:30 +02:00 |
|
Eyck Jentzsch
|
e432dd8208
|
fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
|
Eyck Jentzsch
|
aaceecd5dc
|
fix mu_p platform features and CSRs
|
2021-05-17 09:20:09 +02:00 |
|
Eyck Jentzsch
|
cf7b62a3f9
|
update names
|
2021-05-13 15:54:48 +02:00 |
|
Eyck Jentzsch
|
32e4aa83b8
|
use extracted variables
|
2021-03-27 09:36:52 +00:00 |
|
Eyck Jentzsch
|
78c7064295
|
update groovy template to extract used registers
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2021-03-26 08:24:45 +00:00 |
|
Eyck Jentzsch
|
b0bcb7febb
|
small fixes for robustness and readability
|
2021-03-22 22:47:30 +00:00 |
|
Eyck Jentzsch
|
4e0f20eba0
|
rework abort conditions
|
2021-03-17 19:32:57 +00:00 |
|
Eyck Jentzsch
|
ff3fa19208
|
fix RVM description bugs
|
2021-03-13 10:46:41 +00:00 |
|
Eyck Jentzsch
|
80057eef32
|
fix RVC description bugs, remove paged fetch
|
2021-03-13 10:46:41 +00:00 |
|
Eyck Jentzsch
|
f4ec21007b
|
fix signedness issues
|
2021-03-11 16:12:28 +00:00 |
|
Eyck Jentzsch
|
ac8eab6e25
|
update RISC-V desciptions
|
2021-03-10 17:31:10 +00:00 |
|
Eyck Jentzsch
|
bea0dcc387
|
update missing XLEN
|
2021-03-09 11:03:37 +00:00 |
|
Eyck Jentzsch
|
a6691bcd3c
|
update generated code with correct sign extension
|
2021-03-09 10:21:36 +00:00 |
|
Eyck Jentzsch
|
c171e3c1ba
|
update CoreDSL descriptions
|
2021-03-07 10:51:15 +00:00 |
|
Eyck Jentzsch
|
c251fe15d5
|
fix desscriptions to conform to ISA spec version 20191213 and TGF-C
|
2021-03-07 10:51:00 +00:00 |
|
Eyck Jentzsch
|
dae8acb8a3
|
checkpoint before refactor
|
2021-03-06 07:17:42 +00:00 |
|
Eyck Jentzsch
|
be0e7db185
|
fix templates to comply with CoreDSL2
|
2021-03-01 21:07:20 +00:00 |
|
Eyck Jentzsch
|
9534d58d01
|
regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
|
Eyck Jentzsch
|
1668df0531
|
regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
|
Eyck Jentzsch
|
d8e009c72b
|
update CoreDSL decriptions
|
2021-02-15 18:15:13 +00:00 |
|
Eyck Jentzsch
|
72b09472d5
|
update RISC-V descriptions
|
2021-02-15 18:01:33 +00:00 |
|
Eyck Jentzsch
|
3261055871
|
update description to latest CoreDSL2
|
2021-02-15 11:35:56 +00:00 |
|
Eyck Jentzsch
|
34bb8e62ae
|
generate working ISS from CoreDSL 2.0
|
2021-02-06 14:47:06 +00:00 |
|
Eyck Jentzsch
|
da7e29fbb7
|
update definitions of derived constants
|
2021-01-01 09:19:48 +00:00 |
|
Eyck Jentzsch
|
c4da47cedd
|
integrate code generation into build process (first attempt)
|
2020-12-30 07:29:52 +00:00 |
|
Eyck Jentzsch
|
ab554539e3
|
first version of tgf_c based on CoreDSL 2.0
|
2020-12-29 08:48:22 +00:00 |
 Stanislaw Kaushanski
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43488676dd
|
Update TGF naming convention
|
2020-09-11 10:45:44 +02:00 |
|
Stanislaw Kaushanski
|
9754e3953f
|
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
|
2020-08-24 15:01:54 +02:00 |
|
Stanislaw Kaushanski
|
03172e352d
|
move CoreDSL instraction set description files into a dedicated repository CoreDSL-Instruction-Set-Description
|
2020-08-21 15:57:01 +02:00 |
|
Stanislaw Kaushanski
|
8fce0c4759
|
Generate TGF01 and TGF02 cores
|
2020-08-20 17:29:36 +02:00 |
|
Eyck Jentzsch
|
18976e2ce4
|
adapt to newer gdb protocol
|
2020-06-22 08:45:12 +02:00 |
|
Eyck Jentzsch
|
55450f4900
|
[WIP] update dependencies in core desc
|
2020-06-18 06:18:59 +02:00 |
|
Eyck Jentzsch
|
abcfb75011
|
[WIP]
|
2020-05-31 16:41:04 +02:00 |
|
Eyck Jentzsch
|
10797a473d
|
modernize build system and cleanup dependencies
|
2020-05-30 14:16:10 +02:00 |
|
Eyck Jentzsch
|
0ff6ccf9e2
|
get all compile clean
|
2020-05-30 11:27:44 +02:00 |
|
Eyck Jentzsch
|
0698b604fd
|
add TCC backend
|
2020-05-29 08:52:55 +02:00 |
|
Eyck Jentzsch
|
264053a8d6
|
[WIP] add next increment for TCC
|
2020-04-17 19:23:43 +02:00 |
|
Eyck Jentzsch
|
ae1c0b99fe
|
[WIP] basic infrastructure working
|
2020-04-13 17:03:50 +02:00 |
|
Eyck Jentzsch
|
8cdf50d69e
|
[WIP] implement basic infrastructure
|
2020-04-12 12:44:30 +02:00 |
|
Eyck Jentzsch
|
15f4c059e6
|
[WIP] first working version
|
2020-01-12 18:19:48 +01:00 |
|
Eyck Jentzsch
|
e483887c43
|
[WIP] Cleanup of namespaces etc to get compile clean
|
2020-01-10 11:12:20 +01:00 |
|
Eyck Jentzsch
|
fd2e40bfd2
|
Initial setup
|
2020-01-10 07:24:00 +01:00 |
|
Eyck Jentzsch
|
116ed9bb5c
|
[WIP] started to add TinyCC backend
|
2020-01-09 19:43:17 +01:00 |
|
Eyck Jentzsch
|
8b9775e06b
|
Changed namespaces for LLVM related stuff
|
2020-01-07 16:38:31 +01:00 |
|
Eyck Jentzsch
|
1947a2114f
|
Fixed FMT header define
|
2019-07-14 16:51:14 +02:00 |
|
Eyck Jentzsch
|
7f06bba239
|
Fixed time csr handling
|
2019-06-28 20:58:02 +02:00 |
|
Eyck Jentzsch
|
67d9beb7bd
|
reorganized layout to only contain risc-v stuff
|
2019-06-11 16:49:37 +00:00 |