DBT-RISE/DBT-RISE-TGC
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[WIP] update dependencies in core desc

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This commit is contained in:
Eyck Jentzsch
2020-06-18 06:18:59 +02:00
parent c619194465
commit 55450f4900
8 changed files with 3683 additions and 3969 deletions
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10
gen_input/RVC.core_desc
View File

@ -171,7 +171,7 @@ InsructionSet RV32IC extends RISCVBase{
}
}
InsructionSet RV32FC extends RV32IC{
InsructionSet RV32FC extends RISCVBase{
constants {
FLEN
}
@ -218,7 +218,7 @@ InsructionSet RV32FC extends RV32IC{
}
}
InsructionSet RV32DC extends RV32IC{
InsructionSet RV32DC extends RISCVBase{
constants {
FLEN
}
@ -306,6 +306,12 @@ InsructionSet RV64IC extends RV32IC {
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shrl(X[rs1_idx], shamt);
}
C.SRLI64 {//(RV64)
encoding:b1000 | b00 | rs1[2:0] | 00000 | b01;
args_disass: "{name(8+rs1)}, {shamt}";
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shrl(X[rs1_idx], shamt);
}
C.SRAI {//(RV64)
encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01;
args_disass: "{name(8+rs1)}, {shamt}";

5
gen_input/minres_rv.core_desc
View File

@ -6,6 +6,7 @@ import "RVC.core_desc"
import "RVF.core_desc"
import "RVD.core_desc"
/*
Core MNRV32 provides RV32I, RV32IC {
constants {
XLEN:=32;
@ -56,8 +57,8 @@ Core RV64I provides RV64I {
PGMASK := 0xfff; //PGSIZE-1
}
}
Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV64IC, RV32FC, RV32DC {
*/
Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
constants {
XLEN:=64;
FLEN:=64;

4
gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl
View File

@ -184,8 +184,8 @@ private:
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name} */
{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
}};
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>