diff --git a/gen_input/RVC.core_desc b/gen_input/RVC.core_desc index 273618a..b94f829 100644 --- a/gen_input/RVC.core_desc +++ b/gen_input/RVC.core_desc @@ -171,7 +171,7 @@ InsructionSet RV32IC extends RISCVBase{ } } -InsructionSet RV32FC extends RV32IC{ +InsructionSet RV32FC extends RISCVBase{ constants { FLEN } @@ -218,7 +218,7 @@ InsructionSet RV32FC extends RV32IC{ } } -InsructionSet RV32DC extends RV32IC{ +InsructionSet RV32DC extends RISCVBase{ constants { FLEN } @@ -306,6 +306,12 @@ InsructionSet RV64IC extends RV32IC { val rs1_idx[5] <= rs1+8; X[rs1_idx] <= shrl(X[rs1_idx], shamt); } + C.SRLI64 {//(RV64) + encoding:b1000 | b00 | rs1[2:0] | 00000 | b01; + args_disass: "{name(8+rs1)}, {shamt}"; + val rs1_idx[5] <= rs1+8; + X[rs1_idx] <= shrl(X[rs1_idx], shamt); + } C.SRAI {//(RV64) encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01; args_disass: "{name(8+rs1)}, {shamt}"; diff --git a/gen_input/minres_rv.core_desc b/gen_input/minres_rv.core_desc index 29f08a0..5596bd2 100644 --- a/gen_input/minres_rv.core_desc +++ b/gen_input/minres_rv.core_desc @@ -6,6 +6,7 @@ import "RVC.core_desc" import "RVF.core_desc" import "RVD.core_desc" +/* Core MNRV32 provides RV32I, RV32IC { constants { XLEN:=32; @@ -56,8 +57,8 @@ Core RV64I provides RV64I { PGMASK := 0xfff; //PGSIZE-1 } } - -Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV64IC, RV32FC, RV32DC { +*/ +Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC { constants { XLEN:=64; FLEN:=64; diff --git a/gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl b/gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl index 8d93371..d6b5214 100644 --- a/gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl +++ b/gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl @@ -184,8 +184,8 @@ private: const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %> - /* instruction ${instr.instruction.name} */ - {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%> + /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */ + {${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%> }}; /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %> diff --git a/src/vm/tcc/vm_mnrv32.cpp b/src/vm/tcc/vm_mnrv32.cpp index 67bd5ef..42eb30f 100644 --- a/src/vm/tcc/vm_mnrv32.cpp +++ b/src/vm/tcc/vm_mnrv32.cpp @@ -190,8 +190,6 @@ private: {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, /* instruction JAL, encoding '.........................1101111' */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, - /* instruction JALR, encoding '.................000.....1100111' */ - {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, /* instruction BEQ, encoding '.................000.....1100011' */ {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, /* instruction BNE, encoding '.................001.....1100011' */ @@ -288,6 +286,8 @@ private: {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi}, /* instruction CSRRCI, encoding '.................111.....1110011' */ {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, + /* instruction JALR, encoding '.................000.....1100111' */ + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, /* instruction C.ADDI4SPN, encoding '000...........00' */ {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn}, /* instruction C.LW, encoding '010...........00' */ @@ -440,48 +440,10 @@ private: return std::make_tuple(BRANCH); } - /* instruction 3: JALR */ - compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("JALR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 3); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto new_pc_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - if(rd != 0){ - tu.store(tu.add( - cur_pc_val, - tu.constant(4, 32U)), rd + traits::X0); - } - auto PC_val_v = tu.assignment("PC_val", tu.l_and( - new_pc_val, - tu.l_not(tu.constant(0x1, 32U))), 32); - tu.store(PC_val_v, traits::NEXT_PC); - tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 3); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 4: BEQ */ + /* instruction 3: BEQ */ compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BEQ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 4); + vm_base::gen_sync(tu, PRE_SYNC, 3); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -514,15 +476,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 4); + vm_base::gen_sync(tu, POST_SYNC, 3); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 5: BNE */ + /* instruction 4: BNE */ compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BNE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 5); + vm_base::gen_sync(tu, PRE_SYNC, 4); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -555,15 +517,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 5); + vm_base::gen_sync(tu, POST_SYNC, 4); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 6: BLT */ + /* instruction 5: BLT */ compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 6); + vm_base::gen_sync(tu, PRE_SYNC, 5); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -600,15 +562,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 6); + vm_base::gen_sync(tu, POST_SYNC, 5); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 7: BGE */ + /* instruction 6: BGE */ compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BGE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 7); + vm_base::gen_sync(tu, PRE_SYNC, 6); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -645,15 +607,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 7); + vm_base::gen_sync(tu, POST_SYNC, 6); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 8: BLTU */ + /* instruction 7: BLTU */ compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 8); + vm_base::gen_sync(tu, PRE_SYNC, 7); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -686,15 +648,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 8); + vm_base::gen_sync(tu, POST_SYNC, 7); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 9: BGEU */ + /* instruction 8: BGEU */ compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BGEU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 9); + vm_base::gen_sync(tu, PRE_SYNC, 8); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -727,15 +689,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 9); + vm_base::gen_sync(tu, POST_SYNC, 8); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 10: LB */ + /* instruction 9: LB */ compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 10); + vm_base::gen_sync(tu, PRE_SYNC, 9); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -762,15 +724,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 10); + vm_base::gen_sync(tu, POST_SYNC, 9); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 11: LH */ + /* instruction 10: LH */ compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 11); + vm_base::gen_sync(tu, PRE_SYNC, 10); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -797,15 +759,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 11); + vm_base::gen_sync(tu, POST_SYNC, 10); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 12: LW */ + /* instruction 11: LW */ compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 12); + vm_base::gen_sync(tu, PRE_SYNC, 11); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -832,15 +794,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 12); + vm_base::gen_sync(tu, POST_SYNC, 11); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 13: LBU */ + /* instruction 12: LBU */ compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LBU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 13); + vm_base::gen_sync(tu, PRE_SYNC, 12); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -867,15 +829,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 13); + vm_base::gen_sync(tu, POST_SYNC, 12); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 14: LHU */ + /* instruction 13: LHU */ compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 14); + vm_base::gen_sync(tu, PRE_SYNC, 13); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -902,15 +864,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 14); + vm_base::gen_sync(tu, POST_SYNC, 13); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 15: SB */ + /* instruction 14: SB */ compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 15); + vm_base::gen_sync(tu, PRE_SYNC, 14); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -935,15 +897,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 8)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 15); + vm_base::gen_sync(tu, POST_SYNC, 14); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 16: SH */ + /* instruction 15: SH */ compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 16); + vm_base::gen_sync(tu, PRE_SYNC, 15); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -968,15 +930,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 16)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 16); + vm_base::gen_sync(tu, POST_SYNC, 15); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 17: SW */ + /* instruction 16: SW */ compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 17); + vm_base::gen_sync(tu, PRE_SYNC, 16); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1001,15 +963,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 17); + vm_base::gen_sync(tu, POST_SYNC, 16); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 18: ADDI */ + /* instruction 17: ADDI */ compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 18); + vm_base::gen_sync(tu, PRE_SYNC, 17); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1032,15 +994,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 18); + vm_base::gen_sync(tu, POST_SYNC, 17); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 19: SLTI */ + /* instruction 18: SLTI */ compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 19); + vm_base::gen_sync(tu, PRE_SYNC, 18); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1067,15 +1029,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 19); + vm_base::gen_sync(tu, POST_SYNC, 18); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 20: SLTIU */ + /* instruction 19: SLTIU */ compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTIU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 20); + vm_base::gen_sync(tu, PRE_SYNC, 19); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1101,15 +1063,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 20); + vm_base::gen_sync(tu, POST_SYNC, 19); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 21: XORI */ + /* instruction 20: XORI */ compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("XORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 21); + vm_base::gen_sync(tu, PRE_SYNC, 20); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1132,15 +1094,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 21); + vm_base::gen_sync(tu, POST_SYNC, 20); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 22: ORI */ + /* instruction 21: ORI */ compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 22); + vm_base::gen_sync(tu, PRE_SYNC, 21); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1163,15 +1125,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 22); + vm_base::gen_sync(tu, POST_SYNC, 21); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 23: ANDI */ + /* instruction 22: ANDI */ compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ANDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 23); + vm_base::gen_sync(tu, PRE_SYNC, 22); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1194,15 +1156,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 23); + vm_base::gen_sync(tu, POST_SYNC, 22); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 24: SLLI */ + /* instruction 23: SLLI */ compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 24); + vm_base::gen_sync(tu, PRE_SYNC, 23); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -1227,15 +1189,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 24); + vm_base::gen_sync(tu, POST_SYNC, 23); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 25: SRLI */ + /* instruction 24: SRLI */ compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 25); + vm_base::gen_sync(tu, PRE_SYNC, 24); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -1260,15 +1222,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 25); + vm_base::gen_sync(tu, POST_SYNC, 24); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 26: SRAI */ + /* instruction 25: SRAI */ compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 26); + vm_base::gen_sync(tu, PRE_SYNC, 25); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -1293,15 +1255,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 26); + vm_base::gen_sync(tu, POST_SYNC, 25); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 27: ADD */ + /* instruction 26: ADD */ compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 27); + vm_base::gen_sync(tu, PRE_SYNC, 26); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1322,15 +1284,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 27); + vm_base::gen_sync(tu, POST_SYNC, 26); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 28: SUB */ + /* instruction 27: SUB */ compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 28); + vm_base::gen_sync(tu, PRE_SYNC, 27); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1351,15 +1313,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 28); + vm_base::gen_sync(tu, POST_SYNC, 27); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 29: SLL */ + /* instruction 28: SLL */ compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 29); + vm_base::gen_sync(tu, PRE_SYNC, 28); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1384,15 +1346,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 29); + vm_base::gen_sync(tu, POST_SYNC, 28); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 30: SLT */ + /* instruction 29: SLT */ compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 30); + vm_base::gen_sync(tu, PRE_SYNC, 29); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1421,15 +1383,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 30); + vm_base::gen_sync(tu, POST_SYNC, 29); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 31: SLTU */ + /* instruction 30: SLTU */ compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 31); + vm_base::gen_sync(tu, PRE_SYNC, 30); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1460,15 +1422,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 31); + vm_base::gen_sync(tu, POST_SYNC, 30); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 32: XOR */ + /* instruction 31: XOR */ compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 32); + vm_base::gen_sync(tu, PRE_SYNC, 31); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1489,15 +1451,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 32); + vm_base::gen_sync(tu, POST_SYNC, 31); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 33: SRL */ + /* instruction 32: SRL */ compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 33); + vm_base::gen_sync(tu, PRE_SYNC, 32); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1522,15 +1484,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 33); + vm_base::gen_sync(tu, POST_SYNC, 32); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 34: SRA */ + /* instruction 33: SRA */ compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 34); + vm_base::gen_sync(tu, PRE_SYNC, 33); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1555,15 +1517,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 34); + vm_base::gen_sync(tu, POST_SYNC, 33); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 35: OR */ + /* instruction 34: OR */ compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 35); + vm_base::gen_sync(tu, PRE_SYNC, 34); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1584,15 +1546,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 35); + vm_base::gen_sync(tu, POST_SYNC, 34); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 36: AND */ + /* instruction 35: AND */ compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 36); + vm_base::gen_sync(tu, PRE_SYNC, 35); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1613,15 +1575,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 36); + vm_base::gen_sync(tu, POST_SYNC, 35); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 37: FENCE */ + /* instruction 36: FENCE */ compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 37); + vm_base::gen_sync(tu, PRE_SYNC, 36); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t succ = ((bit_sub<20,4>(instr))); @@ -1643,15 +1605,15 @@ private: tu.constant(succ, 32U)), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 37); + vm_base::gen_sync(tu, POST_SYNC, 36); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 38: FENCE_I */ + /* instruction 37: FENCE_I */ compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_I_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 38); + vm_base::gen_sync(tu, PRE_SYNC, 37); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -1669,15 +1631,15 @@ private: tu.close_scope(); tu.store(tu.constant(std::numeric_limits::max(), 32),traits::LAST_BRANCH); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 38); + vm_base::gen_sync(tu, POST_SYNC, 37); gen_trap_check(tu); return std::make_tuple(FLUSH); } - /* instruction 39: ECALL */ + /* instruction 38: ECALL */ compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ECALL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 39); + vm_base::gen_sync(tu, PRE_SYNC, 38); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ecall"); @@ -1687,15 +1649,15 @@ private: tu.open_scope(); this->gen_raise_trap(tu, 0, 11); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 39); + vm_base::gen_sync(tu, POST_SYNC, 38); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 40: EBREAK */ + /* instruction 39: EBREAK */ compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 40); + vm_base::gen_sync(tu, PRE_SYNC, 39); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ebreak"); @@ -1705,15 +1667,15 @@ private: tu.open_scope(); this->gen_raise_trap(tu, 0, 3); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 40); + vm_base::gen_sync(tu, POST_SYNC, 39); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 41: URET */ + /* instruction 40: URET */ compile_ret_t __uret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("URET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 41); + vm_base::gen_sync(tu, PRE_SYNC, 40); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "uret"); @@ -1723,15 +1685,15 @@ private: tu.open_scope(); this->gen_leave_trap(tu, 0); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 41); + vm_base::gen_sync(tu, POST_SYNC, 40); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 42: SRET */ + /* instruction 41: SRET */ compile_ret_t __sret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 42); + vm_base::gen_sync(tu, PRE_SYNC, 41); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "sret"); @@ -1741,15 +1703,15 @@ private: tu.open_scope(); this->gen_leave_trap(tu, 1); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 42); + vm_base::gen_sync(tu, POST_SYNC, 41); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 43: MRET */ + /* instruction 42: MRET */ compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 43); + vm_base::gen_sync(tu, PRE_SYNC, 42); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "mret"); @@ -1759,15 +1721,15 @@ private: tu.open_scope(); this->gen_leave_trap(tu, 3); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 43); + vm_base::gen_sync(tu, POST_SYNC, 42); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 44: WFI */ + /* instruction 43: WFI */ compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("WFI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 44); + vm_base::gen_sync(tu, PRE_SYNC, 43); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "wfi"); @@ -1778,15 +1740,15 @@ private: this->gen_wait(tu, 1); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 44); + vm_base::gen_sync(tu, POST_SYNC, 43); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 45: SFENCE.VMA */ + /* instruction 44: SFENCE.VMA */ compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SFENCE_VMA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 45); + vm_base::gen_sync(tu, PRE_SYNC, 44); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -1806,15 +1768,15 @@ private: tu.trunc(tu.constant(rs2, 32U), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 45); + vm_base::gen_sync(tu, POST_SYNC, 44); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 46: CSRRW */ + /* instruction 45: CSRRW */ compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 46); + vm_base::gen_sync(tu, PRE_SYNC, 45); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1844,15 +1806,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 46); + vm_base::gen_sync(tu, POST_SYNC, 45); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 47: CSRRS */ + /* instruction 46: CSRRS */ compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRS_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 47); + vm_base::gen_sync(tu, PRE_SYNC, 46); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1881,15 +1843,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 47); + vm_base::gen_sync(tu, POST_SYNC, 46); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 48: CSRRC */ + /* instruction 47: CSRRC */ compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRC_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 48); + vm_base::gen_sync(tu, PRE_SYNC, 47); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1918,15 +1880,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 48); + vm_base::gen_sync(tu, POST_SYNC, 47); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 49: CSRRWI */ + /* instruction 48: CSRRWI */ compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRWI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 49); + vm_base::gen_sync(tu, PRE_SYNC, 48); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1952,15 +1914,15 @@ private: true), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 49); + vm_base::gen_sync(tu, POST_SYNC, 48); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 50: CSRRSI */ + /* instruction 49: CSRRSI */ compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRSI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 50); + vm_base::gen_sync(tu, PRE_SYNC, 49); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1991,15 +1953,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 50); + vm_base::gen_sync(tu, POST_SYNC, 49); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 51: CSRRCI */ + /* instruction 50: CSRRCI */ compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRCI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 51); + vm_base::gen_sync(tu, PRE_SYNC, 50); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -2030,11 +1992,49 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 51); + vm_base::gen_sync(tu, POST_SYNC, 50); gen_trap_check(tu); return std::make_tuple(CONT); } + /* instruction 51: JALR */ + compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("JALR_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 51); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto new_pc_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + if(rd != 0){ + tu.store(tu.add( + cur_pc_val, + tu.constant(4, 32U)), rd + traits::X0); + } + auto PC_val_v = tu.assignment("PC_val", tu.l_and( + new_pc_val, + tu.l_not(tu.constant(0x1, 32U))), 32); + tu.store(PC_val_v, traits::NEXT_PC); + tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 51); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + /* instruction 52: C.ADDI4SPN */ compile_ret_t __c_addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_ADDI4SPN_{:#010x}:", pc.val); diff --git a/src/vm/tcc/vm_rv32gc.cpp b/src/vm/tcc/vm_rv32gc.cpp index 7b7a858..35eef1f 100644 --- a/src/vm/tcc/vm_rv32gc.cpp +++ b/src/vm/tcc/vm_rv32gc.cpp @@ -184,14 +184,50 @@ private: const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ + /* instruction MUL, encoding '0000001..........000.....0110011' */ + {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul}, + /* instruction MULH, encoding '0000001..........001.....0110011' */ + {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh}, + /* instruction MULHSU, encoding '0000001..........010.....0110011' */ + {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu}, + /* instruction MULHU, encoding '0000001..........011.....0110011' */ + {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu}, + /* instruction DIV, encoding '0000001..........100.....0110011' */ + {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div}, + /* instruction DIVU, encoding '0000001..........101.....0110011' */ + {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu}, + /* instruction REM, encoding '0000001..........110.....0110011' */ + {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem}, + /* instruction REMU, encoding '0000001..........111.....0110011' */ + {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu}, + /* instruction LR.W, encoding '00010..00000.....010.....0101111' */ + {32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, &this_class::__lr_w}, + /* instruction SC.W, encoding '00011............010.....0101111' */ + {32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__sc_w}, + /* instruction AMOSWAP.W, encoding '00001............010.....0101111' */ + {32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoswap_w}, + /* instruction AMOADD.W, encoding '00000............010.....0101111' */ + {32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoadd_w}, + /* instruction AMOXOR.W, encoding '00100............010.....0101111' */ + {32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoxor_w}, + /* instruction AMOAND.W, encoding '01100............010.....0101111' */ + {32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoand_w}, + /* instruction AMOOR.W, encoding '01000............010.....0101111' */ + {32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoor_w}, + /* instruction AMOMIN.W, encoding '10000............010.....0101111' */ + {32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomin_w}, + /* instruction AMOMAX.W, encoding '10100............010.....0101111' */ + {32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomax_w}, + /* instruction AMOMINU.W, encoding '11000............010.....0101111' */ + {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_w}, + /* instruction AMOMAXU.W, encoding '11100............010.....0101111' */ + {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w}, /* instruction LUI, encoding '.........................0110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, /* instruction AUIPC, encoding '.........................0010111' */ {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, /* instruction JAL, encoding '.........................1101111' */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, - /* instruction JALR, encoding '.................000.....1100111' */ - {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, /* instruction BEQ, encoding '.................000.....1100011' */ {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, /* instruction BNE, encoding '.................001.....1100011' */ @@ -288,44 +324,6 @@ private: {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi}, /* instruction CSRRCI, encoding '.................111.....1110011' */ {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, - /* instruction MUL, encoding '0000001..........000.....0110011' */ - {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul}, - /* instruction MULH, encoding '0000001..........001.....0110011' */ - {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh}, - /* instruction MULHSU, encoding '0000001..........010.....0110011' */ - {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu}, - /* instruction MULHU, encoding '0000001..........011.....0110011' */ - {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu}, - /* instruction DIV, encoding '0000001..........100.....0110011' */ - {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div}, - /* instruction DIVU, encoding '0000001..........101.....0110011' */ - {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu}, - /* instruction REM, encoding '0000001..........110.....0110011' */ - {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem}, - /* instruction REMU, encoding '0000001..........111.....0110011' */ - {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu}, - /* instruction LR.W, encoding '00010..00000.....010.....0101111' */ - {32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, &this_class::__lr_w}, - /* instruction SC.W, encoding '00011............010.....0101111' */ - {32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__sc_w}, - /* instruction AMOSWAP.W, encoding '00001............010.....0101111' */ - {32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoswap_w}, - /* instruction AMOADD.W, encoding '00000............010.....0101111' */ - {32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoadd_w}, - /* instruction AMOXOR.W, encoding '00100............010.....0101111' */ - {32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoxor_w}, - /* instruction AMOAND.W, encoding '01100............010.....0101111' */ - {32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoand_w}, - /* instruction AMOOR.W, encoding '01000............010.....0101111' */ - {32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoor_w}, - /* instruction AMOMIN.W, encoding '10000............010.....0101111' */ - {32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomin_w}, - /* instruction AMOMAX.W, encoding '10100............010.....0101111' */ - {32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomax_w}, - /* instruction AMOMINU.W, encoding '11000............010.....0101111' */ - {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_w}, - /* instruction AMOMAXU.W, encoding '11100............010.....0101111' */ - {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w}, /* instruction FLW, encoding '.................010.....0000111' */ {32, 0b00000000000000000010000000000111, 0b00000000000000000111000001111111, &this_class::__flw}, /* instruction FSW, encoding '.................010.....0100111' */ @@ -430,6 +428,8 @@ private: {32, 0b11010010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_w}, /* instruction FCVT.D.WU, encoding '110100100001.............1010011' */ {32, 0b11010010000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_wu}, + /* instruction JALR, encoding '.................000.....1100111' */ + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, /* instruction C.ADDI4SPN, encoding '000...........00' */ {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn}, /* instruction C.LW, encoding '010...........00' */ @@ -505,1698 +505,10 @@ private: }}; /* instruction definitions */ - /* instruction 0: LUI */ - compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("LUI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 0); - uint8_t rd = ((bit_sub<7,5>(instr))); - int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.constant(imm, 32U), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 0); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 1: AUIPC */ - compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("AUIPC_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 1); - uint8_t rd = ((bit_sub<7,5>(instr))); - int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.add( - tu.ext( - cur_pc_val, - 32, false), - tu.constant(imm, 32U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 1); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 2: JAL */ - compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("JAL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 2); - uint8_t rd = ((bit_sub<7,5>(instr))); - int32_t imm = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.add( - cur_pc_val, - tu.constant(4, 32U)), rd + traits::X0); - } - auto PC_val_v = tu.assignment("PC_val", tu.add( - tu.ext( - cur_pc_val, - 32, false), - tu.constant(imm, 32U)), 32); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 2); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 3: JALR */ - compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("JALR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 3); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto new_pc_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - if(rd != 0){ - tu.store(tu.add( - cur_pc_val, - tu.constant(4, 32U)), rd + traits::X0); - } - auto PC_val_v = tu.assignment("PC_val", tu.l_and( - new_pc_val, - tu.l_not(tu.constant(0x1, 32U))), 32); - tu.store(PC_val_v, traits::NEXT_PC); - tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 3); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 4: BEQ */ - compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("BEQ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 4); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.choose( - tu.icmp( - ICmpInst::ICMP_EQ, - tu.load(rs1 + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), - tu.add( - tu.ext( - cur_pc_val, - 32, false), - tu.constant(imm, 32U)), - tu.add( - cur_pc_val, - tu.constant(4, 32U))), 32); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 4); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 5: BNE */ - compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("BNE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 5); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.choose( - tu.icmp( - ICmpInst::ICMP_NE, - tu.load(rs1 + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), - tu.add( - tu.ext( - cur_pc_val, - 32, false), - tu.constant(imm, 32U)), - tu.add( - cur_pc_val, - tu.constant(4, 32U))), 32); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 5); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 6: BLT */ - compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("BLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 6); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.choose( - tu.icmp( - ICmpInst::ICMP_SLT, - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.ext( - tu.load(rs2 + traits::X0, 0), - 32, false)), - tu.add( - tu.ext( - cur_pc_val, - 32, false), - tu.constant(imm, 32U)), - tu.add( - cur_pc_val, - tu.constant(4, 32U))), 32); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 6); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 7: BGE */ - compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("BGE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 7); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.choose( - tu.icmp( - ICmpInst::ICMP_SGE, - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.ext( - tu.load(rs2 + traits::X0, 0), - 32, false)), - tu.add( - tu.ext( - cur_pc_val, - 32, false), - tu.constant(imm, 32U)), - tu.add( - cur_pc_val, - tu.constant(4, 32U))), 32); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 7); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 8: BLTU */ - compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("BLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 8); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.choose( - tu.icmp( - ICmpInst::ICMP_ULT, - tu.load(rs1 + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), - tu.add( - tu.ext( - cur_pc_val, - 32, false), - tu.constant(imm, 32U)), - tu.add( - cur_pc_val, - tu.constant(4, 32U))), 32); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 8); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 9: BGEU */ - compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("BGEU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 9); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.choose( - tu.icmp( - ICmpInst::ICMP_UGE, - tu.load(rs1 + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), - tu.add( - tu.ext( - cur_pc_val, - 32, false), - tu.constant(imm, 32U)), - tu.add( - cur_pc_val, - tu.constant(4, 32U))), 32); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 9); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 10: LB */ - compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("LB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 10); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - if(rd != 0){ - tu.store(tu.ext( - tu.read_mem(traits::MEM, offs_val, 8), - 32, - false), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 10); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 11: LH */ - compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("LH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 11); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - if(rd != 0){ - tu.store(tu.ext( - tu.read_mem(traits::MEM, offs_val, 16), - 32, - false), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 11); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 12: LW */ - compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("LW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 12); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - if(rd != 0){ - tu.store(tu.ext( - tu.read_mem(traits::MEM, offs_val, 32), - 32, - false), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 12); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 13: LBU */ - compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("LBU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 13); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - if(rd != 0){ - tu.store(tu.ext( - tu.read_mem(traits::MEM, offs_val, 8), - 32, - true), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 13); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 14: LHU */ - compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("LHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 14); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - if(rd != 0){ - tu.store(tu.ext( - tu.read_mem(traits::MEM, offs_val, 16), - 32, - true), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 14); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 15: SB */ - compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 15); - int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - tu.write_mem( - traits::MEM, - offs_val, - tu.trunc(tu.load(rs2 + traits::X0, 0), 8)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 15); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 16: SH */ - compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 16); - int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - tu.write_mem( - traits::MEM, - offs_val, - tu.trunc(tu.load(rs2 + traits::X0, 0), 16)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 16); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 17: SW */ - compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 17); - int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - tu.write_mem( - traits::MEM, - offs_val, - tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 17); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 18: ADDI */ - compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("ADDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 18); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 18); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 19: SLTI */ - compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SLTI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 19); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.choose( - tu.icmp( - ICmpInst::ICMP_SLT, - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), - tu.constant(1, 32U), - tu.constant(0, 32U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 19); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 20: SLTIU */ - compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SLTIU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 20); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - int32_t full_imm_val = imm; - if(rd != 0){ - tu.store(tu.choose( - tu.icmp( - ICmpInst::ICMP_ULT, - tu.load(rs1 + traits::X0, 0), - tu.constant(full_imm_val, 32U)), - tu.constant(1, 32U), - tu.constant(0, 32U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 20); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 21: XORI */ - compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("XORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 21); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.l_xor( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 21); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 22: ORI */ - compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("ORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 22); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.l_or( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 22); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 23: ANDI */ - compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("ANDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 23); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.l_and( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 23); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 24: SLLI */ - compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 24); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(shamt > 31){ - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0){ - tu.store(tu.shl( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 32U)), rd + traits::X0); - } - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 24); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 25: SRLI */ - compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 25); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(shamt > 31){ - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0){ - tu.store(tu.lshr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 32U)), rd + traits::X0); - } - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 25); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 26: SRAI */ - compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 26); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(shamt > 31){ - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0){ - tu.store(tu.ashr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 32U)), rd + traits::X0); - } - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 26); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 27: ADD */ - compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 27); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.add( - tu.load(rs1 + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 27); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 28: SUB */ - compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 28); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.sub( - tu.load(rs1 + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 28); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 29: SLL */ - compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SLL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 29); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.shl( - tu.load(rs1 + traits::X0, 0), - tu.l_and( - tu.load(rs2 + traits::X0, 0), - tu.sub( - tu.constant(32, 32U), - tu.constant(1, 32U)))), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 29); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 30: SLT */ - compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 30); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.choose( - tu.icmp( - ICmpInst::ICMP_SLT, - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.ext( - tu.load(rs2 + traits::X0, 0), - 32, false)), - tu.constant(1, 32U), - tu.constant(0, 32U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 30); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 31: SLTU */ - compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 31); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.choose( - tu.icmp( - ICmpInst::ICMP_ULT, - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, - true), - tu.ext( - tu.load(rs2 + traits::X0, 0), - 32, - true)), - tu.constant(1, 32U), - tu.constant(0, 32U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 31); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 32: XOR */ - compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 32); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.l_xor( - tu.load(rs1 + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 32); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 33: SRL */ - compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SRL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 33); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.lshr( - tu.load(rs1 + traits::X0, 0), - tu.l_and( - tu.load(rs2 + traits::X0, 0), - tu.sub( - tu.constant(32, 32U), - tu.constant(1, 32U)))), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 33); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 34: SRA */ - compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SRA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 34); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.ashr( - tu.load(rs1 + traits::X0, 0), - tu.l_and( - tu.load(rs2 + traits::X0, 0), - tu.sub( - tu.constant(32, 32U), - tu.constant(1, 32U)))), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 34); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 35: OR */ - compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 35); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.l_or( - tu.load(rs1 + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 35); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 36: AND */ - compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 36); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.l_and( - tu.load(rs1 + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 36); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 37: FENCE */ - compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("FENCE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 37); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t succ = ((bit_sub<20,4>(instr))); - uint8_t pred = ((bit_sub<24,4>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "fence"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - tu.write_mem( - traits::FENCE, - tu.constant(0, 64U), - tu.trunc(tu.l_or( - tu.shl( - tu.constant(pred, 32U), - tu.constant(4, 32U)), - tu.constant(succ, 32U)), 32)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 37); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 38: FENCE_I */ - compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("FENCE_I_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 38); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "fence_i"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - tu.write_mem( - traits::FENCE, - tu.constant(1, 64U), - tu.trunc(tu.constant(imm, 32U), 32)); - tu.close_scope(); - tu.store(tu.constant(std::numeric_limits::max(), 32),traits::LAST_BRANCH); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 38); - gen_trap_check(tu); - return std::make_tuple(FLUSH); - } - - /* instruction 39: ECALL */ - compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("ECALL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 39); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ecall"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - this->gen_raise_trap(tu, 0, 11); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 39); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 40: EBREAK */ - compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 40); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ebreak"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - this->gen_raise_trap(tu, 0, 3); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 40); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 41: URET */ - compile_ret_t __uret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("URET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 41); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "uret"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - this->gen_leave_trap(tu, 0); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 41); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 42: SRET */ - compile_ret_t __sret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 42); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "sret"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - this->gen_leave_trap(tu, 1); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 42); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 43: MRET */ - compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("MRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 43); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "mret"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - this->gen_leave_trap(tu, 3); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 43); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 44: WFI */ - compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("WFI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 44); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "wfi"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - this->gen_wait(tu, 1); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 44); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 45: SFENCE.VMA */ - compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SFENCE_VMA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 45); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "sfence.vma"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - tu.write_mem( - traits::FENCE, - tu.constant(2, 64U), - tu.trunc(tu.constant(rs1, 32U), 32)); - tu.write_mem( - traits::FENCE, - tu.constant(3, 64U), - tu.trunc(tu.constant(rs2, 32U), 32)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 45); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 46: CSRRW */ - compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("CSRRW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 46); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto rs_val_val = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - if(rd != 0){ - auto csr_val_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); - tu.write_mem( - traits::CSR, - tu.constant(csr, 16U), - tu.trunc(rs_val_val, 32)); - tu.store(csr_val_val, rd + traits::X0); - } else { - tu.write_mem( - traits::CSR, - tu.constant(csr, 16U), - tu.trunc(rs_val_val, 32)); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 46); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 47: CSRRS */ - compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("CSRRS_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 47); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto xrd_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); - auto xrs1_val = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - if(rd != 0){ - tu.store(xrd_val, rd + traits::X0); - } - if(rs1 != 0){ - tu.write_mem( - traits::CSR, - tu.constant(csr, 16U), - tu.trunc(tu.l_or( - xrd_val, - xrs1_val), 32)); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 47); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 48: CSRRC */ - compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("CSRRC_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 48); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto xrd_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); - auto xrs1_val = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - if(rd != 0){ - tu.store(xrd_val, rd + traits::X0); - } - if(rs1 != 0){ - tu.write_mem( - traits::CSR, - tu.constant(csr, 16U), - tu.trunc(tu.l_and( - xrd_val, - tu.l_not(xrs1_val)), 32)); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 48); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 49: CSRRWI */ - compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("CSRRWI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 49); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t zimm = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), rd + traits::X0); - } - tu.write_mem( - traits::CSR, - tu.constant(csr, 16U), - tu.trunc(tu.ext( - tu.constant(zimm, 32U), - 32, - true), 32)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 49); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 50: CSRRSI */ - compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("CSRRSI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 50); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t zimm = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto res_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); - if(zimm != 0){ - tu.write_mem( - traits::CSR, - tu.constant(csr, 16U), - tu.trunc(tu.l_or( - res_val, - tu.ext( - tu.constant(zimm, 32U), - 32, - true)), 32)); - } - if(rd != 0){ - tu.store(res_val, rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 50); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 51: CSRRCI */ - compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("CSRRCI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 51); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t zimm = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto res_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); - if(rd != 0){ - tu.store(res_val, rd + traits::X0); - } - if(zimm != 0){ - tu.write_mem( - traits::CSR, - tu.constant(csr, 16U), - tu.trunc(tu.l_and( - res_val, - tu.l_not(tu.ext( - tu.constant(zimm, 32U), - 32, - true))), 32)); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 51); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 52: MUL */ + /* instruction 0: MUL */ compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MUL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 52); + vm_base::gen_sync(tu, PRE_SYNC, 0); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2227,15 +539,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 52); + vm_base::gen_sync(tu, POST_SYNC, 0); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 53: MULH */ + /* instruction 1: MULH */ compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 53); + vm_base::gen_sync(tu, PRE_SYNC, 1); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2268,15 +580,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 53); + vm_base::gen_sync(tu, POST_SYNC, 1); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 54: MULHSU */ + /* instruction 2: MULHSU */ compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHSU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 54); + vm_base::gen_sync(tu, PRE_SYNC, 2); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2309,15 +621,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 54); + vm_base::gen_sync(tu, POST_SYNC, 2); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 55: MULHU */ + /* instruction 3: MULHU */ compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 55); + vm_base::gen_sync(tu, PRE_SYNC, 3); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2350,15 +662,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 55); + vm_base::gen_sync(tu, POST_SYNC, 3); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 56: DIV */ + /* instruction 4: DIV */ compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 56); + vm_base::gen_sync(tu, PRE_SYNC, 4); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2406,15 +718,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 56); + vm_base::gen_sync(tu, POST_SYNC, 4); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 57: DIVU */ + /* instruction 5: DIVU */ compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 57); + vm_base::gen_sync(tu, PRE_SYNC, 5); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2442,15 +754,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 57); + vm_base::gen_sync(tu, POST_SYNC, 5); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 58: REM */ + /* instruction 6: REM */ compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REM_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 58); + vm_base::gen_sync(tu, PRE_SYNC, 6); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2498,15 +810,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 58); + vm_base::gen_sync(tu, POST_SYNC, 6); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 59: REMU */ + /* instruction 7: REMU */ compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 59); + vm_base::gen_sync(tu, PRE_SYNC, 7); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2534,15 +846,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 59); + vm_base::gen_sync(tu, POST_SYNC, 7); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 60: LR.W */ + /* instruction 8: LR.W */ compile_ret_t __lr_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 60); + vm_base::gen_sync(tu, PRE_SYNC, 8); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rl = ((bit_sub<25,1>(instr))); @@ -2573,15 +885,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 60); + vm_base::gen_sync(tu, POST_SYNC, 8); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 61: SC.W */ + /* instruction 9: SC.W */ compile_ret_t __sc_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SC_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 61); + vm_base::gen_sync(tu, PRE_SYNC, 9); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2622,15 +934,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 61); + vm_base::gen_sync(tu, POST_SYNC, 9); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 62: AMOSWAP.W */ + /* instruction 10: AMOSWAP.W */ compile_ret_t __amoswap_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOSWAP_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 62); + vm_base::gen_sync(tu, PRE_SYNC, 10); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2659,15 +971,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 62); + vm_base::gen_sync(tu, POST_SYNC, 10); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 63: AMOADD.W */ + /* instruction 11: AMOADD.W */ compile_ret_t __amoadd_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOADD_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 63); + vm_base::gen_sync(tu, PRE_SYNC, 11); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2700,15 +1012,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 63); + vm_base::gen_sync(tu, POST_SYNC, 11); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 64: AMOXOR.W */ + /* instruction 12: AMOXOR.W */ compile_ret_t __amoxor_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOXOR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 64); + vm_base::gen_sync(tu, PRE_SYNC, 12); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2741,15 +1053,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 64); + vm_base::gen_sync(tu, POST_SYNC, 12); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 65: AMOAND.W */ + /* instruction 13: AMOAND.W */ compile_ret_t __amoand_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOAND_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 65); + vm_base::gen_sync(tu, PRE_SYNC, 13); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2782,15 +1094,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 65); + vm_base::gen_sync(tu, POST_SYNC, 13); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 66: AMOOR.W */ + /* instruction 14: AMOOR.W */ compile_ret_t __amoor_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOOR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 66); + vm_base::gen_sync(tu, PRE_SYNC, 14); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2823,15 +1135,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 66); + vm_base::gen_sync(tu, POST_SYNC, 14); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 67: AMOMIN.W */ + /* instruction 15: AMOMIN.W */ compile_ret_t __amomin_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMIN_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 67); + vm_base::gen_sync(tu, PRE_SYNC, 15); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2872,15 +1184,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 67); + vm_base::gen_sync(tu, POST_SYNC, 15); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 68: AMOMAX.W */ + /* instruction 16: AMOMAX.W */ compile_ret_t __amomax_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAX_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 68); + vm_base::gen_sync(tu, PRE_SYNC, 16); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2921,15 +1233,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 68); + vm_base::gen_sync(tu, POST_SYNC, 16); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 69: AMOMINU.W */ + /* instruction 17: AMOMINU.W */ compile_ret_t __amominu_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMINU_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 69); + vm_base::gen_sync(tu, PRE_SYNC, 17); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2966,15 +1278,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 69); + vm_base::gen_sync(tu, POST_SYNC, 17); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 70: AMOMAXU.W */ + /* instruction 18: AMOMAXU.W */ compile_ret_t __amomaxu_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAXU_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 70); + vm_base::gen_sync(tu, PRE_SYNC, 18); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3011,15 +1323,1665 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 70); + vm_base::gen_sync(tu, POST_SYNC, 18); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 71: FLW */ + /* instruction 19: LUI */ + compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("LUI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 19); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.constant(imm, 32U), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 19); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 20: AUIPC */ + compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("AUIPC_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 20); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.add( + tu.ext( + cur_pc_val, + 32, false), + tu.constant(imm, 32U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 20); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 21: JAL */ + compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("JAL_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 21); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.add( + cur_pc_val, + tu.constant(4, 32U)), rd + traits::X0); + } + auto PC_val_v = tu.assignment("PC_val", tu.add( + tu.ext( + cur_pc_val, + 32, false), + tu.constant(imm, 32U)), 32); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 21); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 22: BEQ */ + compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("BEQ_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 22); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.choose( + tu.icmp( + ICmpInst::ICMP_EQ, + tu.load(rs1 + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), + tu.add( + tu.ext( + cur_pc_val, + 32, false), + tu.constant(imm, 32U)), + tu.add( + cur_pc_val, + tu.constant(4, 32U))), 32); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 22); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 23: BNE */ + compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("BNE_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 23); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.choose( + tu.icmp( + ICmpInst::ICMP_NE, + tu.load(rs1 + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), + tu.add( + tu.ext( + cur_pc_val, + 32, false), + tu.constant(imm, 32U)), + tu.add( + cur_pc_val, + tu.constant(4, 32U))), 32); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 23); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 24: BLT */ + compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("BLT_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 24); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.choose( + tu.icmp( + ICmpInst::ICMP_SLT, + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.ext( + tu.load(rs2 + traits::X0, 0), + 32, false)), + tu.add( + tu.ext( + cur_pc_val, + 32, false), + tu.constant(imm, 32U)), + tu.add( + cur_pc_val, + tu.constant(4, 32U))), 32); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 24); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 25: BGE */ + compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("BGE_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 25); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.choose( + tu.icmp( + ICmpInst::ICMP_SGE, + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.ext( + tu.load(rs2 + traits::X0, 0), + 32, false)), + tu.add( + tu.ext( + cur_pc_val, + 32, false), + tu.constant(imm, 32U)), + tu.add( + cur_pc_val, + tu.constant(4, 32U))), 32); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 25); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 26: BLTU */ + compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("BLTU_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 26); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.choose( + tu.icmp( + ICmpInst::ICMP_ULT, + tu.load(rs1 + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), + tu.add( + tu.ext( + cur_pc_val, + 32, false), + tu.constant(imm, 32U)), + tu.add( + cur_pc_val, + tu.constant(4, 32U))), 32); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 26); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 27: BGEU */ + compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("BGEU_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 27); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.choose( + tu.icmp( + ICmpInst::ICMP_UGE, + tu.load(rs1 + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), + tu.add( + tu.ext( + cur_pc_val, + 32, false), + tu.constant(imm, 32U)), + tu.add( + cur_pc_val, + tu.constant(4, 32U))), 32); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 32U, true), tu.constant(pc.val, 32U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 27); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 28: LB */ + compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("LB_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 28); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + if(rd != 0){ + tu.store(tu.ext( + tu.read_mem(traits::MEM, offs_val, 8), + 32, + false), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 28); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 29: LH */ + compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("LH_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 29); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + if(rd != 0){ + tu.store(tu.ext( + tu.read_mem(traits::MEM, offs_val, 16), + 32, + false), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 29); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 30: LW */ + compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("LW_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 30); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + if(rd != 0){ + tu.store(tu.ext( + tu.read_mem(traits::MEM, offs_val, 32), + 32, + false), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 30); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 31: LBU */ + compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("LBU_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 31); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + if(rd != 0){ + tu.store(tu.ext( + tu.read_mem(traits::MEM, offs_val, 8), + 32, + true), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 31); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 32: LHU */ + compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("LHU_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 32); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + if(rd != 0){ + tu.store(tu.ext( + tu.read_mem(traits::MEM, offs_val, 16), + 32, + true), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 32); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 33: SB */ + compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SB_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 33); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + tu.write_mem( + traits::MEM, + offs_val, + tu.trunc(tu.load(rs2 + traits::X0, 0), 8)); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 33); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 34: SH */ + compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SH_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 34); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + tu.write_mem( + traits::MEM, + offs_val, + tu.trunc(tu.load(rs2 + traits::X0, 0), 16)); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 34); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 35: SW */ + compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SW_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 35); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + tu.write_mem( + traits::MEM, + offs_val, + tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 35); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 36: ADDI */ + compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("ADDI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 36); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 36); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 37: SLTI */ + compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SLTI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 37); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.choose( + tu.icmp( + ICmpInst::ICMP_SLT, + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), + tu.constant(1, 32U), + tu.constant(0, 32U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 37); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 38: SLTIU */ + compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SLTIU_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 38); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + int32_t full_imm_val = imm; + if(rd != 0){ + tu.store(tu.choose( + tu.icmp( + ICmpInst::ICMP_ULT, + tu.load(rs1 + traits::X0, 0), + tu.constant(full_imm_val, 32U)), + tu.constant(1, 32U), + tu.constant(0, 32U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 38); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 39: XORI */ + compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("XORI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 39); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.l_xor( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 39); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 40: ORI */ + compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("ORI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 40); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.l_or( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 40); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 41: ANDI */ + compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("ANDI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 41); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.l_and( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 41); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 42: SLLI */ + compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SLLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 42); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(shamt > 31){ + this->gen_raise_trap(tu, 0, 0); + } else { + if(rd != 0){ + tu.store(tu.shl( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 32U)), rd + traits::X0); + } + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 42); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 43: SRLI */ + compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SRLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 43); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(shamt > 31){ + this->gen_raise_trap(tu, 0, 0); + } else { + if(rd != 0){ + tu.store(tu.lshr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 32U)), rd + traits::X0); + } + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 43); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 44: SRAI */ + compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SRAI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 44); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(shamt > 31){ + this->gen_raise_trap(tu, 0, 0); + } else { + if(rd != 0){ + tu.store(tu.ashr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 32U)), rd + traits::X0); + } + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 44); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 45: ADD */ + compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("ADD_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 45); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.add( + tu.load(rs1 + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 45); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 46: SUB */ + compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SUB_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 46); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.sub( + tu.load(rs1 + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 46); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 47: SLL */ + compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SLL_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 47); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.shl( + tu.load(rs1 + traits::X0, 0), + tu.l_and( + tu.load(rs2 + traits::X0, 0), + tu.sub( + tu.constant(32, 32U), + tu.constant(1, 32U)))), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 47); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 48: SLT */ + compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SLT_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 48); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.choose( + tu.icmp( + ICmpInst::ICMP_SLT, + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.ext( + tu.load(rs2 + traits::X0, 0), + 32, false)), + tu.constant(1, 32U), + tu.constant(0, 32U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 48); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 49: SLTU */ + compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SLTU_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 49); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.choose( + tu.icmp( + ICmpInst::ICMP_ULT, + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, + true), + tu.ext( + tu.load(rs2 + traits::X0, 0), + 32, + true)), + tu.constant(1, 32U), + tu.constant(0, 32U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 49); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 50: XOR */ + compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("XOR_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 50); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.l_xor( + tu.load(rs1 + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 50); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 51: SRL */ + compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SRL_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 51); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.lshr( + tu.load(rs1 + traits::X0, 0), + tu.l_and( + tu.load(rs2 + traits::X0, 0), + tu.sub( + tu.constant(32, 32U), + tu.constant(1, 32U)))), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 51); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 52: SRA */ + compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SRA_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 52); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.ashr( + tu.load(rs1 + traits::X0, 0), + tu.l_and( + tu.load(rs2 + traits::X0, 0), + tu.sub( + tu.constant(32, 32U), + tu.constant(1, 32U)))), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 52); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 53: OR */ + compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("OR_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 53); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.l_or( + tu.load(rs1 + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 53); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 54: AND */ + compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("AND_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 54); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.l_and( + tu.load(rs1 + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 54); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 55: FENCE */ + compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("FENCE_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 55); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "fence"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + tu.write_mem( + traits::FENCE, + tu.constant(0, 64U), + tu.trunc(tu.l_or( + tu.shl( + tu.constant(pred, 32U), + tu.constant(4, 32U)), + tu.constant(succ, 32U)), 32)); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 55); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 56: FENCE_I */ + compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("FENCE_I_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 56); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "fence_i"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + tu.write_mem( + traits::FENCE, + tu.constant(1, 64U), + tu.trunc(tu.constant(imm, 32U), 32)); + tu.close_scope(); + tu.store(tu.constant(std::numeric_limits::max(), 32),traits::LAST_BRANCH); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 56); + gen_trap_check(tu); + return std::make_tuple(FLUSH); + } + + /* instruction 57: ECALL */ + compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("ECALL_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 57); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ecall"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + this->gen_raise_trap(tu, 0, 11); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 57); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 58: EBREAK */ + compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("EBREAK_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 58); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ebreak"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + this->gen_raise_trap(tu, 0, 3); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 58); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 59: URET */ + compile_ret_t __uret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("URET_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 59); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "uret"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + this->gen_leave_trap(tu, 0); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 59); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 60: SRET */ + compile_ret_t __sret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SRET_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 60); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "sret"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + this->gen_leave_trap(tu, 1); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 60); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 61: MRET */ + compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("MRET_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 61); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "mret"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + this->gen_leave_trap(tu, 3); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 61); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 62: WFI */ + compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("WFI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 62); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "wfi"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + this->gen_wait(tu, 1); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 62); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 63: SFENCE.VMA */ + compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SFENCE_VMA_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 63); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "sfence.vma"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + tu.write_mem( + traits::FENCE, + tu.constant(2, 64U), + tu.trunc(tu.constant(rs1, 32U), 32)); + tu.write_mem( + traits::FENCE, + tu.constant(3, 64U), + tu.trunc(tu.constant(rs2, 32U), 32)); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 63); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 64: CSRRW */ + compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("CSRRW_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 64); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto rs_val_val = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); + if(rd != 0){ + auto csr_val_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); + tu.write_mem( + traits::CSR, + tu.constant(csr, 16U), + tu.trunc(rs_val_val, 32)); + tu.store(csr_val_val, rd + traits::X0); + } else { + tu.write_mem( + traits::CSR, + tu.constant(csr, 16U), + tu.trunc(rs_val_val, 32)); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 64); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 65: CSRRS */ + compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("CSRRS_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 65); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto xrd_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); + auto xrs1_val = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); + if(rd != 0){ + tu.store(xrd_val, rd + traits::X0); + } + if(rs1 != 0){ + tu.write_mem( + traits::CSR, + tu.constant(csr, 16U), + tu.trunc(tu.l_or( + xrd_val, + xrs1_val), 32)); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 65); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 66: CSRRC */ + compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("CSRRC_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 66); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto xrd_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); + auto xrs1_val = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); + if(rd != 0){ + tu.store(xrd_val, rd + traits::X0); + } + if(rs1 != 0){ + tu.write_mem( + traits::CSR, + tu.constant(csr, 16U), + tu.trunc(tu.l_and( + xrd_val, + tu.l_not(xrs1_val)), 32)); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 66); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 67: CSRRWI */ + compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("CSRRWI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 67); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), rd + traits::X0); + } + tu.write_mem( + traits::CSR, + tu.constant(csr, 16U), + tu.trunc(tu.ext( + tu.constant(zimm, 32U), + 32, + true), 32)); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 67); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 68: CSRRSI */ + compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("CSRRSI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 68); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto res_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); + if(zimm != 0){ + tu.write_mem( + traits::CSR, + tu.constant(csr, 16U), + tu.trunc(tu.l_or( + res_val, + tu.ext( + tu.constant(zimm, 32U), + 32, + true)), 32)); + } + if(rd != 0){ + tu.store(res_val, rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 68); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 69: CSRRCI */ + compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("CSRRCI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 69); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto res_val = tu.assignment(tu.read_mem(traits::CSR, tu.constant(csr, 16U), 32), 32); + if(rd != 0){ + tu.store(res_val, rd + traits::X0); + } + if(zimm != 0){ + tu.write_mem( + traits::CSR, + tu.constant(csr, 16U), + tu.trunc(tu.l_and( + res_val, + tu.l_not(tu.ext( + tu.constant(zimm, 32U), + 32, + true))), 32)); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 69); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 70: FLW */ compile_ret_t __flw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 71); + vm_base::gen_sync(tu, PRE_SYNC, 70); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -3054,15 +3016,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 71); + vm_base::gen_sync(tu, POST_SYNC, 70); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 72: FSW */ + /* instruction 71: FSW */ compile_ret_t __fsw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 72); + vm_base::gen_sync(tu, PRE_SYNC, 71); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3090,15 +3052,15 @@ private: ), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 72); + vm_base::gen_sync(tu, POST_SYNC, 71); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 73: FMADD.S */ + /* instruction 72: FMADD.S */ compile_ret_t __fmadd_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMADD_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 73); + vm_base::gen_sync(tu, PRE_SYNC, 72); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3183,15 +3145,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 73); + vm_base::gen_sync(tu, POST_SYNC, 72); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 74: FMSUB.S */ + /* instruction 73: FMSUB.S */ compile_ret_t __fmsub_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMSUB_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 74); + vm_base::gen_sync(tu, PRE_SYNC, 73); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3276,15 +3238,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 74); + vm_base::gen_sync(tu, POST_SYNC, 73); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 75: FNMADD.S */ + /* instruction 74: FNMADD.S */ compile_ret_t __fnmadd_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMADD_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 75); + vm_base::gen_sync(tu, PRE_SYNC, 74); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3369,15 +3331,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 75); + vm_base::gen_sync(tu, POST_SYNC, 74); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 76: FNMSUB.S */ + /* instruction 75: FNMSUB.S */ compile_ret_t __fnmsub_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMSUB_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 76); + vm_base::gen_sync(tu, PRE_SYNC, 75); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3462,15 +3424,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 76); + vm_base::gen_sync(tu, POST_SYNC, 75); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 77: FADD.S */ + /* instruction 76: FADD.S */ compile_ret_t __fadd_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FADD_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 77); + vm_base::gen_sync(tu, PRE_SYNC, 76); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3541,15 +3503,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 77); + vm_base::gen_sync(tu, POST_SYNC, 76); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 78: FSUB.S */ + /* instruction 77: FSUB.S */ compile_ret_t __fsub_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSUB_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 78); + vm_base::gen_sync(tu, PRE_SYNC, 77); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3620,15 +3582,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 78); + vm_base::gen_sync(tu, POST_SYNC, 77); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 79: FMUL.S */ + /* instruction 78: FMUL.S */ compile_ret_t __fmul_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMUL_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 79); + vm_base::gen_sync(tu, PRE_SYNC, 78); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3699,15 +3661,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 79); + vm_base::gen_sync(tu, POST_SYNC, 78); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 80: FDIV.S */ + /* instruction 79: FDIV.S */ compile_ret_t __fdiv_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FDIV_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 80); + vm_base::gen_sync(tu, PRE_SYNC, 79); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3778,15 +3740,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 80); + vm_base::gen_sync(tu, POST_SYNC, 79); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 81: FSQRT.S */ + /* instruction 80: FSQRT.S */ compile_ret_t __fsqrt_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSQRT_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 81); + vm_base::gen_sync(tu, PRE_SYNC, 80); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3851,15 +3813,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 81); + vm_base::gen_sync(tu, POST_SYNC, 80); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 82: FSGNJ.S */ + /* instruction 81: FSGNJ.S */ compile_ret_t __fsgnj_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJ_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 82); + vm_base::gen_sync(tu, PRE_SYNC, 81); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3907,15 +3869,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 82); + vm_base::gen_sync(tu, POST_SYNC, 81); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 83: FSGNJN.S */ + /* instruction 82: FSGNJN.S */ compile_ret_t __fsgnjn_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJN_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 83); + vm_base::gen_sync(tu, PRE_SYNC, 82); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3963,15 +3925,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 83); + vm_base::gen_sync(tu, POST_SYNC, 82); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 84: FSGNJX.S */ + /* instruction 83: FSGNJX.S */ compile_ret_t __fsgnjx_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJX_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 84); + vm_base::gen_sync(tu, PRE_SYNC, 83); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4015,15 +3977,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 84); + vm_base::gen_sync(tu, POST_SYNC, 83); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 85: FMIN.S */ + /* instruction 84: FMIN.S */ compile_ret_t __fmin_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMIN_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 85); + vm_base::gen_sync(tu, PRE_SYNC, 84); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4081,15 +4043,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 85); + vm_base::gen_sync(tu, POST_SYNC, 84); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 86: FMAX.S */ + /* instruction 85: FMAX.S */ compile_ret_t __fmax_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMAX_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 86); + vm_base::gen_sync(tu, PRE_SYNC, 85); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4147,15 +4109,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 86); + vm_base::gen_sync(tu, POST_SYNC, 85); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 87: FCVT.W.S */ + /* instruction 86: FCVT.W.S */ compile_ret_t __fcvt_w_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_W_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 87); + vm_base::gen_sync(tu, PRE_SYNC, 86); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4207,15 +4169,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 87); + vm_base::gen_sync(tu, POST_SYNC, 86); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 88: FCVT.WU.S */ + /* instruction 87: FCVT.WU.S */ compile_ret_t __fcvt_wu_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_WU_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 88); + vm_base::gen_sync(tu, PRE_SYNC, 87); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4267,15 +4229,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 88); + vm_base::gen_sync(tu, POST_SYNC, 87); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 89: FEQ.S */ + /* instruction 88: FEQ.S */ compile_ret_t __feq_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FEQ_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 89); + vm_base::gen_sync(tu, PRE_SYNC, 88); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4330,15 +4292,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 89); + vm_base::gen_sync(tu, POST_SYNC, 88); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 90: FLT.S */ + /* instruction 89: FLT.S */ compile_ret_t __flt_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLT_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 90); + vm_base::gen_sync(tu, PRE_SYNC, 89); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4407,15 +4369,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 90); + vm_base::gen_sync(tu, POST_SYNC, 89); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 91: FLE.S */ + /* instruction 90: FLE.S */ compile_ret_t __fle_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLE_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 91); + vm_base::gen_sync(tu, PRE_SYNC, 90); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4470,15 +4432,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 91); + vm_base::gen_sync(tu, POST_SYNC, 90); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 92: FCLASS.S */ + /* instruction 91: FCLASS.S */ compile_ret_t __fclass_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCLASS_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 92); + vm_base::gen_sync(tu, PRE_SYNC, 91); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -4498,15 +4460,15 @@ private: ), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 92); + vm_base::gen_sync(tu, POST_SYNC, 91); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 93: FCVT.S.W */ + /* instruction 92: FCVT.S.W */ compile_ret_t __fcvt_s_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 93); + vm_base::gen_sync(tu, PRE_SYNC, 92); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4556,15 +4518,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 93); + vm_base::gen_sync(tu, POST_SYNC, 92); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 94: FCVT.S.WU */ + /* instruction 93: FCVT.S.WU */ compile_ret_t __fcvt_s_wu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_WU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 94); + vm_base::gen_sync(tu, PRE_SYNC, 93); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4614,15 +4576,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 94); + vm_base::gen_sync(tu, POST_SYNC, 93); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 95: FMV.X.W */ + /* instruction 94: FMV.X.W */ compile_ret_t __fmv_x_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_X_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 95); + vm_base::gen_sync(tu, PRE_SYNC, 94); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -4644,15 +4606,15 @@ private: false), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 95); + vm_base::gen_sync(tu, POST_SYNC, 94); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 96: FMV.W.X */ + /* instruction 95: FMV.W.X */ compile_ret_t __fmv_w_x(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_W_X_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 96); + vm_base::gen_sync(tu, PRE_SYNC, 95); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -4686,15 +4648,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 96); + vm_base::gen_sync(tu, POST_SYNC, 95); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 97: FLD */ + /* instruction 96: FLD */ compile_ret_t __fld(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 97); + vm_base::gen_sync(tu, PRE_SYNC, 96); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -4726,15 +4688,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 97); + vm_base::gen_sync(tu, POST_SYNC, 96); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 98: FSD */ + /* instruction 97: FSD */ compile_ret_t __fsd(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 98); + vm_base::gen_sync(tu, PRE_SYNC, 97); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4762,15 +4724,15 @@ private: ), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 98); + vm_base::gen_sync(tu, POST_SYNC, 97); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 99: FMADD.D */ + /* instruction 98: FMADD.D */ compile_ret_t __fmadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 99); + vm_base::gen_sync(tu, PRE_SYNC, 98); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4834,15 +4796,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 99); + vm_base::gen_sync(tu, POST_SYNC, 98); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 100: FMSUB.D */ + /* instruction 99: FMSUB.D */ compile_ret_t __fmsub_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMSUB_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 100); + vm_base::gen_sync(tu, PRE_SYNC, 99); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4906,15 +4868,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 100); + vm_base::gen_sync(tu, POST_SYNC, 99); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 101: FNMADD.D */ + /* instruction 100: FNMADD.D */ compile_ret_t __fnmadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 101); + vm_base::gen_sync(tu, PRE_SYNC, 100); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4978,15 +4940,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 101); + vm_base::gen_sync(tu, POST_SYNC, 100); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 102: FNMSUB.D */ + /* instruction 101: FNMSUB.D */ compile_ret_t __fnmsub_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMSUB_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 102); + vm_base::gen_sync(tu, PRE_SYNC, 101); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5050,15 +5012,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 102); + vm_base::gen_sync(tu, POST_SYNC, 101); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 103: FADD.D */ + /* instruction 102: FADD.D */ compile_ret_t __fadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 103); + vm_base::gen_sync(tu, PRE_SYNC, 102); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5113,15 +5075,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 103); + vm_base::gen_sync(tu, POST_SYNC, 102); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 104: FSUB.D */ + /* instruction 103: FSUB.D */ compile_ret_t __fsub_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSUB_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 104); + vm_base::gen_sync(tu, PRE_SYNC, 103); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5176,15 +5138,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 104); + vm_base::gen_sync(tu, POST_SYNC, 103); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 105: FMUL.D */ + /* instruction 104: FMUL.D */ compile_ret_t __fmul_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMUL_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 105); + vm_base::gen_sync(tu, PRE_SYNC, 104); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5239,15 +5201,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 105); + vm_base::gen_sync(tu, POST_SYNC, 104); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 106: FDIV.D */ + /* instruction 105: FDIV.D */ compile_ret_t __fdiv_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FDIV_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 106); + vm_base::gen_sync(tu, PRE_SYNC, 105); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5302,15 +5264,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 106); + vm_base::gen_sync(tu, POST_SYNC, 105); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 107: FSQRT.D */ + /* instruction 106: FSQRT.D */ compile_ret_t __fsqrt_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSQRT_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 107); + vm_base::gen_sync(tu, PRE_SYNC, 106); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5360,15 +5322,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 107); + vm_base::gen_sync(tu, POST_SYNC, 106); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 108: FSGNJ.D */ + /* instruction 107: FSGNJ.D */ compile_ret_t __fsgnj_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJ_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 108); + vm_base::gen_sync(tu, PRE_SYNC, 107); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5410,15 +5372,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 108); + vm_base::gen_sync(tu, POST_SYNC, 107); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 109: FSGNJN.D */ + /* instruction 108: FSGNJN.D */ compile_ret_t __fsgnjn_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJN_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 109); + vm_base::gen_sync(tu, PRE_SYNC, 108); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5460,15 +5422,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 109); + vm_base::gen_sync(tu, POST_SYNC, 108); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 110: FSGNJX.D */ + /* instruction 109: FSGNJX.D */ compile_ret_t __fsgnjx_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJX_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 110); + vm_base::gen_sync(tu, PRE_SYNC, 109); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5507,15 +5469,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 110); + vm_base::gen_sync(tu, POST_SYNC, 109); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 111: FMIN.D */ + /* instruction 110: FMIN.D */ compile_ret_t __fmin_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMIN_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 111); + vm_base::gen_sync(tu, PRE_SYNC, 110); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5563,15 +5525,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 111); + vm_base::gen_sync(tu, POST_SYNC, 110); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 112: FMAX.D */ + /* instruction 111: FMAX.D */ compile_ret_t __fmax_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMAX_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 112); + vm_base::gen_sync(tu, PRE_SYNC, 111); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5619,15 +5581,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 112); + vm_base::gen_sync(tu, POST_SYNC, 111); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 113: FCVT.S.D */ + /* instruction 112: FCVT.S.D */ compile_ret_t __fcvt_s_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 113); + vm_base::gen_sync(tu, PRE_SYNC, 112); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5656,15 +5618,15 @@ private: true)), rd + traits::F0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 113); + vm_base::gen_sync(tu, POST_SYNC, 112); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 114: FCVT.D.S */ + /* instruction 113: FCVT.D.S */ compile_ret_t __fcvt_d_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 114); + vm_base::gen_sync(tu, PRE_SYNC, 113); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5697,15 +5659,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 114); + vm_base::gen_sync(tu, POST_SYNC, 113); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 115: FEQ.D */ + /* instruction 114: FEQ.D */ compile_ret_t __feq_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FEQ_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 115); + vm_base::gen_sync(tu, PRE_SYNC, 114); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5746,15 +5708,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 115); + vm_base::gen_sync(tu, POST_SYNC, 114); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 116: FLT.D */ + /* instruction 115: FLT.D */ compile_ret_t __flt_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLT_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 116); + vm_base::gen_sync(tu, PRE_SYNC, 115); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5795,15 +5757,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 116); + vm_base::gen_sync(tu, POST_SYNC, 115); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 117: FLE.D */ + /* instruction 116: FLE.D */ compile_ret_t __fle_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLE_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 117); + vm_base::gen_sync(tu, PRE_SYNC, 116); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5844,15 +5806,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 117); + vm_base::gen_sync(tu, POST_SYNC, 116); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 118: FCLASS.D */ + /* instruction 117: FCLASS.D */ compile_ret_t __fclass_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCLASS_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 118); + vm_base::gen_sync(tu, PRE_SYNC, 117); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -5873,15 +5835,15 @@ private: ), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 118); + vm_base::gen_sync(tu, POST_SYNC, 117); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 119: FCVT.W.D */ + /* instruction 118: FCVT.W.D */ compile_ret_t __fcvt_w_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_W_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 119); + vm_base::gen_sync(tu, PRE_SYNC, 118); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5919,15 +5881,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 119); + vm_base::gen_sync(tu, POST_SYNC, 118); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 120: FCVT.WU.D */ + /* instruction 119: FCVT.WU.D */ compile_ret_t __fcvt_wu_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_WU_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 120); + vm_base::gen_sync(tu, PRE_SYNC, 119); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5965,15 +5927,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 120); + vm_base::gen_sync(tu, POST_SYNC, 119); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 121: FCVT.D.W */ + /* instruction 120: FCVT.D.W */ compile_ret_t __fcvt_d_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 121); + vm_base::gen_sync(tu, PRE_SYNC, 120); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6013,15 +5975,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 121); + vm_base::gen_sync(tu, POST_SYNC, 120); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 122: FCVT.D.WU */ + /* instruction 121: FCVT.D.WU */ compile_ret_t __fcvt_d_wu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_WU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 122); + vm_base::gen_sync(tu, PRE_SYNC, 121); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6061,11 +6023,49 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 122); + vm_base::gen_sync(tu, POST_SYNC, 121); gen_trap_check(tu); return std::make_tuple(CONT); } + /* instruction 122: JALR */ + compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("JALR_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 122); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto new_pc_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + if(rd != 0){ + tu.store(tu.add( + cur_pc_val, + tu.constant(4, 32U)), rd + traits::X0); + } + auto PC_val_v = tu.assignment("PC_val", tu.l_and( + new_pc_val, + tu.l_not(tu.constant(0x1, 32U))), 32); + tu.store(PC_val_v, traits::NEXT_PC); + tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 122); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + /* instruction 123: C.ADDI4SPN */ compile_ret_t __c_addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_ADDI4SPN_{:#010x}:", pc.val); diff --git a/src/vm/tcc/vm_rv32imac.cpp b/src/vm/tcc/vm_rv32imac.cpp index 60f2494..9398720 100644 --- a/src/vm/tcc/vm_rv32imac.cpp +++ b/src/vm/tcc/vm_rv32imac.cpp @@ -190,8 +190,6 @@ private: {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, /* instruction JAL, encoding '.........................1101111' */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, - /* instruction JALR, encoding '.................000.....1100111' */ - {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, /* instruction BEQ, encoding '.................000.....1100011' */ {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, /* instruction BNE, encoding '.................001.....1100011' */ @@ -326,6 +324,8 @@ private: {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_w}, /* instruction AMOMAXU.W, encoding '11100............010.....0101111' */ {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w}, + /* instruction JALR, encoding '.................000.....1100111' */ + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, /* instruction C.ADDI4SPN, encoding '000...........00' */ {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn}, /* instruction C.LW, encoding '010...........00' */ @@ -478,48 +478,10 @@ private: return std::make_tuple(BRANCH); } - /* instruction 3: JALR */ - compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("JALR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 3); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - auto new_pc_val = tu.assignment(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 32, false), - tu.constant(imm, 32U)), 32); - if(rd != 0){ - tu.store(tu.add( - cur_pc_val, - tu.constant(4, 32U)), rd + traits::X0); - } - auto PC_val_v = tu.assignment("PC_val", tu.l_and( - new_pc_val, - tu.l_not(tu.constant(0x1, 32U))), 32); - tu.store(PC_val_v, traits::NEXT_PC); - tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 3); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 4: BEQ */ + /* instruction 3: BEQ */ compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BEQ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 4); + vm_base::gen_sync(tu, PRE_SYNC, 3); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -552,15 +514,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 4); + vm_base::gen_sync(tu, POST_SYNC, 3); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 5: BNE */ + /* instruction 4: BNE */ compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BNE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 5); + vm_base::gen_sync(tu, PRE_SYNC, 4); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -593,15 +555,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 5); + vm_base::gen_sync(tu, POST_SYNC, 4); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 6: BLT */ + /* instruction 5: BLT */ compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 6); + vm_base::gen_sync(tu, PRE_SYNC, 5); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -638,15 +600,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 6); + vm_base::gen_sync(tu, POST_SYNC, 5); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 7: BGE */ + /* instruction 6: BGE */ compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BGE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 7); + vm_base::gen_sync(tu, PRE_SYNC, 6); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -683,15 +645,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 7); + vm_base::gen_sync(tu, POST_SYNC, 6); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 8: BLTU */ + /* instruction 7: BLTU */ compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 8); + vm_base::gen_sync(tu, PRE_SYNC, 7); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -724,15 +686,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 8); + vm_base::gen_sync(tu, POST_SYNC, 7); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 9: BGEU */ + /* instruction 8: BGEU */ compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BGEU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 9); + vm_base::gen_sync(tu, PRE_SYNC, 8); int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -765,15 +727,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 9); + vm_base::gen_sync(tu, POST_SYNC, 8); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 10: LB */ + /* instruction 9: LB */ compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 10); + vm_base::gen_sync(tu, PRE_SYNC, 9); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -800,15 +762,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 10); + vm_base::gen_sync(tu, POST_SYNC, 9); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 11: LH */ + /* instruction 10: LH */ compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 11); + vm_base::gen_sync(tu, PRE_SYNC, 10); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -835,15 +797,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 11); + vm_base::gen_sync(tu, POST_SYNC, 10); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 12: LW */ + /* instruction 11: LW */ compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 12); + vm_base::gen_sync(tu, PRE_SYNC, 11); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -870,15 +832,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 12); + vm_base::gen_sync(tu, POST_SYNC, 11); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 13: LBU */ + /* instruction 12: LBU */ compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LBU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 13); + vm_base::gen_sync(tu, PRE_SYNC, 12); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -905,15 +867,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 13); + vm_base::gen_sync(tu, POST_SYNC, 12); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 14: LHU */ + /* instruction 13: LHU */ compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 14); + vm_base::gen_sync(tu, PRE_SYNC, 13); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -940,15 +902,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 14); + vm_base::gen_sync(tu, POST_SYNC, 13); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 15: SB */ + /* instruction 14: SB */ compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 15); + vm_base::gen_sync(tu, PRE_SYNC, 14); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -973,15 +935,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 8)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 15); + vm_base::gen_sync(tu, POST_SYNC, 14); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 16: SH */ + /* instruction 15: SH */ compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 16); + vm_base::gen_sync(tu, PRE_SYNC, 15); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1006,15 +968,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 16)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 16); + vm_base::gen_sync(tu, POST_SYNC, 15); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 17: SW */ + /* instruction 16: SW */ compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 17); + vm_base::gen_sync(tu, PRE_SYNC, 16); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1039,15 +1001,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 17); + vm_base::gen_sync(tu, POST_SYNC, 16); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 18: ADDI */ + /* instruction 17: ADDI */ compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 18); + vm_base::gen_sync(tu, PRE_SYNC, 17); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1070,15 +1032,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 18); + vm_base::gen_sync(tu, POST_SYNC, 17); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 19: SLTI */ + /* instruction 18: SLTI */ compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 19); + vm_base::gen_sync(tu, PRE_SYNC, 18); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1105,15 +1067,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 19); + vm_base::gen_sync(tu, POST_SYNC, 18); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 20: SLTIU */ + /* instruction 19: SLTIU */ compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTIU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 20); + vm_base::gen_sync(tu, PRE_SYNC, 19); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1139,15 +1101,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 20); + vm_base::gen_sync(tu, POST_SYNC, 19); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 21: XORI */ + /* instruction 20: XORI */ compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("XORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 21); + vm_base::gen_sync(tu, PRE_SYNC, 20); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1170,15 +1132,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 21); + vm_base::gen_sync(tu, POST_SYNC, 20); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 22: ORI */ + /* instruction 21: ORI */ compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 22); + vm_base::gen_sync(tu, PRE_SYNC, 21); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1201,15 +1163,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 22); + vm_base::gen_sync(tu, POST_SYNC, 21); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 23: ANDI */ + /* instruction 22: ANDI */ compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ANDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 23); + vm_base::gen_sync(tu, PRE_SYNC, 22); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -1232,15 +1194,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 23); + vm_base::gen_sync(tu, POST_SYNC, 22); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 24: SLLI */ + /* instruction 23: SLLI */ compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 24); + vm_base::gen_sync(tu, PRE_SYNC, 23); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -1265,15 +1227,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 24); + vm_base::gen_sync(tu, POST_SYNC, 23); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 25: SRLI */ + /* instruction 24: SRLI */ compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 25); + vm_base::gen_sync(tu, PRE_SYNC, 24); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -1298,15 +1260,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 25); + vm_base::gen_sync(tu, POST_SYNC, 24); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 26: SRAI */ + /* instruction 25: SRAI */ compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 26); + vm_base::gen_sync(tu, PRE_SYNC, 25); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -1331,15 +1293,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 26); + vm_base::gen_sync(tu, POST_SYNC, 25); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 27: ADD */ + /* instruction 26: ADD */ compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 27); + vm_base::gen_sync(tu, PRE_SYNC, 26); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1360,15 +1322,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 27); + vm_base::gen_sync(tu, POST_SYNC, 26); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 28: SUB */ + /* instruction 27: SUB */ compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 28); + vm_base::gen_sync(tu, PRE_SYNC, 27); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1389,15 +1351,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 28); + vm_base::gen_sync(tu, POST_SYNC, 27); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 29: SLL */ + /* instruction 28: SLL */ compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 29); + vm_base::gen_sync(tu, PRE_SYNC, 28); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1422,15 +1384,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 29); + vm_base::gen_sync(tu, POST_SYNC, 28); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 30: SLT */ + /* instruction 29: SLT */ compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 30); + vm_base::gen_sync(tu, PRE_SYNC, 29); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1459,15 +1421,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 30); + vm_base::gen_sync(tu, POST_SYNC, 29); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 31: SLTU */ + /* instruction 30: SLTU */ compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 31); + vm_base::gen_sync(tu, PRE_SYNC, 30); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1498,15 +1460,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 31); + vm_base::gen_sync(tu, POST_SYNC, 30); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 32: XOR */ + /* instruction 31: XOR */ compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 32); + vm_base::gen_sync(tu, PRE_SYNC, 31); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1527,15 +1489,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 32); + vm_base::gen_sync(tu, POST_SYNC, 31); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 33: SRL */ + /* instruction 32: SRL */ compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 33); + vm_base::gen_sync(tu, PRE_SYNC, 32); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1560,15 +1522,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 33); + vm_base::gen_sync(tu, POST_SYNC, 32); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 34: SRA */ + /* instruction 33: SRA */ compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 34); + vm_base::gen_sync(tu, PRE_SYNC, 33); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1593,15 +1555,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 34); + vm_base::gen_sync(tu, POST_SYNC, 33); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 35: OR */ + /* instruction 34: OR */ compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 35); + vm_base::gen_sync(tu, PRE_SYNC, 34); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1622,15 +1584,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 35); + vm_base::gen_sync(tu, POST_SYNC, 34); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 36: AND */ + /* instruction 35: AND */ compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 36); + vm_base::gen_sync(tu, PRE_SYNC, 35); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1651,15 +1613,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 36); + vm_base::gen_sync(tu, POST_SYNC, 35); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 37: FENCE */ + /* instruction 36: FENCE */ compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 37); + vm_base::gen_sync(tu, PRE_SYNC, 36); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t succ = ((bit_sub<20,4>(instr))); @@ -1681,15 +1643,15 @@ private: tu.constant(succ, 32U)), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 37); + vm_base::gen_sync(tu, POST_SYNC, 36); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 38: FENCE_I */ + /* instruction 37: FENCE_I */ compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_I_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 38); + vm_base::gen_sync(tu, PRE_SYNC, 37); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -1707,15 +1669,15 @@ private: tu.close_scope(); tu.store(tu.constant(std::numeric_limits::max(), 32),traits::LAST_BRANCH); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 38); + vm_base::gen_sync(tu, POST_SYNC, 37); gen_trap_check(tu); return std::make_tuple(FLUSH); } - /* instruction 39: ECALL */ + /* instruction 38: ECALL */ compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ECALL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 39); + vm_base::gen_sync(tu, PRE_SYNC, 38); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ecall"); @@ -1725,15 +1687,15 @@ private: tu.open_scope(); this->gen_raise_trap(tu, 0, 11); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 39); + vm_base::gen_sync(tu, POST_SYNC, 38); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 40: EBREAK */ + /* instruction 39: EBREAK */ compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 40); + vm_base::gen_sync(tu, PRE_SYNC, 39); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ebreak"); @@ -1743,15 +1705,15 @@ private: tu.open_scope(); this->gen_raise_trap(tu, 0, 3); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 40); + vm_base::gen_sync(tu, POST_SYNC, 39); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 41: URET */ + /* instruction 40: URET */ compile_ret_t __uret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("URET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 41); + vm_base::gen_sync(tu, PRE_SYNC, 40); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "uret"); @@ -1761,15 +1723,15 @@ private: tu.open_scope(); this->gen_leave_trap(tu, 0); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 41); + vm_base::gen_sync(tu, POST_SYNC, 40); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 42: SRET */ + /* instruction 41: SRET */ compile_ret_t __sret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 42); + vm_base::gen_sync(tu, PRE_SYNC, 41); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "sret"); @@ -1779,15 +1741,15 @@ private: tu.open_scope(); this->gen_leave_trap(tu, 1); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 42); + vm_base::gen_sync(tu, POST_SYNC, 41); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 43: MRET */ + /* instruction 42: MRET */ compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 43); + vm_base::gen_sync(tu, PRE_SYNC, 42); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "mret"); @@ -1797,15 +1759,15 @@ private: tu.open_scope(); this->gen_leave_trap(tu, 3); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 43); + vm_base::gen_sync(tu, POST_SYNC, 42); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 44: WFI */ + /* instruction 43: WFI */ compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("WFI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 44); + vm_base::gen_sync(tu, PRE_SYNC, 43); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "wfi"); @@ -1816,15 +1778,15 @@ private: this->gen_wait(tu, 1); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 44); + vm_base::gen_sync(tu, POST_SYNC, 43); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 45: SFENCE.VMA */ + /* instruction 44: SFENCE.VMA */ compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SFENCE_VMA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 45); + vm_base::gen_sync(tu, PRE_SYNC, 44); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -1844,15 +1806,15 @@ private: tu.trunc(tu.constant(rs2, 32U), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 45); + vm_base::gen_sync(tu, POST_SYNC, 44); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 46: CSRRW */ + /* instruction 45: CSRRW */ compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 46); + vm_base::gen_sync(tu, PRE_SYNC, 45); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1882,15 +1844,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 46); + vm_base::gen_sync(tu, POST_SYNC, 45); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 47: CSRRS */ + /* instruction 46: CSRRS */ compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRS_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 47); + vm_base::gen_sync(tu, PRE_SYNC, 46); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1919,15 +1881,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 47); + vm_base::gen_sync(tu, POST_SYNC, 46); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 48: CSRRC */ + /* instruction 47: CSRRC */ compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRC_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 48); + vm_base::gen_sync(tu, PRE_SYNC, 47); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1956,15 +1918,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 48); + vm_base::gen_sync(tu, POST_SYNC, 47); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 49: CSRRWI */ + /* instruction 48: CSRRWI */ compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRWI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 49); + vm_base::gen_sync(tu, PRE_SYNC, 48); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1990,15 +1952,15 @@ private: true), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 49); + vm_base::gen_sync(tu, POST_SYNC, 48); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 50: CSRRSI */ + /* instruction 49: CSRRSI */ compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRSI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 50); + vm_base::gen_sync(tu, PRE_SYNC, 49); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -2029,15 +1991,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 50); + vm_base::gen_sync(tu, POST_SYNC, 49); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 51: CSRRCI */ + /* instruction 50: CSRRCI */ compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRCI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 51); + vm_base::gen_sync(tu, PRE_SYNC, 50); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -2068,15 +2030,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 51); + vm_base::gen_sync(tu, POST_SYNC, 50); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 52: MUL */ + /* instruction 51: MUL */ compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MUL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 52); + vm_base::gen_sync(tu, PRE_SYNC, 51); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2107,15 +2069,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 52); + vm_base::gen_sync(tu, POST_SYNC, 51); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 53: MULH */ + /* instruction 52: MULH */ compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 53); + vm_base::gen_sync(tu, PRE_SYNC, 52); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2148,15 +2110,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 53); + vm_base::gen_sync(tu, POST_SYNC, 52); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 54: MULHSU */ + /* instruction 53: MULHSU */ compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHSU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 54); + vm_base::gen_sync(tu, PRE_SYNC, 53); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2189,15 +2151,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 54); + vm_base::gen_sync(tu, POST_SYNC, 53); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 55: MULHU */ + /* instruction 54: MULHU */ compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 55); + vm_base::gen_sync(tu, PRE_SYNC, 54); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2230,15 +2192,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 55); + vm_base::gen_sync(tu, POST_SYNC, 54); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 56: DIV */ + /* instruction 55: DIV */ compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 56); + vm_base::gen_sync(tu, PRE_SYNC, 55); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2286,15 +2248,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 56); + vm_base::gen_sync(tu, POST_SYNC, 55); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 57: DIVU */ + /* instruction 56: DIVU */ compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 57); + vm_base::gen_sync(tu, PRE_SYNC, 56); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2322,15 +2284,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 57); + vm_base::gen_sync(tu, POST_SYNC, 56); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 58: REM */ + /* instruction 57: REM */ compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REM_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 58); + vm_base::gen_sync(tu, PRE_SYNC, 57); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2378,15 +2340,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 58); + vm_base::gen_sync(tu, POST_SYNC, 57); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 59: REMU */ + /* instruction 58: REMU */ compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 59); + vm_base::gen_sync(tu, PRE_SYNC, 58); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2414,15 +2376,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 59); + vm_base::gen_sync(tu, POST_SYNC, 58); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 60: LR.W */ + /* instruction 59: LR.W */ compile_ret_t __lr_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 60); + vm_base::gen_sync(tu, PRE_SYNC, 59); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rl = ((bit_sub<25,1>(instr))); @@ -2453,15 +2415,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 60); + vm_base::gen_sync(tu, POST_SYNC, 59); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 61: SC.W */ + /* instruction 60: SC.W */ compile_ret_t __sc_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SC_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 61); + vm_base::gen_sync(tu, PRE_SYNC, 60); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2502,15 +2464,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 61); + vm_base::gen_sync(tu, POST_SYNC, 60); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 62: AMOSWAP.W */ + /* instruction 61: AMOSWAP.W */ compile_ret_t __amoswap_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOSWAP_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 62); + vm_base::gen_sync(tu, PRE_SYNC, 61); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2539,15 +2501,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 62); + vm_base::gen_sync(tu, POST_SYNC, 61); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 63: AMOADD.W */ + /* instruction 62: AMOADD.W */ compile_ret_t __amoadd_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOADD_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 63); + vm_base::gen_sync(tu, PRE_SYNC, 62); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2580,15 +2542,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 63); + vm_base::gen_sync(tu, POST_SYNC, 62); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 64: AMOXOR.W */ + /* instruction 63: AMOXOR.W */ compile_ret_t __amoxor_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOXOR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 64); + vm_base::gen_sync(tu, PRE_SYNC, 63); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2621,15 +2583,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 64); + vm_base::gen_sync(tu, POST_SYNC, 63); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 65: AMOAND.W */ + /* instruction 64: AMOAND.W */ compile_ret_t __amoand_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOAND_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 65); + vm_base::gen_sync(tu, PRE_SYNC, 64); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2662,15 +2624,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 65); + vm_base::gen_sync(tu, POST_SYNC, 64); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 66: AMOOR.W */ + /* instruction 65: AMOOR.W */ compile_ret_t __amoor_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOOR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 66); + vm_base::gen_sync(tu, PRE_SYNC, 65); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2703,15 +2665,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 66); + vm_base::gen_sync(tu, POST_SYNC, 65); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 67: AMOMIN.W */ + /* instruction 66: AMOMIN.W */ compile_ret_t __amomin_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMIN_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 67); + vm_base::gen_sync(tu, PRE_SYNC, 66); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2752,15 +2714,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 67); + vm_base::gen_sync(tu, POST_SYNC, 66); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 68: AMOMAX.W */ + /* instruction 67: AMOMAX.W */ compile_ret_t __amomax_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAX_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 68); + vm_base::gen_sync(tu, PRE_SYNC, 67); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2801,15 +2763,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 68); + vm_base::gen_sync(tu, POST_SYNC, 67); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 69: AMOMINU.W */ + /* instruction 68: AMOMINU.W */ compile_ret_t __amominu_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMINU_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 69); + vm_base::gen_sync(tu, PRE_SYNC, 68); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2846,15 +2808,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 69); + vm_base::gen_sync(tu, POST_SYNC, 68); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 70: AMOMAXU.W */ + /* instruction 69: AMOMAXU.W */ compile_ret_t __amomaxu_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAXU_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 70); + vm_base::gen_sync(tu, PRE_SYNC, 69); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2891,11 +2853,49 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 70); + vm_base::gen_sync(tu, POST_SYNC, 69); gen_trap_check(tu); return std::make_tuple(CONT); } + /* instruction 70: JALR */ + compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("JALR_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 70); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + auto new_pc_val = tu.assignment(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 32, false), + tu.constant(imm, 32U)), 32); + if(rd != 0){ + tu.store(tu.add( + cur_pc_val, + tu.constant(4, 32U)), rd + traits::X0); + } + auto PC_val_v = tu.assignment("PC_val", tu.l_and( + new_pc_val, + tu.l_not(tu.constant(0x1, 32U))), 32); + tu.store(PC_val_v, traits::NEXT_PC); + tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 70); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + /* instruction 71: C.ADDI4SPN */ compile_ret_t __c_addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_ADDI4SPN_{:#010x}:", pc.val); diff --git a/src/vm/tcc/vm_rv64gc.cpp b/src/vm/tcc/vm_rv64gc.cpp index df3e057..11ff9d1 100644 --- a/src/vm/tcc/vm_rv64gc.cpp +++ b/src/vm/tcc/vm_rv64gc.cpp @@ -182,7 +182,7 @@ private: compile_func op; }; - const std::array instr_descr = {{ + const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI, encoding '.........................0110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, @@ -232,12 +232,12 @@ private: {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, /* instruction ANDI, encoding '.................111.....0010011' */ {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, - /* instruction SLLI, encoding '0000000..........001.....0010011' */ - {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, - /* instruction SRLI, encoding '0000000..........101.....0010011' */ - {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, - /* instruction SRAI, encoding '0100000..........101.....0010011' */ - {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, + /* instruction SLLI, encoding '000000...........001.....0010011' */ + {32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, &this_class::__slli}, + /* instruction SRLI, encoding '000000...........101.....0010011' */ + {32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srli}, + /* instruction SRAI, encoding '010000...........101.....0010011' */ + {32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srai}, /* instruction ADD, encoding '0000000..........000.....0110011' */ {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, /* instruction SUB, encoding '0100000..........000.....0110011' */ @@ -294,12 +294,6 @@ private: {32, 0b00000000000000000011000000000011, 0b00000000000000000111000001111111, &this_class::__ld}, /* instruction SD, encoding '.................011.....0100011' */ {32, 0b00000000000000000011000000100011, 0b00000000000000000111000001111111, &this_class::__sd}, - /* instruction SLLI, encoding '000000...........001.....0010011' */ - {32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, &this_class::__slli}, - /* instruction SRLI, encoding '000000...........101.....0010011' */ - {32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srli}, - /* instruction SRAI, encoding '010000...........101.....0010011' */ - {32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srai}, /* instruction ADDIW, encoding '.................000.....0011011' */ {32, 0b00000000000000000000000000011011, 0b00000000000000000111000001111111, &this_class::__addiw}, /* instruction SLLIW, encoding '0000000..........001.....0011011' */ @@ -512,6 +506,22 @@ private: {32, 0b11100010000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv_x_d}, /* instruction FMV.D.X, encoding '111100100000.....000.....1010011' */ {32, 0b11110010000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv_d_x}, + /* instruction C.LD, encoding '011...........00' */ + {16, 0b0110000000000000, 0b1110000000000011, &this_class::__c_ld}, + /* instruction C.SD, encoding '111...........00' */ + {16, 0b1110000000000000, 0b1110000000000011, &this_class::__c_sd}, + /* instruction C.LDSP, encoding '011...........10' */ + {16, 0b0110000000000010, 0b1110000000000011, &this_class::__c_ldsp}, + /* instruction C.SDSP, encoding '111...........10' */ + {16, 0b1110000000000010, 0b1110000000000011, &this_class::__c_sdsp}, + /* instruction C.FLD, encoding '001...........00' */ + {16, 0b0010000000000000, 0b1110000000000011, &this_class::__c_fld}, + /* instruction C.FSD, encoding '101...........00' */ + {16, 0b1010000000000000, 0b1110000000000011, &this_class::__c_fsd}, + /* instruction C.FLDSP, encoding '001...........10' */ + {16, 0b0010000000000010, 0b1110000000000011, &this_class::__c_fldsp}, + /* instruction C.FSDSP, encoding '101...........10' */ + {16, 0b1010000000000010, 0b1110000000000011, &this_class::__c_fsdsp}, /* instruction C.ADDI4SPN, encoding '000...........00' */ {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn}, /* instruction C.LW, encoding '010...........00' */ @@ -530,10 +540,10 @@ private: {16, 0b0110000000000001, 0b1110000000000011, &this_class::__c_lui}, /* instruction C.ADDI16SP, encoding '011.00010.....01' */ {16, 0b0110000100000001, 0b1110111110000011, &this_class::__c_addi16sp}, - /* instruction C.SRLI, encoding '100000........01' */ - {16, 0b1000000000000001, 0b1111110000000011, &this_class::__c_srli}, - /* instruction C.SRAI, encoding '100001........01' */ - {16, 0b1000010000000001, 0b1111110000000011, &this_class::__c_srai}, + /* instruction C.SRLI, encoding '100.00........01' */ + {16, 0b1000000000000001, 0b1110110000000011, &this_class::__c_srli}, + /* instruction C.SRAI, encoding '100.01........01' */ + {16, 0b1000010000000001, 0b1110110000000011, &this_class::__c_srai}, /* instruction C.ANDI, encoding '100.10........01' */ {16, 0b1000100000000001, 0b1110110000000011, &this_class::__c_andi}, /* instruction C.SUB, encoding '100011...00...01' */ @@ -550,8 +560,8 @@ private: {16, 0b1100000000000001, 0b1110000000000011, &this_class::__c_beqz}, /* instruction C.BNEZ, encoding '111...........01' */ {16, 0b1110000000000001, 0b1110000000000011, &this_class::__c_bnez}, - /* instruction C.SLLI, encoding '0000..........10' */ - {16, 0b0000000000000010, 0b1111000000000011, &this_class::__c_slli}, + /* instruction C.SLLI, encoding '000...........10' */ + {16, 0b0000000000000010, 0b1110000000000011, &this_class::__c_slli}, /* instruction C.LWSP, encoding '010...........10' */ {16, 0b0100000000000010, 0b1110000000000011, &this_class::__c_lwsp}, /* instruction C.MV, encoding '1000..........10' */ @@ -568,32 +578,12 @@ private: {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c_swsp}, /* instruction DII, encoding '0000000000000000' */ {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, - /* instruction C.LD, encoding '011...........00' */ - {16, 0b0110000000000000, 0b1110000000000011, &this_class::__c_ld}, - /* instruction C.SD, encoding '111...........00' */ - {16, 0b1110000000000000, 0b1110000000000011, &this_class::__c_sd}, - /* instruction C.LDSP, encoding '011...........10' */ - {16, 0b0110000000000010, 0b1110000000000011, &this_class::__c_ldsp}, - /* instruction C.SDSP, encoding '111...........10' */ - {16, 0b1110000000000010, 0b1110000000000011, &this_class::__c_sdsp}, - /* instruction C.FLD, encoding '001...........00' */ - {16, 0b0010000000000000, 0b1110000000000011, &this_class::__c_fld}, - /* instruction C.FSD, encoding '101...........00' */ - {16, 0b1010000000000000, 0b1110000000000011, &this_class::__c_fsd}, - /* instruction C.FLDSP, encoding '001...........10' */ - {16, 0b0010000000000010, 0b1110000000000011, &this_class::__c_fldsp}, - /* instruction C.FSDSP, encoding '101...........10' */ - {16, 0b1010000000000010, 0b1110000000000011, &this_class::__c_fsdsp}, /* instruction C.SUBW, encoding '100111...00...01' */ {16, 0b1001110000000001, 0b1111110001100011, &this_class::__c_subw}, /* instruction C.ADDW, encoding '100111...01...01' */ {16, 0b1001110000100001, 0b1111110001100011, &this_class::__c_addw}, - /* instruction C.SRLI, encoding '100.00........01' */ - {16, 0b1000000000000001, 0b1110110000000011, &this_class::__c_srli}, - /* instruction C.SRAI, encoding '100.01........01' */ - {16, 0b1000010000000001, 0b1110110000000011, &this_class::__c_srai}, - /* instruction C.SLLI, encoding '000...........10' */ - {16, 0b0000000000000010, 0b1110000000000011, &this_class::__c_slli}, + /* instruction C.SRLI64, encoding '100000...01' */ + {11, 0b10000000001, 0b11111100011, &this_class::__c_srli64}, }}; /* instruction definitions */ @@ -1455,7 +1445,7 @@ private: vm_base::gen_sync(tu, PRE_SYNC, 24); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1466,14 +1456,10 @@ private: auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); pc=pc+4; tu.open_scope(); - if(shamt > 31){ - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0){ - tu.store(tu.shl( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); - } + if(rd != 0){ + tu.store(tu.shl( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); @@ -1488,7 +1474,7 @@ private: vm_base::gen_sync(tu, PRE_SYNC, 25); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1499,14 +1485,10 @@ private: auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); pc=pc+4; tu.open_scope(); - if(shamt > 31){ - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0){ - tu.store(tu.lshr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); - } + if(rd != 0){ + tu.store(tu.lshr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); @@ -1521,7 +1503,7 @@ private: vm_base::gen_sync(tu, PRE_SYNC, 26); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1532,14 +1514,10 @@ private: auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); pc=pc+4; tu.open_scope(); - if(shamt > 31){ - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0){ - tu.store(tu.ashr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); - } + if(rd != 0){ + tu.store(tu.ashr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); @@ -2388,97 +2366,10 @@ private: return std::make_tuple(CONT); } - /* instruction 55: SLLI */ - compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 55); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,6>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.shl( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 55); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 56: SRLI */ - compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 56); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,6>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.lshr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 56); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 57: SRAI */ - compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 57); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,6>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(rd != 0){ - tu.store(tu.ashr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 57); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 58: ADDIW */ + /* instruction 55: ADDIW */ compile_ret_t __addiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 58); + vm_base::gen_sync(tu, PRE_SYNC, 55); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -2508,15 +2399,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 58); + vm_base::gen_sync(tu, POST_SYNC, 55); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 59: SLLIW */ + /* instruction 56: SLLIW */ compile_ret_t __slliw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 59); + vm_base::gen_sync(tu, PRE_SYNC, 56); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2544,15 +2435,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 59); + vm_base::gen_sync(tu, POST_SYNC, 56); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 60: SRLIW */ + /* instruction 57: SRLIW */ compile_ret_t __srliw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 60); + vm_base::gen_sync(tu, PRE_SYNC, 57); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2580,15 +2471,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 60); + vm_base::gen_sync(tu, POST_SYNC, 57); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 61: SRAIW */ + /* instruction 58: SRAIW */ compile_ret_t __sraiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 61); + vm_base::gen_sync(tu, PRE_SYNC, 58); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2616,15 +2507,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 61); + vm_base::gen_sync(tu, POST_SYNC, 58); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 62: ADDW */ + /* instruction 59: ADDW */ compile_ret_t __addw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 62); + vm_base::gen_sync(tu, PRE_SYNC, 59); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2652,15 +2543,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 62); + vm_base::gen_sync(tu, POST_SYNC, 59); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 63: SUBW */ + /* instruction 60: SUBW */ compile_ret_t __subw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SUBW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 63); + vm_base::gen_sync(tu, PRE_SYNC, 60); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2688,15 +2579,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 63); + vm_base::gen_sync(tu, POST_SYNC, 60); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 64: SLLW */ + /* instruction 61: SLLW */ compile_ret_t __sllw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 64); + vm_base::gen_sync(tu, PRE_SYNC, 61); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2731,15 +2622,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 64); + vm_base::gen_sync(tu, POST_SYNC, 61); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 65: SRLW */ + /* instruction 62: SRLW */ compile_ret_t __srlw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 65); + vm_base::gen_sync(tu, PRE_SYNC, 62); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2774,15 +2665,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 65); + vm_base::gen_sync(tu, POST_SYNC, 62); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 66: SRAW */ + /* instruction 63: SRAW */ compile_ret_t __sraw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 66); + vm_base::gen_sync(tu, PRE_SYNC, 63); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2817,15 +2708,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 66); + vm_base::gen_sync(tu, POST_SYNC, 63); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 67: MUL */ + /* instruction 64: MUL */ compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MUL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 67); + vm_base::gen_sync(tu, PRE_SYNC, 64); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2856,15 +2747,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 67); + vm_base::gen_sync(tu, POST_SYNC, 64); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 68: MULH */ + /* instruction 65: MULH */ compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 68); + vm_base::gen_sync(tu, PRE_SYNC, 65); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2897,15 +2788,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 68); + vm_base::gen_sync(tu, POST_SYNC, 65); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 69: MULHSU */ + /* instruction 66: MULHSU */ compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHSU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 69); + vm_base::gen_sync(tu, PRE_SYNC, 66); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2938,15 +2829,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 69); + vm_base::gen_sync(tu, POST_SYNC, 66); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 70: MULHU */ + /* instruction 67: MULHU */ compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 70); + vm_base::gen_sync(tu, PRE_SYNC, 67); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2979,15 +2870,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 70); + vm_base::gen_sync(tu, POST_SYNC, 67); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 71: DIV */ + /* instruction 68: DIV */ compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 71); + vm_base::gen_sync(tu, PRE_SYNC, 68); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3035,15 +2926,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 71); + vm_base::gen_sync(tu, POST_SYNC, 68); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 72: DIVU */ + /* instruction 69: DIVU */ compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 72); + vm_base::gen_sync(tu, PRE_SYNC, 69); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3071,15 +2962,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 72); + vm_base::gen_sync(tu, POST_SYNC, 69); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 73: REM */ + /* instruction 70: REM */ compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REM_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 73); + vm_base::gen_sync(tu, PRE_SYNC, 70); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3127,15 +3018,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 73); + vm_base::gen_sync(tu, POST_SYNC, 70); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 74: REMU */ + /* instruction 71: REMU */ compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 74); + vm_base::gen_sync(tu, PRE_SYNC, 71); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3163,15 +3054,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 74); + vm_base::gen_sync(tu, POST_SYNC, 71); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 75: MULW */ + /* instruction 72: MULW */ compile_ret_t __mulw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 75); + vm_base::gen_sync(tu, PRE_SYNC, 72); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3201,15 +3092,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 75); + vm_base::gen_sync(tu, POST_SYNC, 72); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 76: DIVW */ + /* instruction 73: DIVW */ compile_ret_t __divw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 76); + vm_base::gen_sync(tu, PRE_SYNC, 73); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3273,15 +3164,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 76); + vm_base::gen_sync(tu, POST_SYNC, 73); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 77: DIVUW */ + /* instruction 74: DIVUW */ compile_ret_t __divuw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVUW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 77); + vm_base::gen_sync(tu, PRE_SYNC, 74); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3321,15 +3212,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 77); + vm_base::gen_sync(tu, POST_SYNC, 74); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 78: REMW */ + /* instruction 75: REMW */ compile_ret_t __remw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 78); + vm_base::gen_sync(tu, PRE_SYNC, 75); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3394,15 +3285,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 78); + vm_base::gen_sync(tu, POST_SYNC, 75); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 79: REMUW */ + /* instruction 76: REMUW */ compile_ret_t __remuw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMUW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 79); + vm_base::gen_sync(tu, PRE_SYNC, 76); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3448,15 +3339,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 79); + vm_base::gen_sync(tu, POST_SYNC, 76); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 80: LR.W */ + /* instruction 77: LR.W */ compile_ret_t __lr_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 80); + vm_base::gen_sync(tu, PRE_SYNC, 77); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rl = ((bit_sub<25,1>(instr))); @@ -3487,15 +3378,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 80); + vm_base::gen_sync(tu, POST_SYNC, 77); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 81: SC.W */ + /* instruction 78: SC.W */ compile_ret_t __sc_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SC_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 81); + vm_base::gen_sync(tu, PRE_SYNC, 78); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3536,15 +3427,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 81); + vm_base::gen_sync(tu, POST_SYNC, 78); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 82: AMOSWAP.W */ + /* instruction 79: AMOSWAP.W */ compile_ret_t __amoswap_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOSWAP_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 82); + vm_base::gen_sync(tu, PRE_SYNC, 79); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3573,15 +3464,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 82); + vm_base::gen_sync(tu, POST_SYNC, 79); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 83: AMOADD.W */ + /* instruction 80: AMOADD.W */ compile_ret_t __amoadd_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOADD_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 83); + vm_base::gen_sync(tu, PRE_SYNC, 80); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3614,15 +3505,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 83); + vm_base::gen_sync(tu, POST_SYNC, 80); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 84: AMOXOR.W */ + /* instruction 81: AMOXOR.W */ compile_ret_t __amoxor_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOXOR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 84); + vm_base::gen_sync(tu, PRE_SYNC, 81); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3655,15 +3546,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 84); + vm_base::gen_sync(tu, POST_SYNC, 81); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 85: AMOAND.W */ + /* instruction 82: AMOAND.W */ compile_ret_t __amoand_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOAND_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 85); + vm_base::gen_sync(tu, PRE_SYNC, 82); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3696,15 +3587,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 85); + vm_base::gen_sync(tu, POST_SYNC, 82); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 86: AMOOR.W */ + /* instruction 83: AMOOR.W */ compile_ret_t __amoor_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOOR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 86); + vm_base::gen_sync(tu, PRE_SYNC, 83); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3737,15 +3628,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 86); + vm_base::gen_sync(tu, POST_SYNC, 83); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 87: AMOMIN.W */ + /* instruction 84: AMOMIN.W */ compile_ret_t __amomin_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMIN_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 87); + vm_base::gen_sync(tu, PRE_SYNC, 84); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3786,15 +3677,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 87); + vm_base::gen_sync(tu, POST_SYNC, 84); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 88: AMOMAX.W */ + /* instruction 85: AMOMAX.W */ compile_ret_t __amomax_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAX_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 88); + vm_base::gen_sync(tu, PRE_SYNC, 85); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3835,15 +3726,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 88); + vm_base::gen_sync(tu, POST_SYNC, 85); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 89: AMOMINU.W */ + /* instruction 86: AMOMINU.W */ compile_ret_t __amominu_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMINU_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 89); + vm_base::gen_sync(tu, PRE_SYNC, 86); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3880,15 +3771,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 89); + vm_base::gen_sync(tu, POST_SYNC, 86); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 90: AMOMAXU.W */ + /* instruction 87: AMOMAXU.W */ compile_ret_t __amomaxu_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAXU_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 90); + vm_base::gen_sync(tu, PRE_SYNC, 87); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3925,15 +3816,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 90); + vm_base::gen_sync(tu, POST_SYNC, 87); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 91: LR.D */ + /* instruction 88: LR.D */ compile_ret_t __lr_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LR_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 91); + vm_base::gen_sync(tu, PRE_SYNC, 88); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rl = ((bit_sub<25,1>(instr))); @@ -3964,15 +3855,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 91); + vm_base::gen_sync(tu, POST_SYNC, 88); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 92: SC.D */ + /* instruction 89: SC.D */ compile_ret_t __sc_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SC_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 92); + vm_base::gen_sync(tu, PRE_SYNC, 89); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4007,15 +3898,15 @@ private: tu.close_scope(); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 92); + vm_base::gen_sync(tu, POST_SYNC, 89); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 93: AMOSWAP.D */ + /* instruction 90: AMOSWAP.D */ compile_ret_t __amoswap_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOSWAP_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 93); + vm_base::gen_sync(tu, PRE_SYNC, 90); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4044,15 +3935,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 93); + vm_base::gen_sync(tu, POST_SYNC, 90); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 94: AMOADD.D */ + /* instruction 91: AMOADD.D */ compile_ret_t __amoadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 94); + vm_base::gen_sync(tu, PRE_SYNC, 91); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4085,15 +3976,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 94); + vm_base::gen_sync(tu, POST_SYNC, 91); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 95: AMOXOR.D */ + /* instruction 92: AMOXOR.D */ compile_ret_t __amoxor_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOXOR_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 95); + vm_base::gen_sync(tu, PRE_SYNC, 92); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4126,15 +4017,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 95); + vm_base::gen_sync(tu, POST_SYNC, 92); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 96: AMOAND.D */ + /* instruction 93: AMOAND.D */ compile_ret_t __amoand_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOAND_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 96); + vm_base::gen_sync(tu, PRE_SYNC, 93); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4167,15 +4058,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 96); + vm_base::gen_sync(tu, POST_SYNC, 93); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 97: AMOOR.D */ + /* instruction 94: AMOOR.D */ compile_ret_t __amoor_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOOR_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 97); + vm_base::gen_sync(tu, PRE_SYNC, 94); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4208,15 +4099,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 97); + vm_base::gen_sync(tu, POST_SYNC, 94); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 98: AMOMIN.D */ + /* instruction 95: AMOMIN.D */ compile_ret_t __amomin_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMIN_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 98); + vm_base::gen_sync(tu, PRE_SYNC, 95); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4257,15 +4148,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 98); + vm_base::gen_sync(tu, POST_SYNC, 95); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 99: AMOMAX.D */ + /* instruction 96: AMOMAX.D */ compile_ret_t __amomax_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAX_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 99); + vm_base::gen_sync(tu, PRE_SYNC, 96); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4306,15 +4197,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 99); + vm_base::gen_sync(tu, POST_SYNC, 96); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 100: AMOMINU.D */ + /* instruction 97: AMOMINU.D */ compile_ret_t __amominu_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMINU_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 100); + vm_base::gen_sync(tu, PRE_SYNC, 97); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4351,15 +4242,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 100); + vm_base::gen_sync(tu, POST_SYNC, 97); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 101: AMOMAXU.D */ + /* instruction 98: AMOMAXU.D */ compile_ret_t __amomaxu_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAXU_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 101); + vm_base::gen_sync(tu, PRE_SYNC, 98); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4396,15 +4287,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 101); + vm_base::gen_sync(tu, POST_SYNC, 98); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 102: FLW */ + /* instruction 99: FLW */ compile_ret_t __flw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 102); + vm_base::gen_sync(tu, PRE_SYNC, 99); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -4439,15 +4330,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 102); + vm_base::gen_sync(tu, POST_SYNC, 99); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 103: FSW */ + /* instruction 100: FSW */ compile_ret_t __fsw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 103); + vm_base::gen_sync(tu, PRE_SYNC, 100); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4475,15 +4366,15 @@ private: ), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 103); + vm_base::gen_sync(tu, POST_SYNC, 100); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 104: FMADD.S */ + /* instruction 101: FMADD.S */ compile_ret_t __fmadd_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMADD_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 104); + vm_base::gen_sync(tu, PRE_SYNC, 101); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4568,15 +4459,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 104); + vm_base::gen_sync(tu, POST_SYNC, 101); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 105: FMSUB.S */ + /* instruction 102: FMSUB.S */ compile_ret_t __fmsub_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMSUB_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 105); + vm_base::gen_sync(tu, PRE_SYNC, 102); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4661,15 +4552,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 105); + vm_base::gen_sync(tu, POST_SYNC, 102); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 106: FNMADD.S */ + /* instruction 103: FNMADD.S */ compile_ret_t __fnmadd_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMADD_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 106); + vm_base::gen_sync(tu, PRE_SYNC, 103); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4754,15 +4645,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 106); + vm_base::gen_sync(tu, POST_SYNC, 103); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 107: FNMSUB.S */ + /* instruction 104: FNMSUB.S */ compile_ret_t __fnmsub_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMSUB_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 107); + vm_base::gen_sync(tu, PRE_SYNC, 104); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4847,15 +4738,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 107); + vm_base::gen_sync(tu, POST_SYNC, 104); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 108: FADD.S */ + /* instruction 105: FADD.S */ compile_ret_t __fadd_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FADD_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 108); + vm_base::gen_sync(tu, PRE_SYNC, 105); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4926,15 +4817,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 108); + vm_base::gen_sync(tu, POST_SYNC, 105); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 109: FSUB.S */ + /* instruction 106: FSUB.S */ compile_ret_t __fsub_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSUB_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 109); + vm_base::gen_sync(tu, PRE_SYNC, 106); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5005,15 +4896,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 109); + vm_base::gen_sync(tu, POST_SYNC, 106); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 110: FMUL.S */ + /* instruction 107: FMUL.S */ compile_ret_t __fmul_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMUL_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 110); + vm_base::gen_sync(tu, PRE_SYNC, 107); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5084,15 +4975,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 110); + vm_base::gen_sync(tu, POST_SYNC, 107); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 111: FDIV.S */ + /* instruction 108: FDIV.S */ compile_ret_t __fdiv_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FDIV_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 111); + vm_base::gen_sync(tu, PRE_SYNC, 108); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5163,15 +5054,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 111); + vm_base::gen_sync(tu, POST_SYNC, 108); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 112: FSQRT.S */ + /* instruction 109: FSQRT.S */ compile_ret_t __fsqrt_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSQRT_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 112); + vm_base::gen_sync(tu, PRE_SYNC, 109); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5236,15 +5127,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 112); + vm_base::gen_sync(tu, POST_SYNC, 109); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 113: FSGNJ.S */ + /* instruction 110: FSGNJ.S */ compile_ret_t __fsgnj_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJ_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 113); + vm_base::gen_sync(tu, PRE_SYNC, 110); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5292,15 +5183,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 113); + vm_base::gen_sync(tu, POST_SYNC, 110); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 114: FSGNJN.S */ + /* instruction 111: FSGNJN.S */ compile_ret_t __fsgnjn_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJN_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 114); + vm_base::gen_sync(tu, PRE_SYNC, 111); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5348,15 +5239,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 114); + vm_base::gen_sync(tu, POST_SYNC, 111); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 115: FSGNJX.S */ + /* instruction 112: FSGNJX.S */ compile_ret_t __fsgnjx_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJX_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 115); + vm_base::gen_sync(tu, PRE_SYNC, 112); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5400,15 +5291,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 115); + vm_base::gen_sync(tu, POST_SYNC, 112); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 116: FMIN.S */ + /* instruction 113: FMIN.S */ compile_ret_t __fmin_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMIN_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 116); + vm_base::gen_sync(tu, PRE_SYNC, 113); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5466,15 +5357,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 116); + vm_base::gen_sync(tu, POST_SYNC, 113); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 117: FMAX.S */ + /* instruction 114: FMAX.S */ compile_ret_t __fmax_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMAX_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 117); + vm_base::gen_sync(tu, PRE_SYNC, 114); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5532,15 +5423,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 117); + vm_base::gen_sync(tu, POST_SYNC, 114); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 118: FCVT.W.S */ + /* instruction 115: FCVT.W.S */ compile_ret_t __fcvt_w_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_W_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 118); + vm_base::gen_sync(tu, PRE_SYNC, 115); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5592,15 +5483,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 118); + vm_base::gen_sync(tu, POST_SYNC, 115); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 119: FCVT.WU.S */ + /* instruction 116: FCVT.WU.S */ compile_ret_t __fcvt_wu_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_WU_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 119); + vm_base::gen_sync(tu, PRE_SYNC, 116); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5652,15 +5543,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 119); + vm_base::gen_sync(tu, POST_SYNC, 116); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 120: FEQ.S */ + /* instruction 117: FEQ.S */ compile_ret_t __feq_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FEQ_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 120); + vm_base::gen_sync(tu, PRE_SYNC, 117); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5715,15 +5606,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 120); + vm_base::gen_sync(tu, POST_SYNC, 117); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 121: FLT.S */ + /* instruction 118: FLT.S */ compile_ret_t __flt_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLT_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 121); + vm_base::gen_sync(tu, PRE_SYNC, 118); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5792,15 +5683,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 121); + vm_base::gen_sync(tu, POST_SYNC, 118); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 122: FLE.S */ + /* instruction 119: FLE.S */ compile_ret_t __fle_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLE_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 122); + vm_base::gen_sync(tu, PRE_SYNC, 119); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5855,15 +5746,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 122); + vm_base::gen_sync(tu, POST_SYNC, 119); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 123: FCLASS.S */ + /* instruction 120: FCLASS.S */ compile_ret_t __fclass_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCLASS_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 123); + vm_base::gen_sync(tu, PRE_SYNC, 120); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -5883,15 +5774,15 @@ private: ), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 123); + vm_base::gen_sync(tu, POST_SYNC, 120); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 124: FCVT.S.W */ + /* instruction 121: FCVT.S.W */ compile_ret_t __fcvt_s_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 124); + vm_base::gen_sync(tu, PRE_SYNC, 121); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5941,15 +5832,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 124); + vm_base::gen_sync(tu, POST_SYNC, 121); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 125: FCVT.S.WU */ + /* instruction 122: FCVT.S.WU */ compile_ret_t __fcvt_s_wu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_WU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 125); + vm_base::gen_sync(tu, PRE_SYNC, 122); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5999,15 +5890,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 125); + vm_base::gen_sync(tu, POST_SYNC, 122); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 126: FMV.X.W */ + /* instruction 123: FMV.X.W */ compile_ret_t __fmv_x_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_X_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 126); + vm_base::gen_sync(tu, PRE_SYNC, 123); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -6029,15 +5920,15 @@ private: false), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 126); + vm_base::gen_sync(tu, POST_SYNC, 123); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 127: FMV.W.X */ + /* instruction 124: FMV.W.X */ compile_ret_t __fmv_w_x(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_W_X_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 127); + vm_base::gen_sync(tu, PRE_SYNC, 124); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -6071,15 +5962,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 127); + vm_base::gen_sync(tu, POST_SYNC, 124); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 128: FCVT.L.S */ + /* instruction 125: FCVT.L.S */ compile_ret_t __fcvt_l_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_L_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 128); + vm_base::gen_sync(tu, PRE_SYNC, 125); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6117,15 +6008,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 128); + vm_base::gen_sync(tu, POST_SYNC, 125); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 129: FCVT.LU.S */ + /* instruction 126: FCVT.LU.S */ compile_ret_t __fcvt_lu_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_LU_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 129); + vm_base::gen_sync(tu, PRE_SYNC, 126); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6163,15 +6054,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 129); + vm_base::gen_sync(tu, POST_SYNC, 126); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 130: FCVT.S.L */ + /* instruction 127: FCVT.S.L */ compile_ret_t __fcvt_s_l(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_L_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 130); + vm_base::gen_sync(tu, PRE_SYNC, 127); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6208,15 +6099,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 130); + vm_base::gen_sync(tu, POST_SYNC, 127); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 131: FCVT.S.LU */ + /* instruction 128: FCVT.S.LU */ compile_ret_t __fcvt_s_lu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_LU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 131); + vm_base::gen_sync(tu, PRE_SYNC, 128); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6253,15 +6144,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 131); + vm_base::gen_sync(tu, POST_SYNC, 128); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 132: FLD */ + /* instruction 129: FLD */ compile_ret_t __fld(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 132); + vm_base::gen_sync(tu, PRE_SYNC, 129); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -6293,15 +6184,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 132); + vm_base::gen_sync(tu, POST_SYNC, 129); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 133: FSD */ + /* instruction 130: FSD */ compile_ret_t __fsd(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 133); + vm_base::gen_sync(tu, PRE_SYNC, 130); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -6329,15 +6220,15 @@ private: ), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 133); + vm_base::gen_sync(tu, POST_SYNC, 130); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 134: FMADD.D */ + /* instruction 131: FMADD.D */ compile_ret_t __fmadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 134); + vm_base::gen_sync(tu, PRE_SYNC, 131); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6401,15 +6292,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 134); + vm_base::gen_sync(tu, POST_SYNC, 131); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 135: FMSUB.D */ + /* instruction 132: FMSUB.D */ compile_ret_t __fmsub_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMSUB_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 135); + vm_base::gen_sync(tu, PRE_SYNC, 132); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6473,15 +6364,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 135); + vm_base::gen_sync(tu, POST_SYNC, 132); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 136: FNMADD.D */ + /* instruction 133: FNMADD.D */ compile_ret_t __fnmadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 136); + vm_base::gen_sync(tu, PRE_SYNC, 133); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6545,15 +6436,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 136); + vm_base::gen_sync(tu, POST_SYNC, 133); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 137: FNMSUB.D */ + /* instruction 134: FNMSUB.D */ compile_ret_t __fnmsub_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMSUB_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 137); + vm_base::gen_sync(tu, PRE_SYNC, 134); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6617,15 +6508,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 137); + vm_base::gen_sync(tu, POST_SYNC, 134); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 138: FADD.D */ + /* instruction 135: FADD.D */ compile_ret_t __fadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 138); + vm_base::gen_sync(tu, PRE_SYNC, 135); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6680,15 +6571,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 138); + vm_base::gen_sync(tu, POST_SYNC, 135); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 139: FSUB.D */ + /* instruction 136: FSUB.D */ compile_ret_t __fsub_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSUB_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 139); + vm_base::gen_sync(tu, PRE_SYNC, 136); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6743,15 +6634,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 139); + vm_base::gen_sync(tu, POST_SYNC, 136); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 140: FMUL.D */ + /* instruction 137: FMUL.D */ compile_ret_t __fmul_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMUL_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 140); + vm_base::gen_sync(tu, PRE_SYNC, 137); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6806,15 +6697,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 140); + vm_base::gen_sync(tu, POST_SYNC, 137); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 141: FDIV.D */ + /* instruction 138: FDIV.D */ compile_ret_t __fdiv_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FDIV_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 141); + vm_base::gen_sync(tu, PRE_SYNC, 138); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6869,15 +6760,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 141); + vm_base::gen_sync(tu, POST_SYNC, 138); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 142: FSQRT.D */ + /* instruction 139: FSQRT.D */ compile_ret_t __fsqrt_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSQRT_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 142); + vm_base::gen_sync(tu, PRE_SYNC, 139); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6927,15 +6818,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 142); + vm_base::gen_sync(tu, POST_SYNC, 139); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 143: FSGNJ.D */ + /* instruction 140: FSGNJ.D */ compile_ret_t __fsgnj_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJ_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 143); + vm_base::gen_sync(tu, PRE_SYNC, 140); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -6977,15 +6868,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 143); + vm_base::gen_sync(tu, POST_SYNC, 140); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 144: FSGNJN.D */ + /* instruction 141: FSGNJN.D */ compile_ret_t __fsgnjn_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJN_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 144); + vm_base::gen_sync(tu, PRE_SYNC, 141); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7027,15 +6918,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 144); + vm_base::gen_sync(tu, POST_SYNC, 141); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 145: FSGNJX.D */ + /* instruction 142: FSGNJX.D */ compile_ret_t __fsgnjx_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJX_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 145); + vm_base::gen_sync(tu, PRE_SYNC, 142); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7074,15 +6965,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 145); + vm_base::gen_sync(tu, POST_SYNC, 142); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 146: FMIN.D */ + /* instruction 143: FMIN.D */ compile_ret_t __fmin_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMIN_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 146); + vm_base::gen_sync(tu, PRE_SYNC, 143); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7130,15 +7021,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 146); + vm_base::gen_sync(tu, POST_SYNC, 143); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 147: FMAX.D */ + /* instruction 144: FMAX.D */ compile_ret_t __fmax_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMAX_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 147); + vm_base::gen_sync(tu, PRE_SYNC, 144); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7186,15 +7077,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 147); + vm_base::gen_sync(tu, POST_SYNC, 144); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 148: FCVT.S.D */ + /* instruction 145: FCVT.S.D */ compile_ret_t __fcvt_s_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 148); + vm_base::gen_sync(tu, PRE_SYNC, 145); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7223,15 +7114,15 @@ private: true)), rd + traits::F0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 148); + vm_base::gen_sync(tu, POST_SYNC, 145); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 149: FCVT.D.S */ + /* instruction 146: FCVT.D.S */ compile_ret_t __fcvt_d_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 149); + vm_base::gen_sync(tu, PRE_SYNC, 146); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7264,15 +7155,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 149); + vm_base::gen_sync(tu, POST_SYNC, 146); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 150: FEQ.D */ + /* instruction 147: FEQ.D */ compile_ret_t __feq_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FEQ_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 150); + vm_base::gen_sync(tu, PRE_SYNC, 147); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7313,15 +7204,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 150); + vm_base::gen_sync(tu, POST_SYNC, 147); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 151: FLT.D */ + /* instruction 148: FLT.D */ compile_ret_t __flt_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLT_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 151); + vm_base::gen_sync(tu, PRE_SYNC, 148); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7362,15 +7253,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 151); + vm_base::gen_sync(tu, POST_SYNC, 148); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 152: FLE.D */ + /* instruction 149: FLE.D */ compile_ret_t __fle_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLE_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 152); + vm_base::gen_sync(tu, PRE_SYNC, 149); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7411,15 +7302,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 152); + vm_base::gen_sync(tu, POST_SYNC, 149); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 153: FCLASS.D */ + /* instruction 150: FCLASS.D */ compile_ret_t __fclass_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCLASS_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 153); + vm_base::gen_sync(tu, PRE_SYNC, 150); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -7440,15 +7331,15 @@ private: ), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 153); + vm_base::gen_sync(tu, POST_SYNC, 150); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 154: FCVT.W.D */ + /* instruction 151: FCVT.W.D */ compile_ret_t __fcvt_w_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_W_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 154); + vm_base::gen_sync(tu, PRE_SYNC, 151); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7486,15 +7377,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 154); + vm_base::gen_sync(tu, POST_SYNC, 151); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 155: FCVT.WU.D */ + /* instruction 152: FCVT.WU.D */ compile_ret_t __fcvt_wu_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_WU_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 155); + vm_base::gen_sync(tu, PRE_SYNC, 152); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7532,15 +7423,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 155); + vm_base::gen_sync(tu, POST_SYNC, 152); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 156: FCVT.D.W */ + /* instruction 153: FCVT.D.W */ compile_ret_t __fcvt_d_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 156); + vm_base::gen_sync(tu, PRE_SYNC, 153); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7580,15 +7471,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 156); + vm_base::gen_sync(tu, POST_SYNC, 153); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 157: FCVT.D.WU */ + /* instruction 154: FCVT.D.WU */ compile_ret_t __fcvt_d_wu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_WU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 157); + vm_base::gen_sync(tu, PRE_SYNC, 154); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7628,15 +7519,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 157); + vm_base::gen_sync(tu, POST_SYNC, 154); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 158: FCVT.L.D */ + /* instruction 155: FCVT.L.D */ compile_ret_t __fcvt_l_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_L_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 158); + vm_base::gen_sync(tu, PRE_SYNC, 155); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7674,15 +7565,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 158); + vm_base::gen_sync(tu, POST_SYNC, 155); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 159: FCVT.LU.D */ + /* instruction 156: FCVT.LU.D */ compile_ret_t __fcvt_lu_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_LU_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 159); + vm_base::gen_sync(tu, PRE_SYNC, 156); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7720,15 +7611,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 159); + vm_base::gen_sync(tu, POST_SYNC, 156); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 160: FCVT.D.L */ + /* instruction 157: FCVT.D.L */ compile_ret_t __fcvt_d_l(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_L_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 160); + vm_base::gen_sync(tu, PRE_SYNC, 157); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7765,15 +7656,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 160); + vm_base::gen_sync(tu, POST_SYNC, 157); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 161: FCVT.D.LU */ + /* instruction 158: FCVT.D.LU */ compile_ret_t __fcvt_d_lu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_LU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 161); + vm_base::gen_sync(tu, PRE_SYNC, 158); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7810,15 +7701,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 161); + vm_base::gen_sync(tu, POST_SYNC, 158); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 162: FMV.X.D */ + /* instruction 159: FMV.X.D */ compile_ret_t __fmv_x_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_X_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 162); + vm_base::gen_sync(tu, PRE_SYNC, 159); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -7837,15 +7728,15 @@ private: false), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 162); + vm_base::gen_sync(tu, POST_SYNC, 159); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 163: FMV.D.X */ + /* instruction 160: FMV.D.X */ compile_ret_t __fmv_d_x(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_D_X_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 163); + vm_base::gen_sync(tu, PRE_SYNC, 160); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -7864,802 +7755,15 @@ private: true), rd + traits::F0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 163); + vm_base::gen_sync(tu, POST_SYNC, 160); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 164: C.ADDI4SPN */ - compile_ret_t __c_addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_ADDI4SPN_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 164); - uint8_t rd = ((bit_sub<2,3>(instr))); - uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - if(imm == 0){ - this->gen_raise_trap(tu, 0, 2); - } - tu.store(tu.add( - tu.load(2 + traits::X0, 0), - tu.constant(imm, 64U)), rd + 8 + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 164); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 165: C.LW */ - compile_ret_t __c_lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_LW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 165); - uint8_t rd = ((bit_sub<2,3>(instr))); - uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"), - fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.load(rs1 + 8 + traits::X0, 0), - tu.constant(uimm, 64U)), 64); - tu.store(tu.ext( - tu.read_mem(traits::MEM, offs_val, 32), - 64, - false), rd + 8 + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 165); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 166: C.SW */ - compile_ret_t __c_sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 166); - uint8_t rs2 = ((bit_sub<2,3>(instr))); - uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"), - fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.load(rs1 + 8 + traits::X0, 0), - tu.constant(uimm, 64U)), 64); - tu.write_mem( - traits::MEM, - offs_val, - tu.trunc(tu.load(rs2 + 8 + traits::X0, 0), 32)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 166); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 167: C.ADDI */ - compile_ret_t __c_addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_ADDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 167); - int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - tu.store(tu.add( - tu.ext( - tu.load(rs1 + traits::X0, 0), - 64, false), - tu.constant(imm, 64U)), rs1 + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 167); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 168: C.NOP */ - compile_ret_t __c_nop(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_NOP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 168); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c.nop"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - tu.close_scope(); - /* TODO: describe operations for C.NOP ! */ - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 168); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 169: C.ADDIW */ - compile_ret_t __c_addiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_ADDIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 169); - int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addiw"), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - if(rs1 != 0){ - auto res_val = tu.assignment(tu.add( - tu.ext( - tu.trunc( - tu.load(rs1 + traits::X0, 0), - 32 - ), - 32, false), - tu.constant(imm, 32U)), 32); - tu.store(tu.ext( - res_val, - 64, - false), rs1 + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 169); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 170: C.LI */ - compile_ret_t __c_li(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_LI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 170); - int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t rd = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - if(rd == 0){ - this->gen_raise_trap(tu, 0, 2); - } - tu.store(tu.constant(imm, 64U), rd + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 170); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 171: C.LUI */ - compile_ret_t __c_lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_LUI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 171); - int32_t imm = signextend((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); - uint8_t rd = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - if(rd == 0){ - this->gen_raise_trap(tu, 0, 2); - } - if(imm == 0){ - this->gen_raise_trap(tu, 0, 2); - } - tu.store(tu.constant(imm, 64U), rd + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 171); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 172: C.ADDI16SP */ - compile_ret_t __c_addi16sp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_ADDI16SP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 172); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.addi16sp"), - fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - tu.store(tu.add( - tu.ext( - tu.load(2 + traits::X0, 0), - 64, false), - tu.constant(imm, 64U)), 2 + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 172); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 173: C.SRLI */ - compile_ret_t __c_srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 173); - uint8_t shamt = ((bit_sub<2,5>(instr))); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"), - fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - uint8_t rs1_idx_val = rs1 + 8; - tu.store(tu.lshr( - tu.load(rs1_idx_val + traits::X0, 0), - tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 173); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 174: C.SRAI */ - compile_ret_t __c_srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 174); - uint8_t shamt = ((bit_sub<2,5>(instr))); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), - fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - uint8_t rs1_idx_val = rs1 + 8; - tu.store(tu.ashr( - tu.load(rs1_idx_val + traits::X0, 0), - tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 174); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 175: C.ANDI */ - compile_ret_t __c_andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_ANDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 175); - int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"), - fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - uint8_t rs1_idx_val = rs1 + 8; - tu.store(tu.l_and( - tu.ext( - tu.load(rs1_idx_val + traits::X0, 0), - 64, false), - tu.constant(imm, 64U)), rs1_idx_val + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 175); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 176: C.SUB */ - compile_ret_t __c_sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 176); - uint8_t rs2 = ((bit_sub<2,3>(instr))); - uint8_t rd = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"), - fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - uint8_t rd_idx_val = rd + 8; - tu.store(tu.sub( - tu.load(rd_idx_val + traits::X0, 0), - tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 176); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 177: C.XOR */ - compile_ret_t __c_xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 177); - uint8_t rs2 = ((bit_sub<2,3>(instr))); - uint8_t rd = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"), - fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - uint8_t rd_idx_val = rd + 8; - tu.store(tu.l_xor( - tu.load(rd_idx_val + traits::X0, 0), - tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 177); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 178: C.OR */ - compile_ret_t __c_or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 178); - uint8_t rs2 = ((bit_sub<2,3>(instr))); - uint8_t rd = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"), - fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - uint8_t rd_idx_val = rd + 8; - tu.store(tu.l_or( - tu.load(rd_idx_val + traits::X0, 0), - tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 178); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 179: C.AND */ - compile_ret_t __c_and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 179); - uint8_t rs2 = ((bit_sub<2,3>(instr))); - uint8_t rd = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"), - fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - uint8_t rd_idx_val = rd + 8; - tu.store(tu.l_and( - tu.load(rd_idx_val + traits::X0, 0), - tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 179); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 180: C.J */ - compile_ret_t __c_j(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_J_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 180); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"), - fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.add( - tu.ext( - cur_pc_val, - 64, false), - tu.constant(imm, 64U)), 64); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 64U, true), tu.constant(pc.val, 64U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 180); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 181: C.BEQZ */ - compile_ret_t __c_beqz(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_BEQZ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 181); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"), - fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.choose( - tu.icmp( - ICmpInst::ICMP_EQ, - tu.load(rs1 + 8 + traits::X0, 0), - tu.constant(0, 64U)), - tu.add( - tu.ext( - cur_pc_val, - 64, false), - tu.constant(imm, 64U)), - tu.add( - cur_pc_val, - tu.constant(2, 64U))), 64); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 64U, true), tu.constant(pc.val, 64U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 181); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 182: C.BNEZ */ - compile_ret_t __c_bnez(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_BNEZ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 182); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"), - fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.choose( - tu.icmp( - ICmpInst::ICMP_NE, - tu.load(rs1 + 8 + traits::X0, 0), - tu.constant(0, 64U)), - tu.add( - tu.ext( - cur_pc_val, - 64, false), - tu.constant(imm, 64U)), - tu.add( - cur_pc_val, - tu.constant(2, 64U))), 64); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 64U, true), tu.constant(pc.val, 64U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 182); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 183: C.SLLI */ - compile_ret_t __c_slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 183); - uint8_t shamt = ((bit_sub<2,5>(instr))); - uint8_t rs1 = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - if(rs1 == 0){ - this->gen_raise_trap(tu, 0, 2); - } - tu.store(tu.shl( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rs1 + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 183); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 184: C.LWSP */ - compile_ret_t __c_lwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_LWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 184); - uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); - uint8_t rd = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"), - fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.load(2 + traits::X0, 0), - tu.constant(uimm, 64U)), 64); - tu.store(tu.ext( - tu.read_mem(traits::MEM, offs_val, 32), - 64, - false), rd + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 184); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 185: C.MV */ - compile_ret_t __c_mv(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_MV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 185); - uint8_t rs2 = ((bit_sub<2,5>(instr))); - uint8_t rd = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"), - fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - tu.store(tu.load(rs2 + traits::X0, 0), rd + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 185); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 186: C.JR */ - compile_ret_t __c_jr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_JR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 186); - uint8_t rs1 = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"), - fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits::X0, 0), 64); - tu.store(PC_val_v, traits::NEXT_PC); - tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 186); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 187: C.ADD */ - compile_ret_t __c_add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 187); - uint8_t rs2 = ((bit_sub<2,5>(instr))); - uint8_t rd = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"), - fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - tu.store(tu.add( - tu.load(rd + traits::X0, 0), - tu.load(rs2 + traits::X0, 0)), rd + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 187); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 188: C.JALR */ - compile_ret_t __c_jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_JALR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 188); - uint8_t rs1 = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"), - fmt::arg("rs1", name(rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - tu.store(tu.add( - cur_pc_val, - tu.constant(2, 64U)), 1 + traits::X0); - auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits::X0, 0), 64); - tu.store(PC_val_v, traits::NEXT_PC); - tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 188); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 189: C.EBREAK */ - compile_ret_t __c_ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 189); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c.ebreak"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - this->gen_raise_trap(tu, 0, 3); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 189); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 190: C.SWSP */ - compile_ret_t __c_swsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 190); - uint8_t rs2 = ((bit_sub<2,5>(instr))); - uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"), - fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.load(2 + traits::X0, 0), - tu.constant(uimm, 64U)), 64); - tu.write_mem( - traits::MEM, - offs_val, - tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 190); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 191: DII */ - compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("DII_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 191); - if(this->disass_enabled){ - /* generate console output when executing the command */ - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "dii"); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - this->gen_raise_trap(tu, 0, 2); - tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 191); - gen_trap_check(tu); - return std::make_tuple(BRANCH); - } - - /* instruction 192: C.LD */ + /* instruction 161: C.LD */ compile_ret_t __c_ld(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_LD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 192); + vm_base::gen_sync(tu, PRE_SYNC, 161); uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -8682,15 +7786,15 @@ private: false), rd + 8 + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 192); + vm_base::gen_sync(tu, POST_SYNC, 161); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 193: C.SD */ + /* instruction 162: C.SD */ compile_ret_t __c_sd(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 193); + vm_base::gen_sync(tu, PRE_SYNC, 162); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -8713,15 +7817,15 @@ private: tu.trunc(tu.load(rs2 + 8 + traits::X0, 0), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 193); + vm_base::gen_sync(tu, POST_SYNC, 162); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 194: C.LDSP */ + /* instruction 163: C.LDSP */ compile_ret_t __c_ldsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_LDSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 194); + vm_base::gen_sync(tu, PRE_SYNC, 163); uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -8745,15 +7849,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 194); + vm_base::gen_sync(tu, POST_SYNC, 163); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 195: C.SDSP */ + /* instruction 164: C.SDSP */ compile_ret_t __c_sdsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SDSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 195); + vm_base::gen_sync(tu, PRE_SYNC, 164); uint8_t rs2 = ((bit_sub<2,5>(instr))); uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); if(this->disass_enabled){ @@ -8775,15 +7879,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 195); + vm_base::gen_sync(tu, POST_SYNC, 164); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 196: C.FLD */ + /* instruction 165: C.FLD */ compile_ret_t __c_fld(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_FLD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 196); + vm_base::gen_sync(tu, PRE_SYNC, 165); uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -8813,15 +7917,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 196); + vm_base::gen_sync(tu, POST_SYNC, 165); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 197: C.FSD */ + /* instruction 166: C.FSD */ compile_ret_t __c_fsd(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_FSD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 197); + vm_base::gen_sync(tu, PRE_SYNC, 166); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -8847,15 +7951,15 @@ private: ), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 197); + vm_base::gen_sync(tu, POST_SYNC, 166); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 198: C.FLDSP */ + /* instruction 167: C.FLDSP */ compile_ret_t __c_fldsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_FLDSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 198); + vm_base::gen_sync(tu, PRE_SYNC, 167); uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -8887,15 +7991,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 198); + vm_base::gen_sync(tu, POST_SYNC, 167); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 199: C.FSDSP */ + /* instruction 168: C.FSDSP */ compile_ret_t __c_fsdsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_FSDSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 199); + vm_base::gen_sync(tu, PRE_SYNC, 168); uint8_t rs2 = ((bit_sub<2,5>(instr))); uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); if(this->disass_enabled){ @@ -8920,15 +8024,802 @@ private: ), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 199); + vm_base::gen_sync(tu, POST_SYNC, 168); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 200: C.SUBW */ + /* instruction 169: C.ADDI4SPN */ + compile_ret_t __c_addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_ADDI4SPN_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 169); + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + if(imm == 0){ + this->gen_raise_trap(tu, 0, 2); + } + tu.store(tu.add( + tu.load(2 + traits::X0, 0), + tu.constant(imm, 64U)), rd + 8 + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 169); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 170: C.LW */ + compile_ret_t __c_lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_LW_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 170); + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.load(rs1 + 8 + traits::X0, 0), + tu.constant(uimm, 64U)), 64); + tu.store(tu.ext( + tu.read_mem(traits::MEM, offs_val, 32), + 64, + false), rd + 8 + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 170); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 171: C.SW */ + compile_ret_t __c_sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SW_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 171); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.load(rs1 + 8 + traits::X0, 0), + tu.constant(uimm, 64U)), 64); + tu.write_mem( + traits::MEM, + offs_val, + tu.trunc(tu.load(rs2 + 8 + traits::X0, 0), 32)); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 171); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 172: C.ADDI */ + compile_ret_t __c_addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_ADDI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 172); + int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + tu.store(tu.add( + tu.ext( + tu.load(rs1 + traits::X0, 0), + 64, false), + tu.constant(imm, 64U)), rs1 + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 172); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 173: C.NOP */ + compile_ret_t __c_nop(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_NOP_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 173); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c.nop"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + tu.close_scope(); + /* TODO: describe operations for C.NOP ! */ + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 173); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 174: C.ADDIW */ + compile_ret_t __c_addiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_ADDIW_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 174); + int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addiw"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + if(rs1 != 0){ + auto res_val = tu.assignment(tu.add( + tu.ext( + tu.trunc( + tu.load(rs1 + traits::X0, 0), + 32 + ), + 32, false), + tu.constant(imm, 32U)), 32); + tu.store(tu.ext( + res_val, + 64, + false), rs1 + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 174); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 175: C.LI */ + compile_ret_t __c_li(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_LI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 175); + int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + if(rd == 0){ + this->gen_raise_trap(tu, 0, 2); + } + tu.store(tu.constant(imm, 64U), rd + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 175); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 176: C.LUI */ + compile_ret_t __c_lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_LUI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 176); + int32_t imm = signextend((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + if(rd == 0){ + this->gen_raise_trap(tu, 0, 2); + } + if(imm == 0){ + this->gen_raise_trap(tu, 0, 2); + } + tu.store(tu.constant(imm, 64U), rd + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 176); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 177: C.ADDI16SP */ + compile_ret_t __c_addi16sp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_ADDI16SP_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 177); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.addi16sp"), + fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + tu.store(tu.add( + tu.ext( + tu.load(2 + traits::X0, 0), + 64, false), + tu.constant(imm, 64U)), 2 + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 177); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 178: C.SRLI */ + compile_ret_t __c_srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SRLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 178); + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + uint8_t rs1_idx_val = rs1 + 8; + tu.store(tu.lshr( + tu.load(rs1_idx_val + traits::X0, 0), + tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 178); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 179: C.SRAI */ + compile_ret_t __c_srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SRAI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 179); + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + uint8_t rs1_idx_val = rs1 + 8; + tu.store(tu.ashr( + tu.load(rs1_idx_val + traits::X0, 0), + tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 179); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 180: C.ANDI */ + compile_ret_t __c_andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_ANDI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 180); + int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + uint8_t rs1_idx_val = rs1 + 8; + tu.store(tu.l_and( + tu.ext( + tu.load(rs1_idx_val + traits::X0, 0), + 64, false), + tu.constant(imm, 64U)), rs1_idx_val + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 180); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 181: C.SUB */ + compile_ret_t __c_sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SUB_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 181); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + uint8_t rd_idx_val = rd + 8; + tu.store(tu.sub( + tu.load(rd_idx_val + traits::X0, 0), + tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 181); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 182: C.XOR */ + compile_ret_t __c_xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_XOR_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 182); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + uint8_t rd_idx_val = rd + 8; + tu.store(tu.l_xor( + tu.load(rd_idx_val + traits::X0, 0), + tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 182); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 183: C.OR */ + compile_ret_t __c_or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_OR_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 183); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + uint8_t rd_idx_val = rd + 8; + tu.store(tu.l_or( + tu.load(rd_idx_val + traits::X0, 0), + tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 183); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 184: C.AND */ + compile_ret_t __c_and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_AND_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 184); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + uint8_t rd_idx_val = rd + 8; + tu.store(tu.l_and( + tu.load(rd_idx_val + traits::X0, 0), + tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 184); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 185: C.J */ + compile_ret_t __c_j(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_J_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 185); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"), + fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.add( + tu.ext( + cur_pc_val, + 64, false), + tu.constant(imm, 64U)), 64); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 64U, true), tu.constant(pc.val, 64U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 185); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 186: C.BEQZ */ + compile_ret_t __c_beqz(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_BEQZ_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 186); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.choose( + tu.icmp( + ICmpInst::ICMP_EQ, + tu.load(rs1 + 8 + traits::X0, 0), + tu.constant(0, 64U)), + tu.add( + tu.ext( + cur_pc_val, + 64, false), + tu.constant(imm, 64U)), + tu.add( + cur_pc_val, + tu.constant(2, 64U))), 64); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 64U, true), tu.constant(pc.val, 64U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 186); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 187: C.BNEZ */ + compile_ret_t __c_bnez(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_BNEZ_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 187); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.choose( + tu.icmp( + ICmpInst::ICMP_NE, + tu.load(rs1 + 8 + traits::X0, 0), + tu.constant(0, 64U)), + tu.add( + tu.ext( + cur_pc_val, + 64, false), + tu.constant(imm, 64U)), + tu.add( + cur_pc_val, + tu.constant(2, 64U))), 64); + tu.store(PC_val_v, traits::NEXT_PC); + auto is_cont_v = tu.choose( + tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 64U, true), tu.constant(pc.val, 64U)), + tu.constant(0U, 32), tu.constant(1U, 32)); + tu.store(is_cont_v, traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 187); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 188: C.SLLI */ + compile_ret_t __c_slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SLLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 188); + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + if(rs1 == 0){ + this->gen_raise_trap(tu, 0, 2); + } + tu.store(tu.shl( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rs1 + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 188); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 189: C.LWSP */ + compile_ret_t __c_lwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_LWSP_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 189); + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.load(2 + traits::X0, 0), + tu.constant(uimm, 64U)), 64); + tu.store(tu.ext( + tu.read_mem(traits::MEM, offs_val, 32), + 64, + false), rd + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 189); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 190: C.MV */ + compile_ret_t __c_mv(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_MV_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 190); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + tu.store(tu.load(rs2 + traits::X0, 0), rd + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 190); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 191: C.JR */ + compile_ret_t __c_jr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_JR_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 191); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"), + fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits::X0, 0), 64); + tu.store(PC_val_v, traits::NEXT_PC); + tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 191); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 192: C.ADD */ + compile_ret_t __c_add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_ADD_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 192); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + tu.store(tu.add( + tu.load(rd + traits::X0, 0), + tu.load(rs2 + traits::X0, 0)), rd + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 192); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 193: C.JALR */ + compile_ret_t __c_jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_JALR_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 193); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"), + fmt::arg("rs1", name(rs1))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + tu.store(tu.add( + cur_pc_val, + tu.constant(2, 64U)), 1 + traits::X0); + auto PC_val_v = tu.assignment("PC_val", tu.load(rs1 + traits::X0, 0), 64); + tu.store(PC_val_v, traits::NEXT_PC); + tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 193); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 194: C.EBREAK */ + compile_ret_t __c_ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_EBREAK_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 194); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c.ebreak"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + this->gen_raise_trap(tu, 0, 3); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 194); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 195: C.SWSP */ + compile_ret_t __c_swsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SWSP_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 195); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto offs_val = tu.assignment(tu.add( + tu.load(2 + traits::X0, 0), + tu.constant(uimm, 64U)), 64); + tu.write_mem( + traits::MEM, + offs_val, + tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 195); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 196: DII */ + compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("DII_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 196); + if(this->disass_enabled){ + /* generate console output when executing the command */ + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "dii"); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + this->gen_raise_trap(tu, 0, 2); + tu.close_scope(); + vm_base::gen_sync(tu, POST_SYNC, 196); + gen_trap_check(tu); + return std::make_tuple(BRANCH); + } + + /* instruction 197: C.SUBW */ compile_ret_t __c_subw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SUBW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 200); + vm_base::gen_sync(tu, PRE_SYNC, 197); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8956,15 +8847,15 @@ private: false), rd + 8 + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 200); + vm_base::gen_sync(tu, POST_SYNC, 197); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 201: C.ADDW */ + /* instruction 198: C.ADDW */ compile_ret_t __c_addw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_ADDW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 201); + vm_base::gen_sync(tu, PRE_SYNC, 198); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8992,92 +8883,13 @@ private: false), rd + 8 + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 201); + vm_base::gen_sync(tu, POST_SYNC, 198); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 202: C.SRLI */ - compile_ret_t __c_srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 202); - uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"), - fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - uint8_t rs1_idx_val = rs1 + 8; - tu.store(tu.lshr( - tu.load(rs1_idx_val + traits::X0, 0), - tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 202); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 203: C.SRAI */ - compile_ret_t __c_srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 203); - uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), - fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - uint8_t rs1_idx_val = rs1 + 8; - tu.store(tu.ashr( - tu.load(rs1_idx_val + traits::X0, 0), - tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 203); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 204: C.SLLI */ - compile_ret_t __c_slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 204); - uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - if(rs1 == 0){ - this->gen_raise_trap(tu, 0, 2); - } - tu.store(tu.shl( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rs1 + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 204); - gen_trap_check(tu); - return std::make_tuple(CONT); + /* instruction 199: C.SRLI64 */ + compile_ret_t __c_srli64(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ } /**************************************************************************** diff --git a/src/vm/tcc/vm_rv64i.cpp b/src/vm/tcc/vm_rv64i.cpp index e57c22a..4080a49 100644 --- a/src/vm/tcc/vm_rv64i.cpp +++ b/src/vm/tcc/vm_rv64i.cpp @@ -182,7 +182,7 @@ private: compile_func op; }; - const std::array instr_descr = {{ + const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI, encoding '.........................0110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, @@ -232,12 +232,6 @@ private: {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, /* instruction ANDI, encoding '.................111.....0010011' */ {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, - /* instruction SLLI, encoding '0000000..........001.....0010011' */ - {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, - /* instruction SRLI, encoding '0000000..........101.....0010011' */ - {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, - /* instruction SRAI, encoding '0100000..........101.....0010011' */ - {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, /* instruction ADD, encoding '0000000..........000.....0110011' */ {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, /* instruction SUB, encoding '0100000..........000.....0110011' */ @@ -1183,109 +1177,10 @@ private: return std::make_tuple(CONT); } - /* instruction 24: SLLI */ - compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 24); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(shamt > 31){ - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0){ - tu.store(tu.shl( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); - } - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 24); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 25: SRLI */ - compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 25); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(shamt > 31){ - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0){ - tu.store(tu.lshr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); - } - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 25); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 26: SRAI */ - compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 26); - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+4; - tu.open_scope(); - if(shamt > 31){ - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0){ - tu.store(tu.ashr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); - } - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 26); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 27: ADD */ + /* instruction 24: ADD */ compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 27); + vm_base::gen_sync(tu, PRE_SYNC, 24); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1306,15 +1201,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 27); + vm_base::gen_sync(tu, POST_SYNC, 24); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 28: SUB */ + /* instruction 25: SUB */ compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 28); + vm_base::gen_sync(tu, PRE_SYNC, 25); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1335,15 +1230,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 28); + vm_base::gen_sync(tu, POST_SYNC, 25); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 29: SLL */ + /* instruction 26: SLL */ compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 29); + vm_base::gen_sync(tu, PRE_SYNC, 26); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1368,15 +1263,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 29); + vm_base::gen_sync(tu, POST_SYNC, 26); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 30: SLT */ + /* instruction 27: SLT */ compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 30); + vm_base::gen_sync(tu, PRE_SYNC, 27); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1405,15 +1300,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 30); + vm_base::gen_sync(tu, POST_SYNC, 27); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 31: SLTU */ + /* instruction 28: SLTU */ compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 31); + vm_base::gen_sync(tu, PRE_SYNC, 28); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1444,15 +1339,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 31); + vm_base::gen_sync(tu, POST_SYNC, 28); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 32: XOR */ + /* instruction 29: XOR */ compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 32); + vm_base::gen_sync(tu, PRE_SYNC, 29); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1473,15 +1368,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 32); + vm_base::gen_sync(tu, POST_SYNC, 29); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 33: SRL */ + /* instruction 30: SRL */ compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 33); + vm_base::gen_sync(tu, PRE_SYNC, 30); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1506,15 +1401,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 33); + vm_base::gen_sync(tu, POST_SYNC, 30); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 34: SRA */ + /* instruction 31: SRA */ compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 34); + vm_base::gen_sync(tu, PRE_SYNC, 31); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1539,15 +1434,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 34); + vm_base::gen_sync(tu, POST_SYNC, 31); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 35: OR */ + /* instruction 32: OR */ compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 35); + vm_base::gen_sync(tu, PRE_SYNC, 32); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1568,15 +1463,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 35); + vm_base::gen_sync(tu, POST_SYNC, 32); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 36: AND */ + /* instruction 33: AND */ compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 36); + vm_base::gen_sync(tu, PRE_SYNC, 33); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1597,15 +1492,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 36); + vm_base::gen_sync(tu, POST_SYNC, 33); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 37: FENCE */ + /* instruction 34: FENCE */ compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 37); + vm_base::gen_sync(tu, PRE_SYNC, 34); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t succ = ((bit_sub<20,4>(instr))); @@ -1627,15 +1522,15 @@ private: tu.constant(succ, 64U)), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 37); + vm_base::gen_sync(tu, POST_SYNC, 34); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 38: FENCE_I */ + /* instruction 35: FENCE_I */ compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_I_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 38); + vm_base::gen_sync(tu, PRE_SYNC, 35); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -1653,15 +1548,15 @@ private: tu.close_scope(); tu.store(tu.constant(std::numeric_limits::max(), 32),traits::LAST_BRANCH); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 38); + vm_base::gen_sync(tu, POST_SYNC, 35); gen_trap_check(tu); return std::make_tuple(FLUSH); } - /* instruction 39: ECALL */ + /* instruction 36: ECALL */ compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ECALL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 39); + vm_base::gen_sync(tu, PRE_SYNC, 36); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ecall"); @@ -1671,15 +1566,15 @@ private: tu.open_scope(); this->gen_raise_trap(tu, 0, 11); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 39); + vm_base::gen_sync(tu, POST_SYNC, 36); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 40: EBREAK */ + /* instruction 37: EBREAK */ compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 40); + vm_base::gen_sync(tu, PRE_SYNC, 37); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ebreak"); @@ -1689,15 +1584,15 @@ private: tu.open_scope(); this->gen_raise_trap(tu, 0, 3); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 40); + vm_base::gen_sync(tu, POST_SYNC, 37); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 41: URET */ + /* instruction 38: URET */ compile_ret_t __uret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("URET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 41); + vm_base::gen_sync(tu, PRE_SYNC, 38); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "uret"); @@ -1707,15 +1602,15 @@ private: tu.open_scope(); this->gen_leave_trap(tu, 0); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 41); + vm_base::gen_sync(tu, POST_SYNC, 38); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 42: SRET */ + /* instruction 39: SRET */ compile_ret_t __sret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 42); + vm_base::gen_sync(tu, PRE_SYNC, 39); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "sret"); @@ -1725,15 +1620,15 @@ private: tu.open_scope(); this->gen_leave_trap(tu, 1); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 42); + vm_base::gen_sync(tu, POST_SYNC, 39); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 43: MRET */ + /* instruction 40: MRET */ compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 43); + vm_base::gen_sync(tu, PRE_SYNC, 40); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "mret"); @@ -1743,15 +1638,15 @@ private: tu.open_scope(); this->gen_leave_trap(tu, 3); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 43); + vm_base::gen_sync(tu, POST_SYNC, 40); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 44: WFI */ + /* instruction 41: WFI */ compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("WFI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 44); + vm_base::gen_sync(tu, PRE_SYNC, 41); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "wfi"); @@ -1762,15 +1657,15 @@ private: this->gen_wait(tu, 1); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 44); + vm_base::gen_sync(tu, POST_SYNC, 41); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 45: SFENCE.VMA */ + /* instruction 42: SFENCE.VMA */ compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SFENCE_VMA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 45); + vm_base::gen_sync(tu, PRE_SYNC, 42); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -1790,15 +1685,15 @@ private: tu.trunc(tu.constant(rs2, 64U), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 45); + vm_base::gen_sync(tu, POST_SYNC, 42); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 46: CSRRW */ + /* instruction 43: CSRRW */ compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 46); + vm_base::gen_sync(tu, PRE_SYNC, 43); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1828,15 +1723,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 46); + vm_base::gen_sync(tu, POST_SYNC, 43); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 47: CSRRS */ + /* instruction 44: CSRRS */ compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRS_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 47); + vm_base::gen_sync(tu, PRE_SYNC, 44); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1865,15 +1760,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 47); + vm_base::gen_sync(tu, POST_SYNC, 44); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 48: CSRRC */ + /* instruction 45: CSRRC */ compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRC_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 48); + vm_base::gen_sync(tu, PRE_SYNC, 45); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1902,15 +1797,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 48); + vm_base::gen_sync(tu, POST_SYNC, 45); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 49: CSRRWI */ + /* instruction 46: CSRRWI */ compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRWI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 49); + vm_base::gen_sync(tu, PRE_SYNC, 46); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1936,15 +1831,15 @@ private: true), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 49); + vm_base::gen_sync(tu, POST_SYNC, 46); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 50: CSRRSI */ + /* instruction 47: CSRRSI */ compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRSI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 50); + vm_base::gen_sync(tu, PRE_SYNC, 47); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1975,15 +1870,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 50); + vm_base::gen_sync(tu, POST_SYNC, 47); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 51: CSRRCI */ + /* instruction 48: CSRRCI */ compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRCI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 51); + vm_base::gen_sync(tu, PRE_SYNC, 48); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -2014,15 +1909,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 51); + vm_base::gen_sync(tu, POST_SYNC, 48); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 52: LWU */ + /* instruction 49: LWU */ compile_ret_t __lwu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LWU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 52); + vm_base::gen_sync(tu, PRE_SYNC, 49); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -2049,15 +1944,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 52); + vm_base::gen_sync(tu, POST_SYNC, 49); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 53: LD */ + /* instruction 50: LD */ compile_ret_t __ld(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 53); + vm_base::gen_sync(tu, PRE_SYNC, 50); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -2084,15 +1979,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 53); + vm_base::gen_sync(tu, POST_SYNC, 50); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 54: SD */ + /* instruction 51: SD */ compile_ret_t __sd(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 54); + vm_base::gen_sync(tu, PRE_SYNC, 51); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2117,15 +2012,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 54); + vm_base::gen_sync(tu, POST_SYNC, 51); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 55: SLLI */ + /* instruction 52: SLLI */ compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 55); + vm_base::gen_sync(tu, PRE_SYNC, 52); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,6>(instr))); @@ -2146,15 +2041,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 55); + vm_base::gen_sync(tu, POST_SYNC, 52); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 56: SRLI */ + /* instruction 53: SRLI */ compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 56); + vm_base::gen_sync(tu, PRE_SYNC, 53); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,6>(instr))); @@ -2175,15 +2070,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 56); + vm_base::gen_sync(tu, POST_SYNC, 53); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 57: SRAI */ + /* instruction 54: SRAI */ compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 57); + vm_base::gen_sync(tu, PRE_SYNC, 54); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,6>(instr))); @@ -2204,15 +2099,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 57); + vm_base::gen_sync(tu, POST_SYNC, 54); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 58: ADDIW */ + /* instruction 55: ADDIW */ compile_ret_t __addiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 58); + vm_base::gen_sync(tu, PRE_SYNC, 55); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -2242,15 +2137,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 58); + vm_base::gen_sync(tu, POST_SYNC, 55); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 59: SLLIW */ + /* instruction 56: SLLIW */ compile_ret_t __slliw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 59); + vm_base::gen_sync(tu, PRE_SYNC, 56); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2278,15 +2173,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 59); + vm_base::gen_sync(tu, POST_SYNC, 56); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 60: SRLIW */ + /* instruction 57: SRLIW */ compile_ret_t __srliw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 60); + vm_base::gen_sync(tu, PRE_SYNC, 57); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2314,15 +2209,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 60); + vm_base::gen_sync(tu, POST_SYNC, 57); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 61: SRAIW */ + /* instruction 58: SRAIW */ compile_ret_t __sraiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 61); + vm_base::gen_sync(tu, PRE_SYNC, 58); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2350,15 +2245,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 61); + vm_base::gen_sync(tu, POST_SYNC, 58); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 62: ADDW */ + /* instruction 59: ADDW */ compile_ret_t __addw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 62); + vm_base::gen_sync(tu, PRE_SYNC, 59); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2386,15 +2281,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 62); + vm_base::gen_sync(tu, POST_SYNC, 59); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 63: SUBW */ + /* instruction 60: SUBW */ compile_ret_t __subw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SUBW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 63); + vm_base::gen_sync(tu, PRE_SYNC, 60); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2422,15 +2317,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 63); + vm_base::gen_sync(tu, POST_SYNC, 60); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 64: SLLW */ + /* instruction 61: SLLW */ compile_ret_t __sllw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 64); + vm_base::gen_sync(tu, PRE_SYNC, 61); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2465,15 +2360,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 64); + vm_base::gen_sync(tu, POST_SYNC, 61); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 65: SRLW */ + /* instruction 62: SRLW */ compile_ret_t __srlw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 65); + vm_base::gen_sync(tu, PRE_SYNC, 62); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2508,15 +2403,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 65); + vm_base::gen_sync(tu, POST_SYNC, 62); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 66: SRAW */ + /* instruction 63: SRAW */ compile_ret_t __sraw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 66); + vm_base::gen_sync(tu, PRE_SYNC, 63); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2551,7 +2446,7 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 66); + vm_base::gen_sync(tu, POST_SYNC, 63); gen_trap_check(tu); return std::make_tuple(CONT); }