adds terminator to char str in wrap_puts

camera

.cproject

@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="cdt.managedbuild.toolchain.gnu.base.1610975709">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.toolchain.gnu.base.1610975709" moduleId="org.eclipse.cdt.core.settings" name="Default">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration buildProperties="" id="cdt.managedbuild.toolchain.gnu.base.1610975709" name="Default" optionalBuildProperties="" parent="org.eclipse.cdt.build.core.emptycfg">
+					<folderInfo id="cdt.managedbuild.toolchain.gnu.base.1610975709.1546824349" name="/" resourcePath="">
+						<toolChain id="cdt.managedbuild.toolchain.gnu.base.759422847" name="Linux GCC" superClass="cdt.managedbuild.toolchain.gnu.base">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="cdt.managedbuild.target.gnu.platform.base.1243356996" name="Debug Platform" osList="linux,hpux,aix,qnx" superClass="cdt.managedbuild.target.gnu.platform.base"/>
+							<builder id="cdt.managedbuild.target.gnu.builder.base.1892113927" managedBuildOn="false" name="Gnu Make Builder.Default" superClass="cdt.managedbuild.target.gnu.builder.base"/>
+							<tool id="cdt.managedbuild.tool.gnu.archiver.base.1296149061" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
+							<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.base.407512210" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.base">
+								<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1764780737" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+							</tool>
+							<tool id="cdt.managedbuild.tool.gnu.c.compiler.base.1062663578" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.base">
+								<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1828857752" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+							</tool>
+							<tool id="cdt.managedbuild.tool.gnu.c.linker.base.774157935" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.base"/>
+							<tool id="cdt.managedbuild.tool.gnu.cpp.linker.base.1756027799" name="GCC C++ Linker" superClass="cdt.managedbuild.tool.gnu.cpp.linker.base">
+								<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.103622118" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="cdt.managedbuild.tool.gnu.assembler.base.236534392" name="GCC Assembler" superClass="cdt.managedbuild.tool.gnu.assembler.base">
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1135961135" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="bm-bsp.null.406870477" name="bm-bsp"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+</cproject>

.gitignore

@@ -151,3 +151,4 @@ compile_commands.json
 CTestTestfile.cmake
 *.dump
 
+/doc/

.project

@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>bm-bsp</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>

CMakeLists.txt

@@ -0,0 +1,46 @@
+cmake_minimum_required(VERSION 3.21)
+include(CheckLinkerFlag)
+
+project(mnrs-bsp LANGUAGES ASM C)
+set(LINKER_SCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/env/${BOARD}/link.lds"
+    CACHE FILEPATH "Linker script to use for BSP linking")
+set(BSP_STARTUP "${CMAKE_CURRENT_SOURCE_DIR}/env/start.S"
+    CACHE FILEPATH "Path to the BSP startup assembly file")
+set(BSP_TRAP_HANDLER "${CMAKE_CURRENT_SOURCE_DIR}/env/entry.S"
+    CACHE FILEPATH "Assembly file implementing trap handler")
+if(NOT DEFINED BOARD)
+message(FATAL_ERROR "No Board selected")
+endif()
+add_compile_definitions("BOARD_${BOARD}")
+
+set(TESTBENCHES "rtl" "TGCP")
+list(FIND TESTBENCHES ${BOARD} _index)
+if(NOT _index EQUAL -1)
+    set(BOARD "testbench/${BOARD}")
+endif()
+
+option(SEMIHOSTING "Enable semihosting support" OFF)
+if(SEMIHOSTING)
+    add_compile_definitions(SEMIHOSTING)
+endif()
+
+add_library(startup STATIC ${BSP_STARTUP} ${BSP_TRAP_HANDLER})
+target_include_directories(startup PUBLIC env include)
+
+add_subdirectory(libwrap)
+
+add_library(bsp STATIC env/${BOARD}/init.c)
+target_link_libraries(bsp PUBLIC startup wrap)
+target_include_directories(bsp PUBLIC env/${BOARD})
+
+check_linker_flag(C "LINKER:--no-warn-rwx-segments" HAS_NO_WARN_RWX_SEGMENTS)
+
+if(HAS_NO_WARN_RWX_SEGMENTS)
+    target_link_options(bsp INTERFACE LINKER:--no-warn-rwx-segments)
+endif()
+target_link_options(bsp INTERFACE LINKER: -nostartfiles -T ${LINKER_SCRIPT})
+
+if(SEMIHOSTING)
+    target_include_directories(bsp INTERFACE include)
+    target_sources(bsp INTERFACE env/semihosting.c env/trap.c)
+endif()

cmake/rv32imc.cmake

@@ -0,0 +1,59 @@
+# Look for GCC in path
+# https://xpack.github.io/riscv-none-embed-gcc/
+FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXE "riscv-none-embed-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv-none-embed-gcc" PATHS ENV INCLUDE)
+# New versions of xpack
+FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER_EXE "riscv-none-elf-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER "riscv-none-elf-gcc" PATHS ENV INCLUDE)
+# Look for RISC-V github GCC
+# https://github.com/riscv/riscv-gnu-toolchain
+FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXT "riscv64-unknown-elf-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv64-unknown-elf-gcc" PATHS ENV INCLUDE)
+
+# Select which is found
+if (EXISTS ${RISCV_XPACK_NEW_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER})
+elseif (EXISTS ${RISCV_XPACK_GCC_NEW_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER_EXE})
+elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER})
+elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER_EXE})
+elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER})
+elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER_EXE})
+else()
+message(FATAL_ERROR "RISC-V GCC not found. ${RISCV_GITHUB_GCC_COMPILER} ${RISCV_XPACK_GCC_COMPILER} ${RISCV_GITHUB_GCC_COMPILER_EXE} ${RISCV_XPACK_GCC_COMPILER_EXE}")
+endif()
+
+get_filename_component(RISCV_TOOLCHAIN_BIN_PATH ${RISCV_GCC_COMPILER} DIRECTORY)
+get_filename_component(RISCV_TOOLCHAIN_BIN_GCC ${RISCV_GCC_COMPILER} NAME_WE)
+get_filename_component(RISCV_TOOLCHAIN_BIN_EXT ${RISCV_GCC_COMPILER} EXT)
+
+STRING(REGEX REPLACE "\-gcc" "-" CROSS_COMPILE ${RISCV_TOOLCHAIN_BIN_GCC})
+
+# The Generic system name is used for embedded targets (targets without OS)
+set(CMAKE_SYSTEM_NAME Generic )
+set(CMAKE_EXECUTABLE_SUFFIX_C ".elf")
+set(RISCV_ARCH rv32imc_zicsr_zifencei )
+set(RISCV_ABI ilp32)
+
+
+set(CMAKE_ASM_COMPILER {CROSS_COMPILE}gcc )
+set(CMAKE_AR ${CROSS_COMPILE}ar)
+set(CMAKE_ASM_COMPILER ${CROSS_COMPILE}gcc)
+set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
+set(CMAKE_CXX_COMPILER ${CROSS_COMPILE}g++)
+
+set( CMAKE_OBJCOPY      ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objcopy
+     CACHE FILEPATH "The toolchain objcopy command " FORCE )
+
+set( CMAKE_OBJDUMP      ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objdump
+     CACHE FILEPATH "The toolchain objdump command " FORCE )
+
+set( CMAKE_C_FLAGS "-march=${RISCV_ARCH} -mabi=${RISCV_ABI} -mcmodel=medany" )
+
+set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
+set( CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
+set( CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )

cmake/rv64gc.cmake

@@ -0,0 +1,59 @@
+# Look for GCC in path
+# https://xpack.github.io/riscv-none-embed-gcc/
+FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXE "riscv-none-embed-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv-none-embed-gcc" PATHS ENV INCLUDE)
+# New versions of xpack
+FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER_EXE "riscv-none-elf-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_NEW_GCC_COMPILER "riscv-none-elf-gcc" PATHS ENV INCLUDE)
+# Look for RISC-V github GCC
+# https://github.com/riscv/riscv-gnu-toolchain
+FIND_FILE( RISCV_XPACK_GCC_COMPILER_EXT "riscv64-unknown-elf-gcc.exe" PATHS ENV INCLUDE)
+FIND_FILE( RISCV_XPACK_GCC_COMPILER "riscv64-unknown-elf-gcc" PATHS ENV INCLUDE)
+
+# Select which is found
+if (EXISTS ${RISCV_XPACK_NEW_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER})
+elseif (EXISTS ${RISCV_XPACK_GCC_NEW_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_NEW_GCC_COMPILER_EXE})
+elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER})
+elseif (EXISTS ${RISCV_XPACK_GCC_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_XPACK_GCC_COMPILER_EXE})
+elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER})
+set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER})
+elseif (EXISTS ${RISCV_GITHUB_GCC_COMPILER_EXE})
+set( RISCV_GCC_COMPILER ${RISCV_GITHUB_GCC_COMPILER_EXE})
+else()
+message(FATAL_ERROR "RISC-V GCC not found. ${RISCV_GITHUB_GCC_COMPILER} ${RISCV_XPACK_GCC_COMPILER} ${RISCV_GITHUB_GCC_COMPILER_EXE} ${RISCV_XPACK_GCC_COMPILER_EXE}")
+endif()
+
+get_filename_component(RISCV_TOOLCHAIN_BIN_PATH ${RISCV_GCC_COMPILER} DIRECTORY)
+get_filename_component(RISCV_TOOLCHAIN_BIN_GCC ${RISCV_GCC_COMPILER} NAME_WE)
+get_filename_component(RISCV_TOOLCHAIN_BIN_EXT ${RISCV_GCC_COMPILER} EXT)
+
+STRING(REGEX REPLACE "\-gcc" "-" CROSS_COMPILE ${RISCV_TOOLCHAIN_BIN_GCC})
+
+# The Generic system name is used for embedded targets (targets without OS)
+set(CMAKE_SYSTEM_NAME Generic )
+set(CMAKE_EXECUTABLE_SUFFIX_C ".elf")
+set(RISCV_ARCH rv64gc )
+set(RISCV_ABI lp64d)
+
+
+set(CMAKE_ASM_COMPILER {CROSS_COMPILE}gcc )
+set(CMAKE_AR ${CROSS_COMPILE}ar)
+set(CMAKE_ASM_COMPILER ${CROSS_COMPILE}gcc)
+set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
+set(CMAKE_CXX_COMPILER ${CROSS_COMPILE}g++)
+
+set( CMAKE_OBJCOPY      ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objcopy
+     CACHE FILEPATH "The toolchain objcopy command " FORCE )
+
+set( CMAKE_OBJDUMP      ${RISCV_TOOLCHAIN_BIN_PATH}/${CROSS_COMPILE}objdump
+     CACHE FILEPATH "The toolchain objdump command " FORCE )
+
+set( CMAKE_C_FLAGS "-march=${RISCV_ARCH} -mabi=${RISCV_ABI} -mcmodel=medany" )
+
+set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
+set( CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )
+set( CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS}" CACHE STRING "" )

drivers/fe300prci/fe300prci_driver.c

@@ -1,252 +0,0 @@
-// See LICENSE file for license details
-
-#include "platform.h"
-
-#ifdef PRCI_CTRL_ADDR
-#include "fe300prci/fe300prci_driver.h"
-#include <unistd.h>
-
-#define rdmcycle(x)  {				       \
-    uint32_t lo, hi, hi2;			       \
-    __asm__ __volatile__ ("1:\n\t"		       \
-			  "csrr %0, mcycleh\n\t"       \
-			  "csrr %1, mcycle\n\t"	       \
-			  "csrr %2, mcycleh\n\t"		\
-			  "bne  %0, %2, 1b\n\t"			\
-			  : "=r" (hi), "=r" (lo), "=r" (hi2)) ;	\
-    *(x) = lo | ((uint64_t) hi << 32); 				\
-  }
-
-uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq)
-{
-
-  uint32_t start_mtime = CLINT_REG(CLINT_MTIME);
-  uint32_t end_mtime = start_mtime + mtime_ticks + 1;
-
-  // Make sure we won't get rollover.
-  while (end_mtime < start_mtime){
-    start_mtime = CLINT_REG(CLINT_MTIME);
-    end_mtime = start_mtime + mtime_ticks + 1;
-  }
-
-  // Don't start measuring until mtime edge.
-  uint32_t tmp = start_mtime;
-  do {
-    start_mtime = CLINT_REG(CLINT_MTIME);
-  } while (start_mtime == tmp);
-  
-  uint64_t start_mcycle;
-  rdmcycle(&start_mcycle);
-  
-  while (CLINT_REG(CLINT_MTIME) < end_mtime) ;
-  
-  uint64_t end_mcycle;
-  rdmcycle(&end_mcycle);
-  uint32_t difference = (uint32_t) (end_mcycle - start_mcycle);
-
-  uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks;
-  return (uint32_t) freq & 0xFFFFFFFF;
-  
-}
- 
-
-void PRCI_use_hfrosc(int div, int trim)
-{
-  // Make sure the HFROSC is running at its default setting
-  // It is OK to change this even if we are running off of it.
-  
-  PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
-
-  while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
-  
-  PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
-}
-
-void PRCI_use_pll(int refsel, int bypass,
-			 int r, int f, int q, int finaldiv,
-			 int hfroscdiv, int hfrosctrim)
-{
-  // Ensure that we aren't running off the PLL before we mess with it.
-  if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
-    // Make sure the HFROSC is running at its default setting
-    PRCI_use_hfrosc(4, 16);
-  }
-  
-  // Set PLL Source to be HFXOSC if desired.
-  uint32_t config_value = 0;
-
-  config_value |= PLL_REFSEL(refsel);
-  
-  if (bypass) {
-    // Bypass
-    config_value |= PLL_BYPASS(1);
-
-    PRCI_REG(PRCI_PLLCFG) = config_value;
-
-    // If we don't have an HFXTAL, this doesn't really matter.
-    // Set our Final output divide to divide-by-1:
-    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
-  } else {
-  
-    // To overclock, use the hfrosc
-    if (hfrosctrim >= 0 && hfroscdiv >= 0) {
-      PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
-    }
-    
-    // Set DIV Settings for PLL
-    
-    // (Legal values of f_REF are 6-48MHz)
-
-    // Set DIVR to divide-by-2 to get 8MHz frequency
-    // (legal values of f_R are 6-12 MHz)
-
-    config_value |= PLL_BYPASS(1);
-    config_value |= PLL_R(r);
-
-    // Set DIVF to get 512Mhz frequncy
-    // There is an implied multiply-by-2, 16Mhz.
-    // So need to write 32-1
-    // (legal values of f_F are 384-768 MHz)
-    config_value |= PLL_F(f);
-
-    // Set DIVQ to divide-by-2 to get 256 MHz frequency
-    // (legal values of f_Q are 50-400Mhz)
-    config_value |= PLL_Q(q);
-
-    // Set our Final output divide to divide-by-1:
-    if (finaldiv == 1){
-      PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
-    } else {
-      PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1));
-    }
-
-    PRCI_REG(PRCI_PLLCFG) = config_value;
-
-    // Un-Bypass the PLL.
-    PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
-
-    // Wait for PLL Lock
-    // Note that the Lock signal can be glitchy.
-    // Need to wait 100 us
-    // RTC is running at 32kHz.
-    // So wait 4 ticks of RTC.
-    uint32_t now = CLINT_REG(CLINT_MTIME);
-    while (CLINT_REG(CLINT_MTIME) - now < 4) ;
-    
-    // Now it is safe to check for PLL Lock
-    while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
-
-  }
-
-  // Switch over to PLL Clock source
-  PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
-
-  // If we're running off HFXOSC, turn off the HFROSC to
-  // save power.
-  if (refsel) {
-    PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
-  }
-  
-}
-
-void PRCI_use_default_clocks()
-{
-  // Turn off the LFROSC
-  AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
-
-  // Use HFROSC
-  PRCI_use_hfrosc(4, 16);
-}
-
-void PRCI_use_hfxosc(uint32_t finaldiv)
-{
-  
-  PRCI_use_pll(1, // Use HFXTAL
-	       1, // Bypass = 1
-	       0, // PLL settings don't matter
-	       0, // PLL settings don't matter
-	       0, // PLL settings don't matter
-	       finaldiv,
-	       -1,
-	       -1);
-}
-
-// This is a generic function, which
-// doesn't span the entire range of HFROSC settings.
-// It only adjusts the trim, which can span a hundred MHz or so.
-// This function does not check the legality of the PLL settings
-// at all, and it is quite possible to configure invalid PLL settings
-// this way.
-// It returns the actual measured CPU frequency.
-
-uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target )
-{
-
-  uint32_t hfrosctrim = 0;
-  uint32_t hfroscdiv = 4;
-  uint32_t prev_trim = 0;
-
-  // In this function we use PLL settings which
-  // will give us a 32x multiplier from the output
-  // of the HFROSC source to the output of the
-  // PLL. We first measure our HFROSC to get the
-  // right trim, then finally use it as the PLL source.
-  // We should really check here that the f_cpu
-  // requested is something in the limit of the PLL. For
-  // now that is up to the user.
-
-  // This will undershoot for frequencies not divisible by 16.
-  uint32_t desired_hfrosc_freq = (f_cpu/ 16);
-
-  PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
-  
-  // Ignore the first run (for icache reasons)
-  uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
-
-  cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
-  uint32_t prev_freq = cpu_freq;
-  
-  while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){
-    prev_trim = hfrosctrim;
-    prev_freq = cpu_freq;
-    hfrosctrim ++;
-    PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
-    cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
-  } 
-
-  // We couldn't go low enough
-  if (prev_freq > desired_hfrosc_freq){
-    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
-    cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
-    return cpu_freq;
-  }
-  
-  // We couldn't go high enough
-  if (cpu_freq < desired_hfrosc_freq){
-    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
-    cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
-    return cpu_freq;
-  }
-
-  // Check for over/undershoot
-  switch(target) {
-  case(PRCI_FREQ_CLOSEST):
-    if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) {
-      PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
-    } else {
-      PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
-    }
-    break;
-  case(PRCI_FREQ_UNDERSHOOT):
-    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
-    break;
-  default:
-    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
-  }
-
-  cpu_freq =  PRCI_measure_mcycle_freq(1000, RTC_FREQ);
-  return cpu_freq;
-
-}
-
-#endif

drivers/fe300prci/fe300prci_driver.h

@@ -1,79 +0,0 @@
-// See LICENSE file for license details
-
-#ifndef _FE300PRCI_DRIVER_H_
-#define _FE300PRCI_DRIVER_H_
-
-__BEGIN_DECLS
-
-#include <unistd.h>
-
-typedef enum prci_freq_target {
-  
-  PRCI_FREQ_OVERSHOOT,
-  PRCI_FREQ_CLOSEST,
-  PRCI_FREQ_UNDERSHOOT
-
-} PRCI_freq_target;
-
-/* Measure and return the approximate frequency of the 
- * CPU, as given by measuring the mcycle counter against 
- * the mtime ticks.
- */
-uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq);
-
-/* Safely switch over to the HFROSC using the given div
- * and trim settings.
- */
-void PRCI_use_hfrosc(int div, int trim);
-
-/* Safely switch over to the 16MHz HFXOSC,
- * applying the finaldiv clock divider (1 is the lowest
- * legal value).
- */
-void PRCI_use_hfxosc(uint32_t finaldiv);
-
-/* Safely switch over to the PLL using the given
- * settings.
- * 
- * Note that not all combinations of the inputs are actually
- * legal, and this function does not check for their
- * legality ("safely" means that this function won't turn off
- * or glitch the clock the CPU is actually running off, but
- * doesn't protect against you making it too fast or slow.)
- */
-
-void PRCI_use_pll(int refsel, int bypass,
-			 int r, int f, int q, int finaldiv,
-			 int hfroscdiv, int hfrosctrim);
-
-/* Use the default clocks configured at reset.
- * This is ~16Mhz HFROSC and turns off the LFROSC
- * (on the current FE310 Dev Platforms, an external LFROSC is 
- * used as it is more power efficient).
- */
-void PRCI_use_default_clocks();
-
-/* This routine will adjust the HFROSC trim
- * while using HFROSC as the clock source, 
- * measure the resulting frequency, then
- * use it as the PLL clock source, 
- * in an attempt to get over, under, or close to the 
- * requested frequency. It returns the actual measured 
- * frequency. 
- *
- * Note that the requested frequency must be within the 
- * range supported by the PLL so not all values are 
- * achievable with this function, and not all 
- * are guaranteed to actually work. The PLL
- * is rated higher than the hardware.
- * 
- * There is no check on the desired f_cpu frequency, it
- * is up to the user to specify something reasonable.
- */
-
-uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target);
-
-__END_DECLS
-
-#endif
-  

env/abi_eabi.txt

@@ -0,0 +1,52 @@
+            EABI Name  Description                      Saver
+    x0        zero     Hard-wired zero value            -
+    x1        ra       Return address                   Caller
+    x2        sp       Stack pointer                    Callee
+    x3        gp       Global pointer                   -
+    x4        tp       Thread pointer                   -
+    x5        t0       Temporary/link register          Caller
+    x6        s3       Saved register                   Callee
+    x7        s4       Saved register                   Callee
+    x8        s0/fp    Saved register/frame pointer     Callee
+    x9        s1       Saved register                   Callee
+    x10       a0       Argument/return value            Caller
+    x11       a1       Argument/return value            Caller
+    x12       a2       Argument                         Caller
+    x13       a3       Argument                         Caller
+    x14       s2       Saved register                   Callee
+    x15       t1       Temporary                        Caller
+    x16-x31   s5-s20   Saved registers                  Callee
+    
+	reg 	ABI 	Use by convention 					Preserved?
+	x0 	    zero 	hardwired to 0, ignores writes 		n/a
+	x1 	    ra 		return address for jumps 			no
+	x2 	    sp 		stack pointer 						yes
+	x3 	    gp 		global pointer 						n/a
+	x4 	    tp 		thread pointer 						n/a
+	x5 	    t0 		temporary register 0 				no
+	x6 	    t1 		temporary register 1 				no
+	x7 	    t2 		temporary register 2 				no
+	x8 	    s0/fp 	saved register 0 or frame pointer 	yes
+	x9 	    s1 		saved register 1 					yes
+	x10 	a0 		argument/return value 0 			no
+	x11 	a1 		argument/return value 1 			no
+	x12 	a2 		argument 2 							no
+	x13 	a3 		argument 3 							no
+	x14 	a4 		argument 4 							no
+	x15 	a5 		argument 5 							no
+	x16 	a6 		argument 6 							no
+	x17 	a7 		argument 7 							no
+	x18 	s2 		saved register 2 					yes
+	x19 	s3 		saved register 3 					yes
+	x20 	s4 		saved register 4 					yes
+	x21 	s5 		saved register 5 					yes
+	x22 	s6 		saved register 6 					yes
+	x23 	s7 		saved register 7 					yes
+	x24 	s8 		saved register 8 					yes
+	x25 	s9 		saved register 9 					yes
+	x26 	s10 	saved register 10 					yes
+	x27 	s11 	saved register 11 					yes
+	x28 	t3 		temporary register 3 				no
+	x29 	t4 		temporary register 4 				no
+	x30 	t5 		temporary register 5 				no
+	x31 	t6 		temporary register 6 				no

env/common-clang.mk

@@ -63,10 +63,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
 
 .PHONY: clean
 clean:
-	rm -f $(TARGET) $(LINK_OBJS)
+	rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf *.o
-
-.PHONY: clean-all
-clean-all:
-	rm -f $(CLEAN_OBJS) $(LIBWRAP)
 
 endif

env/common-gcc.mk

@@ -1,32 +1,42 @@
 ifndef _MK_COMMON
 _MK_COMMON := # defined
 
-.PHONY: all
+TL_TARGET?=all
-all: $(TARGET)
+
+.PHONY: $(TL_TARGET)
+$(TL_TARGET): $(TARGET).elf
+
+ENV_DIR:=$(dir $(lastword $(MAKEFILE_LIST)))
+BSP_BASE=$(ENV_DIR)/..
+PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
 
 include $(BSP_BASE)/libwrap/libwrap.mk
 
 BOARD?=iss
-ENV_DIR = $(BSP_BASE)/env
-PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
 
-ASM_SRCS += $(ENV_DIR)/start.S
+ASM_SRCS += $(ENV_DIR)/start.S $(ENV_DIR)/entry.S
-ASM_SRCS += $(ENV_DIR)/entry.S
 C_SRCS   += $(PLATFORM_DIR)/init.c
+C_SRCS   += $(PLATFORM_DIR)/bsp_write.c $(PLATFORM_DIR)/bsp_read.c
 
-LINKER_SCRIPT := $(PLATFORM_DIR)/$(LINK_TARGET).lds
+
+LINKER_SCRIPT ?= $(PLATFORM_DIR)/$(LINK_TARGET).lds
 
 INCLUDES += -I$(BSP_BASE)/include
 INCLUDES += -I$(BSP_BASE)/drivers/
 INCLUDES += -I$(ENV_DIR)
 INCLUDES += -I$(PLATFORM_DIR)
-
+INCLUDES += -I$(BSP_BASE)/libwrap/sys/
-TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin/
 
 LDFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
-LDFLAGS += -T $(LINKER_SCRIPT) -Wl,--no-warn-rwx-segments -Wl,-Map=$(TARGET).map  -nostartfiles 
+LDFLAGS += -L$(ENV_DIR) -L$(PLATFORM_DIR)
-LDFLAGS += -L$(ENV_DIR)
+LD_SCRIPT += -T $(LINKER_SCRIPT) -Wl,--no-warn-rwx-segments -Wl,-Map=$(TARGET).map  -nostartfiles 
-# --specs=nano.specs
+
+ifneq (,$(findstring specs=nano.specs,$(LDFLAGS), LD_SCRIPT))
+    # Found
+else
+    # Not found
+endif
+
 
 ASM_OBJS := $(ASM_SRCS:.S=.o)
 C_OBJS   := $(C_SRCS:.c=.o)
@@ -53,11 +63,13 @@ CC=$(TOOL_DIR)$(TRIPLET)-gcc
 LD=$(TOOL_DIR)$(TRIPLET)-gcc
 AR=$(TOOL_DIR)$(TRIPLET)-ar
 OBJDUMP := $(TOOL_DIR)$(TRIPLET)-objdump
+OBJCOPY := $(TOOL_DIR)$(TRIPLET)-objcopy
 
-
+ifndef NO_DEFAULT_LINK
-$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
+$(TARGET).elf: $(LINK_OBJS) $(LINK_DEPS)
-	$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP) -o $@
+	$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP_LDFLAGS) $(LIBWRAP) $(LD_SCRIPT) -o $@
-	$(OBJDUMP) -d -S $(TARGET) > $(TARGET).dis
+	$(OBJDUMP) -d -S $@ > $(TARGET).dis
+endif
 
 $(ASM_OBJS): %.o: %.S $(HEADERS)
 	$(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
@@ -70,6 +82,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
 
 .PHONY: clean
 clean:
-	rm -f $(CLEAN_OBJS) $(LIBWRAP)
+	rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf *.o
 
 endif

env/entry.S

@@ -4,7 +4,7 @@
 #define ENTRY_S
 
 #include "encoding.h"
-#include "rtl/bits.h"
+#include "bits.h"
 
   .section      .text.entry	
   .align 2
@@ -12,38 +12,38 @@
 trap_entry:
   addi sp, sp, -32*REGBYTES
 
-  STORE x1, 1*REGBYTES(sp)
+  sw  x1,  1*REGBYTES(sp)
-  STORE x2, 2*REGBYTES(sp)
+  sw  x2,  2*REGBYTES(sp)
-  STORE x3, 3*REGBYTES(sp)
+  sw  x3,  3*REGBYTES(sp)
-  STORE x4, 4*REGBYTES(sp)
+  sw  x4,  4*REGBYTES(sp)
-  STORE x5, 5*REGBYTES(sp)
+  sw  x5,  5*REGBYTES(sp)
-  STORE x6, 6*REGBYTES(sp)
+  sw  x6,  6*REGBYTES(sp)
-  STORE x7, 7*REGBYTES(sp)
+  sw  x7,  7*REGBYTES(sp)
-  STORE x8, 8*REGBYTES(sp)
+  sw  x8,  8*REGBYTES(sp)
-  STORE x9, 9*REGBYTES(sp)
+  sw  x9,  9*REGBYTES(sp)
-  STORE x10, 10*REGBYTES(sp)
+  sw x10, 10*REGBYTES(sp)
-  STORE x11, 11*REGBYTES(sp)
+  sw x11, 11*REGBYTES(sp)
-  STORE x12, 12*REGBYTES(sp)
+  sw x12, 12*REGBYTES(sp)
-  STORE x13, 13*REGBYTES(sp)
+  sw x13, 13*REGBYTES(sp)
-  STORE x14, 14*REGBYTES(sp)
+  sw x14, 14*REGBYTES(sp)
-  STORE x15, 15*REGBYTES(sp)
+  sw x15, 15*REGBYTES(sp)
 #ifndef __riscv_abi_rve
-  STORE x16, 16*REGBYTES(sp)
+  sw x16, 16*REGBYTES(sp)
-  STORE x17, 17*REGBYTES(sp)
+  sw x17, 17*REGBYTES(sp)
-  STORE x18, 18*REGBYTES(sp)
+  sw x18, 18*REGBYTES(sp)
-  STORE x19, 19*REGBYTES(sp)
+  sw x19, 19*REGBYTES(sp)
-  STORE x20, 20*REGBYTES(sp)
+  sw x20, 20*REGBYTES(sp)
-  STORE x21, 21*REGBYTES(sp)
+  sw x21, 21*REGBYTES(sp)
-  STORE x22, 22*REGBYTES(sp)
+  sw x22, 22*REGBYTES(sp)
-  STORE x23, 23*REGBYTES(sp)
+  sw x23, 23*REGBYTES(sp)
-  STORE x24, 24*REGBYTES(sp)
+  sw x24, 24*REGBYTES(sp)
-  STORE x25, 25*REGBYTES(sp)
+  sw x25, 25*REGBYTES(sp)
-  STORE x26, 26*REGBYTES(sp)
+  sw x26, 26*REGBYTES(sp)
-  STORE x27, 27*REGBYTES(sp)
+  sw x27, 27*REGBYTES(sp)
-  STORE x28, 28*REGBYTES(sp)
+  sw x28, 28*REGBYTES(sp)
-  STORE x29, 29*REGBYTES(sp)
+  sw x29, 29*REGBYTES(sp)
-  STORE x30, 30*REGBYTES(sp)
+  sw x30, 30*REGBYTES(sp)
-  STORE x31, 31*REGBYTES(sp)
+  sw x31, 31*REGBYTES(sp)
 #endif
   csrr a0, mcause
   csrr a1, mepc
@@ -51,44 +51,40 @@ trap_entry:
   call handle_trap
   csrw mepc, a0
 
-  # Remain in M-mode after mret
-  li t0, MSTATUS_MPP
-  csrs mstatus, t0
 
-  LOAD x1, 1*REGBYTES(sp)
+  lw  x1,  1*REGBYTES(sp)
-  LOAD x2, 2*REGBYTES(sp)
+  lw  x2,  2*REGBYTES(sp)
-  LOAD x3, 3*REGBYTES(sp)
+  lw  x3,  3*REGBYTES(sp)
-  LOAD x4, 4*REGBYTES(sp)
+  lw  x4,  4*REGBYTES(sp)
-  LOAD x5, 5*REGBYTES(sp)
+  lw  x5,  5*REGBYTES(sp)
-  LOAD x6, 6*REGBYTES(sp)
+  lw  x6,  6*REGBYTES(sp)
-  LOAD x7, 7*REGBYTES(sp)
+  lw  x7,  7*REGBYTES(sp)
-  LOAD x8, 8*REGBYTES(sp)
+  lw  x8,  8*REGBYTES(sp)
-  LOAD x9, 9*REGBYTES(sp)
+  lw  x9,  9*REGBYTES(sp)
-  LOAD x10, 10*REGBYTES(sp)
+  lw x10, 10*REGBYTES(sp)
-  LOAD x11, 11*REGBYTES(sp)
+  lw x11, 11*REGBYTES(sp)
-  LOAD x12, 12*REGBYTES(sp)
+  lw x12, 12*REGBYTES(sp)
-  LOAD x13, 13*REGBYTES(sp)
+  lw x13, 13*REGBYTES(sp)
-  LOAD x14, 14*REGBYTES(sp)
+  lw x14, 14*REGBYTES(sp)
-  LOAD x15, 15*REGBYTES(sp)
+  lw x15, 15*REGBYTES(sp)
 #ifndef __riscv_abi_rve
-  LOAD x16, 16*REGBYTES(sp)
+  lw x16, 16*REGBYTES(sp)
-  LOAD x17, 17*REGBYTES(sp)
+  lw x17, 17*REGBYTES(sp)
-  LOAD x18, 18*REGBYTES(sp)
+  lw x18, 18*REGBYTES(sp)
-  LOAD x19, 19*REGBYTES(sp)
+  lw x19, 19*REGBYTES(sp)
-  LOAD x20, 20*REGBYTES(sp)
+  lw x20, 20*REGBYTES(sp)
-  LOAD x21, 21*REGBYTES(sp)
+  lw x21, 21*REGBYTES(sp)
-  LOAD x22, 22*REGBYTES(sp)
+  lw x22, 22*REGBYTES(sp)
-  LOAD x23, 23*REGBYTES(sp)
+  lw x23, 23*REGBYTES(sp)
-  LOAD x24, 24*REGBYTES(sp)
+  lw x24, 24*REGBYTES(sp)
-  LOAD x25, 25*REGBYTES(sp)
+  lw x25, 25*REGBYTES(sp)
-  LOAD x26, 26*REGBYTES(sp)
+  lw x26, 26*REGBYTES(sp)
-  LOAD x27, 27*REGBYTES(sp)
+  lw x27, 27*REGBYTES(sp)
-  LOAD x28, 28*REGBYTES(sp)
+  lw x28, 28*REGBYTES(sp)
-  LOAD x29, 29*REGBYTES(sp)
+  lw x29, 29*REGBYTES(sp)
-  LOAD x30, 30*REGBYTES(sp)
+  lw x30, 30*REGBYTES(sp)
-  LOAD x31, 31*REGBYTES(sp)
+  lw x31, 31*REGBYTES(sp)
 #endif
-  addi sp, sp, 32*REGBYTES
   mret
 
 .weak handle_trap

env/hifive1.h

@@ -1,81 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_HIFIVE1_H
-#define _SIFIVE_HIFIVE1_H
-
-#include <stdint.h>
-
-/****************************************************************************
- * GPIO Connections
- *****************************************************************************/
-
-// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
-// These are also mapped to RGB LEDs on the Freedom E300 Arty
-// FPGA
-// Dev Kit.
-
-#define RED_LED_OFFSET   22
-#define GREEN_LED_OFFSET 19
-#define BLUE_LED_OFFSET  21
-
-// These are the GPIO bit offsets for the differen digital pins
-// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
-#define PIN_0_OFFSET 16
-#define PIN_1_OFFSET 17
-#define PIN_2_OFFSET 18
-#define PIN_3_OFFSET 19
-#define PIN_4_OFFSET 20
-#define PIN_5_OFFSET 21
-#define PIN_6_OFFSET 22
-#define PIN_7_OFFSET 23
-#define PIN_8_OFFSET 0
-#define PIN_9_OFFSET 1
-#define PIN_10_OFFSET 2
-#define PIN_11_OFFSET 3
-#define PIN_12_OFFSET 4
-#define PIN_13_OFFSET 5
-//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
-#define PIN_15_OFFSET 9
-#define PIN_16_OFFSET 10
-#define PIN_17_OFFSET 11
-#define PIN_18_OFFSET 12
-#define PIN_19_OFFSET 13
-
-// These are *PIN* numbers, not
-// GPIO Offset Numbers.
-#define PIN_SPI1_SCK    (13u)
-#define PIN_SPI1_MISO   (12u)
-#define PIN_SPI1_MOSI   (11u)
-#define PIN_SPI1_SS0    (10u)
-#define PIN_SPI1_SS1    (14u) 
-#define PIN_SPI1_SS2    (15u)
-#define PIN_SPI1_SS3    (16u)
-
-#define SS_PIN_TO_CS_ID(x) \
-  ((x==PIN_SPI1_SS0 ? 0 :		 \
-    (x==PIN_SPI1_SS1 ? 1 :		 \
-     (x==PIN_SPI1_SS2 ? 2 :		 \
-      (x==PIN_SPI1_SS3 ? 3 :		 \
-       -1))))) 
-
-
-// These buttons are present only on the Freedom E300 Arty Dev Kit.
-#ifdef HAS_BOARD_BUTTONS
-#define BUTTON_0_OFFSET 15
-#define BUTTON_1_OFFSET 30
-#define BUTTON_2_OFFSET 31
-
-#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
-#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
-#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
-
-#endif
-
-#define HAS_HFXOSC 1
-#define HAS_LFROSC_BYPASS 1
-
-#define RTC_FREQ 32768
-
-void write_hex(int fd, unsigned long int hex);
-
-#endif /* _SIFIVE_HIFIVE1_H */

env/hifive1/init.c

@@ -1,238 +0,0 @@
-#include <stdint.h>
-#include <stdio.h>
-#include <unistd.h>
-
-#include "../hifive1/platform.h"
-#include "encoding.h"
-
-extern int main(int argc, char** argv);
-extern void trap_entry();
-
-static unsigned long mtime_lo(void)
-{
-  return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
-}
-
-#ifdef __riscv32
-
-static uint32_t mtime_hi(void)
-{
-  return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
-}
-
-uint64_t get_timer_value()
-{
-  while (1) {
-    uint32_t hi = mtime_hi();
-    uint32_t lo = mtime_lo();
-    if (hi == mtime_hi())
-      return ((uint64_t)hi << 32) | lo;
-  }
-}
-
-#else /* __riscv32 */
-
-uint64_t get_timer_value()
-{
-  return mtime_lo();
-}
-
-#endif
-
-unsigned long get_timer_freq()
-{
-  return 32768;
-}
-
-static void use_hfrosc(int div, int trim)
-{
-  // Make sure the HFROSC is running at its default setting
-  PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
-  while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
-  PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
-}
-
-static void use_pll(int refsel, int bypass, int r, int f, int q)
-{
-  // Ensure that we aren't running off the PLL before we mess with it.
-  if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
-    // Make sure the HFROSC is running at its default setting
-    use_hfrosc(4, 16);
-  }
-
-  // Set PLL Source to be HFXOSC if available.
-  uint32_t config_value = 0;
-
-  config_value |= PLL_REFSEL(refsel);
-
-  if (bypass) {
-    // Bypass
-    config_value |= PLL_BYPASS(1);
-
-    PRCI_REG(PRCI_PLLCFG) = config_value;
-
-    // If we don't have an HFXTAL, this doesn't really matter.
-    // Set our Final output divide to divide-by-1:
-    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
-  } else {
-    // In case we are executing from QSPI,
-    // (which is quite likely) we need to
-    // set the QSPI clock divider appropriately
-    // before boosting the clock frequency.
-
-    // Div = f_sck/2
-    SPI0_REG(SPI_REG_SCKDIV) = 8;
-
-    // Set DIV Settings for PLL
-    // Both HFROSC and HFXOSC are modeled as ideal
-    // 16MHz sources (assuming dividers are set properly for
-    // HFROSC).
-    // (Legal values of f_REF are 6-48MHz)
-
-    // Set DIVR to divide-by-2 to get 8MHz frequency
-    // (legal values of f_R are 6-12 MHz)
-
-    config_value |= PLL_BYPASS(1);
-    config_value |= PLL_R(r);
-
-    // Set DIVF to get 512Mhz frequncy
-    // There is an implied multiply-by-2, 16Mhz.
-    // So need to write 32-1
-    // (legal values of f_F are 384-768 MHz)
-    config_value |= PLL_F(f);
-
-    // Set DIVQ to divide-by-2 to get 256 MHz frequency
-    // (legal values of f_Q are 50-400Mhz)
-    config_value |= PLL_Q(q);
-
-    // Set our Final output divide to divide-by-1:
-    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
-
-    PRCI_REG(PRCI_PLLCFG) = config_value;
-
-    // Un-Bypass the PLL.
-    PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
-
-    // Wait for PLL Lock
-    // Note that the Lock signal can be glitchy.
-    // Need to wait 100 us
-    // RTC is running at 32kHz.
-    // So wait 4 ticks of RTC.
-    uint32_t now = mtime_lo();
-    while (mtime_lo() - now < 4) ;
-
-    // Now it is safe to check for PLL Lock
-    while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
-  }
-
-  // Switch over to PLL Clock source
-  PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
-}
-
-static void use_default_clocks()
-{
-  // Turn off the LFROSC
-  AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
-
-  // Use HFROSC
-  use_hfrosc(4, 16);
-}
-
-static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
-{
-  unsigned long start_mtime, delta_mtime;
-  unsigned long mtime_freq = get_timer_freq();
-
-  // Don't start measuruing until we see an mtime tick
-  unsigned long tmp = mtime_lo();
-  do {
-    start_mtime = mtime_lo();
-  } while (start_mtime == tmp);
-
-  unsigned long start_mcycle = read_csr(mcycle);
-
-  do {
-    delta_mtime = mtime_lo() - start_mtime;
-  } while (delta_mtime < n);
-
-  unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
-
-  return (delta_mcycle / delta_mtime) * mtime_freq
-         + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
-}
-
-unsigned long get_cpu_freq()
-{
-  static uint32_t cpu_freq;
-
-  if (!cpu_freq) {
-    // warm up I$
-    measure_cpu_freq(1);
-    // measure for real
-    cpu_freq = measure_cpu_freq(10);
-  }
-
-  return cpu_freq;
-}
-
-static void uart_init(size_t baud_rate)
-{
-  GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
-  GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
-  UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
-  UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
-}
-
-
-
-#ifdef USE_PLIC
-extern void handle_m_ext_interrupt();
-#endif
-
-#ifdef USE_M_TIME
-extern void handle_m_time_interrupt();
-#endif
-
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
-{
-  if (0){
-#ifdef USE_PLIC
-    // External Machine-Level interrupt from PLIC
-  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
-    handle_m_ext_interrupt();
-#endif
-#ifdef USE_M_TIME
-    // External Machine-Level interrupt from PLIC
-  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
-    handle_m_time_interrupt();
-#endif
-  }
-  else {
-    write(1, "trap\n", 5);
-    _exit(1 + mcause);
-  }
-  return epc;
-}
-
-void _init()
-{
-  
-  #ifndef NO_INIT
-  use_default_clocks();
-  use_pll(0, 0, 1, 31, 1);
-  uart_init(115200);
-
-  printf("core freq at %d Hz\n", get_cpu_freq());
-
-  write_csr(mtvec, &trap_entry);
-  if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
-    write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
-    write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
-  }
-  #endif
-  
-}
-
-void _fini()
-{
-}

env/hifive1/openocd.cfg

@@ -1,34 +0,0 @@
-adapter_khz     10000
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
-
-#Reset Stretcher logic on FE310 is ~1 second long
-#This doesn't apply if you use
-# ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
-init
-#reset -- This type of reset is not implemented yet
-if {[ info exists pulse_srst]} {
-  ftdi_set_signal nSRST 0
-  ftdi_set_signal nSRST z
-  #Wait for the reset stretcher
-  #It will work without this, but
-  #will incur lots of delays for later commands.
-  sleep 1500
-}	
-halt
-#flash protect 0 64 last off

env/hifive1/platform.h

@@ -1,133 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PLATFORM_H
-#define _SIFIVE_PLATFORM_H
-
-// Some things missing from the official encoding.h
-#define MCAUSE_INT         0x80000000
-#define MCAUSE_CAUSE       0x7FFFFFFF
-
-#include "sifive/const.h"
-#include "sifive/devices/aon.h"
-#include "sifive/devices/clint.h"
-#include "sifive/devices/gpio.h"
-#include "sifive/devices/otp.h"
-#include "sifive/devices/plic.h"
-#include "sifive/devices/prci.h"
-#include "sifive/devices/pwm.h"
-#include "sifive/devices/spi.h"
-#include "sifive/devices/uart.h"
-
-/****************************************************************************
- * Platform definitions
- *****************************************************************************/
-
-// Memory map
-#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
-#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
-#define OTP_MEM_ADDR _AC(0x00020000,UL)
-#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
-#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
-#define AON_CTRL_ADDR _AC(0x10000000,UL)
-#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
-#define OTP_CTRL_ADDR _AC(0x10010000,UL)
-#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
-#define UART0_CTRL_ADDR _AC(0x10013000,UL)
-#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
-#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
-#define UART1_CTRL_ADDR _AC(0x10023000,UL)
-#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
-#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
-#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
-#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
-#define SPI0_MEM_ADDR _AC(0x20000000,UL)
-#define MEM_CTRL_ADDR _AC(0x80000000,UL)
-
-// IOF masks
-#define IOF0_SPI1_MASK          _AC(0x000007FC,UL)
-#define SPI11_NUM_SS     (4)
-#define IOF_SPI1_SS0          (2u)
-#define IOF_SPI1_SS1          (8u)
-#define IOF_SPI1_SS2          (9u)
-#define IOF_SPI1_SS3          (10u)
-#define IOF_SPI1_MOSI         (3u)
-#define IOF_SPI1_MISO         (4u)
-#define IOF_SPI1_SCK          (5u)
-#define IOF_SPI1_DQ0          (3u)
-#define IOF_SPI1_DQ1          (4u)
-#define IOF_SPI1_DQ2          (6u)
-#define IOF_SPI1_DQ3          (7u)
-
-#define IOF0_SPI2_MASK          _AC(0xFC000000,UL)
-#define SPI2_NUM_SS       (1)
-#define IOF_SPI2_SS0          (26u)
-#define IOF_SPI2_MOSI         (27u)
-#define IOF_SPI2_MISO         (28u)
-#define IOF_SPI2_SCK          (29u)
-#define IOF_SPI2_DQ0          (27u)
-#define IOF_SPI2_DQ1          (28u)
-#define IOF_SPI2_DQ2          (30u)
-#define IOF_SPI2_DQ3          (31u)
-
-//#define IOF0_I2C_MASK          _AC(0x00003000,UL)
-
-#define IOF0_UART0_MASK         _AC(0x00030000, UL)
-#define IOF_UART0_RX   (16u)
-#define IOF_UART0_TX   (17u)
-
-#define IOF0_UART1_MASK         _AC(0x03000000, UL)
-#define IOF_UART1_RX (24u)
-#define IOF_UART1_TX (25u)
-
-#define IOF1_PWM0_MASK          _AC(0x0000000F, UL)
-#define IOF1_PWM1_MASK          _AC(0x00780000, UL)
-#define IOF1_PWM2_MASK          _AC(0x00003C00, UL)
-
-// Interrupt numbers
-#define INT_RESERVED 0
-#define INT_WDOGCMP 1
-#define INT_RTCCMP 2
-#define INT_UART0_BASE 3
-#define INT_UART1_BASE 4
-#define INT_SPI0_BASE 5
-#define INT_SPI1_BASE 6
-#define INT_SPI2_BASE 7
-#define INT_GPIO_BASE 8
-#define INT_PWM0_BASE 40
-#define INT_PWM1_BASE 44
-#define INT_PWM2_BASE 48
-
-// Helper functions
-#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
-#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
-#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
-#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
-#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
-#define OTP_REG(offset)  _REG32(OTP_CTRL_ADDR, offset)
-#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
-#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
-#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
-#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
-#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
-#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
-#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
-#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
-#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
-#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
-
-// Misc
-
-#include <stdint.h>
-
-#define NUM_GPIO 32
-
-#define PLIC_NUM_INTERRUPTS 52
-#define PLIC_NUM_PRIORITIES 7
-
-#include "hifive1.h"
-
-unsigned long get_cpu_freq(void);
-unsigned long get_timer_freq(void);
-uint64_t get_timer_value(void);
-
-#endif /* _SIFIVE_PLATFORM_H */

env/hifive1/settings.mk

@@ -1,3 +0,0 @@
-# Describes the CPU on this board to the rest of the SDK.
-RISCV_ARCH := rv32imac
-RISCV_ABI  := ilp32

env/iss/bsp_read.c

@@ -0,0 +1,6 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_read(int fd, void *ptr, size_t len) { return EOF; }

env/iss/bsp_write.c

@@ -0,0 +1,25 @@
+/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include <string.h>
+
+extern volatile uint64_t tohost;
+
+ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
+
+  if (isatty(fd)) {
+    volatile uint64_t payload[8];
+    memset((void *)payload, 0, 8 * sizeof(uint64_t));
+    payload[0] = 64;
+    payload[2] = (uintptr_t)ptr;
+    payload[3] = len;
+    tohost = (uintptr_t)payload;
+    return len;
+  }
+
+  return 1;
+}

env/iss/link.lds

@@ -5,7 +5,7 @@ ENTRY( _start )
 MEMORY
 {
   flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 1M
-  ram (wxa!ri) :   ORIGIN = 0x10000000, LENGTH = 16K
+  ram (wxa!ri) :   ORIGIN = 0x20000000, LENGTH = 1M
 }
 
 PHDRS
@@ -13,11 +13,12 @@ PHDRS
   flash PT_LOAD;
   ram_init PT_LOAD;
   ram PT_NULL;
+
 }
 
 SECTIONS
 {
-  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 8K;
 
   .init ORIGIN(flash)        :
   {
@@ -48,6 +49,18 @@ SECTIONS
     *(.gnu.linkonce.r.*)
   } >flash AT>flash :flash
 
+  .srodata        :
+  {
+
+    PROVIDE( _gp = . + 0x800 );
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+
+  } >flash AT>flash :flash
+  
   . = ALIGN(4);
 
   .preinit_array  :
@@ -123,21 +136,14 @@ SECTIONS
     *(.gnu.linkonce.d.*)
   } >ram AT>flash :ram_init
 
-  .srodata        :
-  {
-    PROVIDE( _gp = . + 0x800 );
-    *(.srodata.cst16)
-    *(.srodata.cst8)
-    *(.srodata.cst4)
-    *(.srodata.cst2)
-    *(.srodata .srodata.*)
-  } >ram AT>flash :ram_init
  
   .sdata          :
   {    
+     
     __SDATA_BEGIN__ = .;
     *(.sdata .sdata.*)
     *(.gnu.linkonce.s.*)
+
   } >ram AT>flash :ram_init
  
   . = ALIGN(4);
@@ -169,6 +175,7 @@ SECTIONS
     PROVIDE( _sp = . );
   } >ram AT>ram :ram
 
-  PROVIDE( tohost = 0xfffffff0 );
+  PROVIDE( tohost = . );
-  PROVIDE( fromhost = 0xfffffff8 );
+  PROVIDE( fromhost = . + 8 );
 }
+

env/iss/platform.h

@@ -7,7 +7,7 @@
 #define MCAUSE_INT         0x80000000
 #define MCAUSE_CAUSE       0x7FFFFFFF
 
-#include "rtl/const.h"
+#include "bits.h"
 /****************************************************************************
  * Platform definitions
  *****************************************************************************/
@@ -22,6 +22,9 @@
 
 #include <stdint.h>
 
+extern volatile uintptr_t tohost;
+extern volatile uintptr_t fromhost;
+
 void init_pll(void);
 unsigned long get_cpu_freq(void);
 unsigned long get_timer_freq(void);

env/moonlight/bsp_read.c

@@ -0,0 +1,21 @@
+#include "platform.h"
+#include <stdint.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_read(int fd, void *ptr, size_t len) {
+  uint8_t *current = (uint8_t *)ptr;
+  ssize_t result = 0;
+  if (isatty(fd)) {
+    for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
+                                   (get_uart_rx_tx_reg_rx_avail(uart) > 0);
+         current++) {
+      *current = uart_read(uart);
+      result++;
+    }
+
+    return result;
+  }
+  return EOF;
+}

env/moonlight/bsp_write.c

@@ -0,0 +1,21 @@
+/* See LICENSE of license details. */
+
+#include "platform.h"
+#include <errno.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
+  const uint8_t *current = (const uint8_t *)ptr;
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      uart_write(uart, current[jj]);
+      if (current[jj] == '\n') {
+        uart_write(uart, '\r');
+      }
+    }
+    return len;
+  }
+  return 1;
+}

env/moonlight/camera.lds

@@ -4,13 +4,13 @@ ENTRY( _start )
 
 MEMORY
 {
-  flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
+  rom (rxai!w) : ORIGIN = 0x80000000, LENGTH = 16k
-  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+  ram (wxa!ri) : ORIGIN = 0x80004000, LENGTH = 112k
 }
 
 PHDRS
 {
-  flash PT_LOAD;
+  rom PT_LOAD;
   ram_init PT_LOAD;
   ram PT_NULL;
 }
@@ -19,10 +19,10 @@ SECTIONS
 {
   __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
 
-  .init           :
+  .init ORIGIN(rom)        :
   {
     KEEP (*(SORT_NONE(.init)))
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom
 
   .text           :
   {
@@ -30,17 +30,24 @@ SECTIONS
     *(.text.startup .text.startup.*)
     *(.text .text.*)
     *(.gnu.linkonce.t.*)
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom
 
   .fini           :
   {
     KEEP (*(SORT_NONE(.fini)))
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom
 
   PROVIDE (__etext = .);
   PROVIDE (_etext = .);
   PROVIDE (etext = .);
 
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
   . = ALIGN(4);
 
   .preinit_array  :
@@ -48,7 +55,7 @@ SECTIONS
     PROVIDE_HIDDEN (__preinit_array_start = .);
     KEEP (*(.preinit_array))
     PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom
 
   .init_array     :
   {
@@ -56,7 +63,7 @@ SECTIONS
     KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
     KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
     PROVIDE_HIDDEN (__init_array_end = .);
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom
 
   .fini_array     :
   {
@@ -64,7 +71,7 @@ SECTIONS
     KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
     KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
     PROVIDE_HIDDEN (__fini_array_end = .);
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom
 
   .ctors          :
   {
@@ -86,7 +93,7 @@ SECTIONS
     KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
     KEEP (*(SORT(.ctors.*)))
     KEEP (*(.ctors))
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom
 
   .dtors          :
   {
@@ -95,38 +102,41 @@ SECTIONS
     KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
     KEEP (*(SORT(.dtors.*)))
     KEEP (*(.dtors))
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom
 
   .lalign         :
   {
     . = ALIGN(4);
     PROVIDE( _data_lma = . );
-  } >flash AT>flash :flash
+  } >rom AT>rom :rom
 
   .dalign         :
   {
     . = ALIGN(4);
     PROVIDE( _data = . );
-  } >ram AT>flash :ram_init
+  } >ram AT>rom :ram_init
 
   .data          :
   {
-    *(.rdata)
-    *(.rodata .rodata.*)
-    *(.gnu.linkonce.r.*)
     *(.data .data.*)
     *(.gnu.linkonce.d.*)
-    . = ALIGN(8);
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
     PROVIDE( __global_pointer$ = . + 0x800 );
-    *(.sdata .sdata.*)
-    *(.gnu.linkonce.s.*)
-    . = ALIGN(8);
     *(.srodata.cst16)
     *(.srodata.cst8)
     *(.srodata.cst4)
     *(.srodata.cst2)
     *(.srodata .srodata.*)
-  } >ram AT>flash :ram_init
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
 
   . = ALIGN(4);
   PROVIDE( _edata = . );

env/moonlight/init.c

@@ -0,0 +1,138 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include "platform.h"
+#include "encoding.h"
+
+
+extern int main(int argc, char** argv);
+extern void trap_entry(void);
+#define IRQ_M_SOFT   3
+#define IRQ_M_TIMER  7
+#define IRQ_M_EXT    11
+
+#define NUM_INTERRUPTS 16
+#define MTIMER_NEXT_TICK_INC 1000
+
+void handle_m_ext_interrupt(void);
+void handle_m_time_interrupt(void);
+uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp);
+void default_handler(void);
+void _init(void);
+
+typedef void (*my_interrupt_function_ptr_t) (void);
+my_interrupt_function_ptr_t localISR[NUM_INTERRUPTS] __attribute__((aligned(64)));
+
+static unsigned long mtime_lo(void)
+{
+    unsigned long ret;
+    __asm volatile("rdtime %0":"=r"(ret));
+    return ret;
+}
+
+
+#if __riscv_xlen==32
+
+static uint32_t mtime_hi(void)
+{
+    unsigned long ret;
+    __asm volatile("rdtimeh %0":"=r"(ret));
+    return ret;
+}
+
+uint64_t get_timer_value(void)
+{
+  while (1) {
+    uint32_t hi = mtime_hi();
+    uint32_t lo = mtime_lo();
+    if (hi == mtime_hi())
+      return ((uint64_t)hi << 32) | lo;
+  }
+}
+
+#elif __riscv_xlen==64
+
+uint64_t get_timer_value()
+{
+  return mtime_lo();
+}
+
+#endif
+
+unsigned long get_timer_freq()
+{
+  return 32768;
+}
+
+unsigned long get_cpu_freq()
+{
+  return 100000000;
+}
+
+void init_pll(void){
+    //TODO: implement initialization
+}
+
+static void uart_init(size_t baud_rate)
+{
+  //TODO: implement initialization
+}
+
+void __attribute__((weak)) handle_m_ext_interrupt(){
+}
+
+void __attribute__((weak)) handle_m_time_interrupt(){
+  uint64_t time = get_aclint_mtime(aclint);
+  time+=MTIMER_NEXT_TICK_INC;
+  set_aclint_mtimecmp(aclint, time);
+}
+
+void __attribute__((weak)) default_handler(void) {
+  puts("default handler\n");
+}
+
+void __attribute__((weak)) interrupt_handler(unsigned) {
+  puts("interrupt handler\n");
+}
+
+uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp){
+  if ((mcause & MCAUSE_INT)) {
+    if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
+      handle_m_ext_interrupt();
+    } else if (((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ 
+      handle_m_time_interrupt();
+    } else {
+      interrupt_handler(mcause& ~MCAUSE_INT);
+    }
+  } else {
+    write(1, "trap\n", 5);
+    _exit(1 + mcause);
+  }
+  return mepc;
+}
+
+void _init()
+{
+  
+#ifndef NO_INIT
+  init_pll();
+  uart_init(115200);
+  printf("core freq at %lu Hz\n", get_cpu_freq());
+  write_csr(mtvec, &trap_entry);
+  if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
+    write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
+    write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
+  }
+  int i=0;
+  while(i<NUM_INTERRUPTS)  {
+    localISR[i++] = default_handler;
+  }
+
+#endif
+  
+}
+
+void _fini(void)
+{
+}

env/moonlight/link.lds

@@ -4,8 +4,10 @@ ENTRY( _start )
 
 MEMORY
 {
-  flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 512M
+  rom   (rxai!w) : ORIGIN = 0xFFFFE000, LENGTH = 2k
-  ram (wxa!ri) :   ORIGIN = 0x80000000, LENGTH = 128K
+  flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 16M
+  ram   (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128K
+  dram  (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 2048M
 }
 
 PHDRS
@@ -13,6 +15,7 @@ PHDRS
   flash PT_LOAD;
   ram_init PT_LOAD;
   ram PT_NULL;
+  dram PT_NULL;
 }
 
 SECTIONS
@@ -104,6 +107,11 @@ SECTIONS
     KEEP (*(.dtors))
   } >flash AT>flash :flash
 
+  .dummy          :
+  {
+	*(.comment.*)
+
+  }
   .lalign         :
   {
     . = ALIGN(4);
@@ -123,16 +131,6 @@ SECTIONS
     *(.gnu.linkonce.d.*)
   } >ram AT>flash :ram_init
 
-  .srodata        :
-  {
-    PROVIDE( _gp = . + 0x800 );
-    *(.srodata.cst16)
-    *(.srodata.cst8)
-    *(.srodata.cst4)
-    *(.srodata.cst2)
-    *(.srodata .srodata.*)
-  } >ram AT>flash :ram_init
-
   .sdata          :
   {
     __SDATA_BEGIN__ = .;
@@ -140,6 +138,15 @@ SECTIONS
     *(.gnu.linkonce.s.*)
   } >ram AT>flash :ram_init
 
+  .srodata        :
+  {
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash :ram_init
+
   . = ALIGN(4);
   PROVIDE( _edata = . );
   PROVIDE( edata = . );
@@ -169,6 +176,8 @@ SECTIONS
     PROVIDE( _sp = . );
   } >ram AT>ram :ram
 
-  PROVIDE( tohost = 0xfffffff0 );
+
-  PROVIDE( fromhost = 0xfffffff8 );
+  
+  PROVIDE( tohost = . );
+  PROVIDE( fromhost = . + 8 );
 }

env/moonlight/platform.h

@@ -0,0 +1,60 @@
+// See LICENSE for license details.
+
+#ifndef _ISS_PLATFORM_H
+#define _ISS_PLATFORM_H
+
+#if __riscv_xlen == 32
+#define MCAUSE_INT 0x80000000UL
+#define MCAUSE_CAUSE 0x000003FFUL
+#else
+#define MCAUSE_INT 0x8000000000000000UL
+#define MCAUSE_CAUSE 0x00000000000003FFUL
+#endif
+
+#define APB_BUS
+
+#include "minres/devices/aclint.h"
+#include "minres/devices/camera.h"
+#include "minres/devices/dma.h"
+#include "minres/devices/gen/sysctrl.h"
+#include "minres/devices/gpio.h"
+#include "minres/devices/i2s.h"
+#include "minres/devices/msg_if.h"
+#include "minres/devices/qspi.h"
+#include "minres/devices/timer.h"
+#include "minres/devices/uart.h"
+
+#define PERIPH(TYPE, ADDR) ((volatile TYPE *)(ADDR))
+
+#define APB_BASE 0xF0000000
+
+#define gpio PERIPH(gpio_t, APB_BASE + 0x0000)
+#define uart PERIPH(uart_t, APB_BASE + 0x01000)
+#define timer PERIPH(timercounter_t, APB_BASE + 0x20000)
+#define aclint PERIPH(aclint_t, APB_BASE + 0x30000)
+#define sysctrl PERIPH(sysctrl_t, APB_BASE + 0x40000)
+#define qspi PERIPH(qspi_t, APB_BASE + 0x50000)
+#define i2s PERIPH(i2s_t, APB_BASE + 0x90000)
+#define camera PERIPH(camera_t, APB_BASE + 0xA0000)
+#define dma PERIPH(dma_t, APB_BASE + 0xB0000)
+#define msgif PERIPH(mkcontrolclusterstreamcontroller_t, APB_BASE + 0xC0000)
+
+#include "minres/devices/fki_cluster_info.h"
+#include "minres/devices/flexki_messages.h"
+
+#ifndef XIP_START_LOC
+#define XIP_START_LOC 0xE0000000
+#endif
+#ifndef RAM_START_LOC
+#define RAM_START_LOC 0xC0000000
+#endif
+
+// Misc
+
+#include <stdint.h>
+
+void init_pll(void);
+unsigned long get_cpu_freq(void);
+unsigned long get_timer_freq(void);
+
+#endif /* _ISS_PLATFORM_H */

env/moonlight/ram.lds

@@ -0,0 +1,173 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  rom (rxai!w) : ORIGIN = 0xC0000000, LENGTH = 64k
+  ram (wxa!ri) : ORIGIN = 0xC0010000, LENGTH = 64k
+}
+
+PHDRS
+{
+  rom PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(rom)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >rom AT>rom :rom
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >rom AT>rom :rom
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >rom AT>rom :rom
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >rom AT>rom :rom
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >rom AT>rom :rom
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom AT>rom :rom
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >rom AT>rom :rom
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >rom AT>rom :rom
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >rom AT>rom :rom
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>rom :ram_init
+
+  .data          :
+  {
+    __DATA_BEGIN__ = .;
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>rom :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  __BSS_END__ = .;
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+
+  PROVIDE( tohost = 0xfffffff0 );
+  PROVIDE( fromhost = 0xfffffff8 );
+}

env/moonlight/rom.lds

@@ -0,0 +1,173 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 2k
+  ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128k
+}
+
+PHDRS
+{
+  rom PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(rom)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >rom AT>rom :rom
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >rom AT>rom :rom
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >rom AT>rom :rom
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >rom AT>rom :rom
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >rom AT>rom :rom
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom AT>rom :rom
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >rom AT>rom :rom
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >rom AT>rom :rom
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >rom AT>rom :rom
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>rom :ram_init
+
+  .data          :
+  {
+    __DATA_BEGIN__ = .;
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>rom :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  __BSS_END__ = .;
+  __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,  MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+
+  PROVIDE( tohost = 0xfffffff0 );
+  PROVIDE( fromhost = 0xfffffff8 );
+}

env/moonlight/spi_flash.lds

@@ -0,0 +1,180 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 16M
+  ram   (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128K
+  dram  (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 2048M
+}
+
+PHDRS
+{
+  flash PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+  dram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(flash)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash :flash
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash :flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash :flash
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >flash AT>flash :flash
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash :flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash :flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash :flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash :flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash :flash
+
+  .dummy          :
+  {
+	*(.comment.*)
+
+  }
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash :flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash :ram_init
+
+  .data          :
+  {
+    __DATA_BEGIN__ = .;
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>flash :ram_init
+
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>flash :ram_init
+
+  .srodata        :
+  {
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  __BSS_END__ = .;
+  __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,  MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+	PROVIDE( tohost = . );
+  	PROVIDE( fromhost = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+
+}

env/riscv_vp/bsp_read.c

@@ -0,0 +1,21 @@
+#include "platform.h"
+#include <stdint.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_read(int fd, void *ptr, size_t len) {
+  uint8_t *current = (uint8_t *)ptr;
+  ssize_t result = 0;
+  if (isatty(fd)) {
+    for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
+                                   (get_uart_rx_tx_reg_rx_avail(uart) > 0);
+         current++) {
+      *current = uart_read(uart);
+      result++;
+    }
+
+    return result;
+  }
+  return EOF;
+}

env/riscv_vp/bsp_write.c

@@ -0,0 +1,21 @@
+/* See LICENSE of license details. */
+
+#include "platform.h"
+#include <errno.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
+  const uint8_t *current = (const uint8_t *)ptr;
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      uart_write(uart, current[jj]);
+      if (current[jj] == '\n') {
+        uart_write(uart, '\r');
+      }
+    }
+    return len;
+  }
+  return 1;
+}

env/riscv_vp/flash.lds

@@ -2,24 +2,21 @@ OUTPUT_ARCH( "riscv" )
 
 ENTRY( _start )
 
-MEMORY
+INCLUDE memory_map.ld
-{
-  flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
-  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 512K
-}
 
 PHDRS
 {
   flash PT_LOAD;
   ram_init PT_LOAD;
   ram PT_NULL;
+  dram PT_NULL;
 }
 
 SECTIONS
 {
   __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
 
-  .init           :
+  .init ORIGIN(flash)        :
   {
     KEEP (*(SORT_NONE(.init)))
   } >flash AT>flash :flash
@@ -104,11 +101,11 @@ SECTIONS
     KEEP (*(.dtors))
   } >flash AT>flash :flash
 
-  .except :
+  .dummy          :
   {
-  	*(.gcc_except_table.*)
+	*(.comment.*)
-  } >flash AT>flash :flash
 
+  }
   .lalign         :
   {
     . = ALIGN(4);
@@ -123,13 +120,20 @@ SECTIONS
 
   .data          :
   {
+    __DATA_BEGIN__ = .;
     *(.data .data.*)
     *(.gnu.linkonce.d.*)
-    . = ALIGN(8);
+  } >ram AT>flash :ram_init
-    PROVIDE( __global_pointer$ = . + 0x800 );
+
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
     *(.sdata .sdata.*)
     *(.gnu.linkonce.s.*)
-    . = ALIGN(8);
+  } >ram AT>flash :ram_init
+
+  .srodata        :
+  {
     *(.srodata.cst16)
     *(.srodata.cst8)
     *(.srodata.cst4)
@@ -154,6 +158,8 @@ SECTIONS
   } >ram AT>ram :ram
 
   . = ALIGN(8);
+  __BSS_END__ = .;
+  __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,  MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
   PROVIDE( _end = . );
   PROVIDE( end = . );
 
@@ -163,4 +169,9 @@ SECTIONS
     . = __stack_size;
     PROVIDE( _sp = . );
   } >ram AT>ram :ram
+
+
+  
+  PROVIDE( tohost = . );
+  PROVIDE( fromhost = . + 8 );
 }

env/riscv_vp/init.c

@@ -0,0 +1,138 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include "platform.h"
+#include "encoding.h"
+
+
+extern int main(int argc, char** argv);
+extern void trap_entry(void);
+#define IRQ_M_SOFT   3
+#define IRQ_M_TIMER  7
+#define IRQ_M_EXT    11
+
+#define NUM_INTERRUPTS 16
+#define MTIMER_NEXT_TICK_INC 1000
+
+void handle_m_ext_interrupt(void);
+void handle_m_time_interrupt(void);
+uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp);
+void default_handler(void);
+void _init(void);
+
+typedef void (*my_interrupt_function_ptr_t) (void);
+my_interrupt_function_ptr_t localISR[NUM_INTERRUPTS] __attribute__((aligned(64)));
+
+static unsigned long mtime_lo(void)
+{
+    unsigned long ret;
+    __asm volatile("rdtime %0":"=r"(ret));
+    return ret;
+}
+
+
+#if __riscv_xlen==32
+
+static uint32_t mtime_hi(void)
+{
+    unsigned long ret;
+    __asm volatile("rdtimeh %0":"=r"(ret));
+    return ret;
+}
+
+uint64_t get_timer_value(void)
+{
+  while (1) {
+    uint32_t hi = mtime_hi();
+    uint32_t lo = mtime_lo();
+    if (hi == mtime_hi())
+      return ((uint64_t)hi << 32) | lo;
+  }
+}
+
+#elif __riscv_xlen==64
+
+uint64_t get_timer_value()
+{
+  return mtime_lo();
+}
+
+#endif
+
+unsigned long get_timer_freq()
+{
+  return 32768;
+}
+
+unsigned long get_cpu_freq()
+{
+  return 100000000;
+}
+
+void init_pll(void){
+    //TODO: implement initialization
+}
+
+static void uart_init(size_t baud_rate)
+{
+  //TODO: implement initialization
+}
+
+void __attribute__((weak)) handle_m_ext_interrupt(){
+}
+
+void __attribute__((weak)) handle_m_time_interrupt(){
+  uint64_t time = get_aclint_mtime(aclint);
+  time+=MTIMER_NEXT_TICK_INC;
+  set_aclint_mtimecmp(aclint, time);
+}
+
+void __attribute__((weak)) default_handler(void) {
+  puts("default handler\n");
+}
+
+void __attribute__((weak)) interrupt_handler(unsigned) {
+  puts("interrupt handler\n");
+}
+
+uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp){
+  if ((mcause & MCAUSE_INT)) {
+    if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
+      handle_m_ext_interrupt();
+    } else if (((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ 
+      handle_m_time_interrupt();
+    } else {
+      interrupt_handler(mcause& ~MCAUSE_INT);
+    }
+  } else {
+    write(1, "trap\n", 5);
+    _exit(1 + mcause);
+  }
+  return mepc;
+}
+
+void _init()
+{
+  
+#ifndef NO_INIT
+  init_pll();
+  uart_init(115200);
+  printf("core freq at %lu Hz\n", get_cpu_freq());
+  write_csr(mtvec, &trap_entry);
+  if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
+    write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
+    write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
+  }
+  int i=0;
+  while(i<NUM_INTERRUPTS)  {
+    localISR[i++] = default_handler;
+  }
+
+#endif
+  
+}
+
+void _fini(void)
+{
+}

env/riscv_vp/memory_map.ld

@@ -0,0 +1,7 @@
+MEMORY
+{
+  ram   (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 128K
+  rom   (rxai!w) : ORIGIN = 0x10080000, LENGTH = 8k
+  flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 16M
+  dram  (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 2048M
+}

env/riscv_vp/platform.h

@@ -0,0 +1,48 @@
+// See LICENSE for license details.
+
+#ifndef _ISS_PLATFORM_H
+#define _ISS_PLATFORM_H
+
+#if __riscv_xlen == 32
+#define MCAUSE_INT 0x80000000UL
+#define MCAUSE_CAUSE 0x000003FFUL
+#else
+#define MCAUSE_INT 0x8000000000000000UL
+#define MCAUSE_CAUSE 0x00000000000003FFUL
+#endif
+
+#define APB_BUS
+
+#include "minres/devices/aclint.h"
+#include "minres/devices/dma.h"
+#include "minres/devices/gen/sysctrl.h"
+#include "minres/devices/gpio.h"
+#include "minres/devices/i2s.h"
+#include "minres/devices/qspi.h"
+#include "minres/devices/timer.h"
+#include "minres/devices/uart.h"
+
+#define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR))
+// values from memory_map.ld
+#define XIP_START_LOC 0x20000000
+#define RAM_START_LOC 0x00000000
+#define APB_BASE 0x10000000
+
+#define gpio PERIPH(gpio_t, APB_BASE + 0x0000)
+#define uart PERIPH(uart_t, APB_BASE + 0x01000)
+#define timer PERIPH(timercounter_t, APB_BASE + 0x20000)
+#define aclint PERIPH(aclint_t, APB_BASE + 0x30000)
+#define sysctrl PERIPH(sysctrl_t, APB_BASE + 0x40000)
+#define qspi PERIPH(qspi_t, APB_BASE + 0x50000)
+#define i2s PERIPH(i2s_t, APB_BASE + 0x90000)
+#define dma PERIPH(dma_t, APB_BASE + 0xB0000)
+
+// Misc
+
+#include <stdint.h>
+
+void init_pll(void);
+unsigned long get_cpu_freq(void);
+unsigned long get_timer_freq(void);
+
+#endif /* _ISS_PLATFORM_H */

env/riscv_vp/rom.lds

@@ -0,0 +1,177 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+INCLUDE memory_map.ld
+
+PHDRS
+{
+  rom PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+  dram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(rom)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >rom AT>rom :rom
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >rom AT>rom :rom
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >rom AT>rom :rom
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >rom AT>rom :rom
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >rom AT>rom :rom
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >rom AT>rom :rom
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom AT>rom :rom
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >rom AT>rom :rom
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >rom AT>rom :rom
+
+  .dummy          :
+  {
+	*(.comment.*)
+
+  }
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >rom AT>rom :rom
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>rom :ram_init
+
+  .data          :
+  {
+    __DATA_BEGIN__ = .;
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>rom :ram_init
+
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
+  .srodata        :
+  {
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>rom :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  __BSS_END__ = .;
+  __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,  MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+
+
+  
+  PROVIDE( tohost = . );
+  PROVIDE( fromhost = . + 8 );
+}

env/semihosting.c

@@ -0,0 +1,195 @@
+#include <stdarg.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include "semihosting.h"
+
+#define SEMIHOSTING_SYS_OPEN 0x01
+#define SEMIHOSTING_SYS_CLOSE 0x02
+#define SEMIHOSTING_SYS_WRITEC 0x03
+#define SEMIHOSTING_SYS_WRITE0 0x04
+#define SEMIHOSTING_SYS_WRITE 0x05
+#define SEMIHOSTING_SYS_READ 0x06
+#define SEMIHOSTING_SYS_READC 0x07
+#define SEMIHOSTING_SYS_ISERROR 0x08
+#define SEMIHOSTING_SYS_ISTTY 0x09
+#define SEMIHOSTING_SYS_SEEK 0x0A
+#define SEMIHOSTING_SYS_FLEN 0x0C
+#define SEMIHOSTING_SYS_TMPNAM 0x0D
+#define SEMIHOSTING_SYS_REMOVE 0x0E
+#define SEMIHOSTING_SYS_RENAME 0x0F
+#define SEMIHOSTING_SYS_CLOCK 0x10
+#define SEMIHOSTING_SYS_TIME 0x11
+#define SEMIHOSTING_SYS_SYSTEM 0x12
+#define SEMIHOSTING_SYS_ERRNO 0x13
+#define SEMIHOSTING_SYS_GET_CMDLINE 0x15
+#define SEMIHOSTING_SYS_HEAPINFO 0x16
+#define SEMIHOSTING_EnterSVC 0x17
+#define SEMIHOSTING_SYS_EXIT 0x18
+#define SEMIHOSTING_SYS_EXIT_EXTENDED 0x20
+#define SEMIHOSTING_SYS_ELAPSED 0x30
+#define SEMIHOSTING_SYS_TICKFREQ 0x31
+
+#define RISCV_SEMIHOSTING_CALL_NUMBER 7
+
+typedef struct {
+  char *str;
+  int mode;
+  size_t length;
+} OpenVector;
+
+typedef struct {
+  char *old;
+  int old_len;
+  char *new;
+  int new_len;
+} RenameVector;
+
+typedef struct {
+  char *path;
+  size_t len;
+} RemoveVector;
+
+typedef struct {
+  int fd;
+  off_t pos;
+} SeekVector;
+
+static inline int __attribute__((always_inline))
+call_host(int reason, void *arg) {
+#if 1
+  // This must always be set back to 0 to cover the case where a host wasn't
+  // initially present, but only connected while the program was already up and
+  // running. In that case, trap() suddenly won't be called anymore, so we have
+  // to clear this variable *before* EBREAK is called.
+  sh_missing_host = 0;
+
+  register int value asm("a0") = reason;
+  register void *ptr asm("a1") = arg;
+  asm volatile(
+      // Workaround for RISC-V lack of multiple EBREAKs.
+      " .option push \n"
+      " .option norvc \n"
+      // Force 16-byte alignment to make sure that the 3 instruction fall
+      // within the same virtual page. If you the instruction straddle a page
+      // boundary the debugger fetching the instructions could lead to a page
+      // fault. Note: align 4 means, align by 2 to the power of 4!
+      " .align 4 \n"
+      " slli x0, x0, 0x1f \n"
+      " ebreak \n"
+      " srai x0, x0, 0x07 \n"
+      " .option pop \n"
+
+      : "=r"(value) /* Outputs */
+      : "0"(value),
+        "r"(ptr), [swi] "i"(RISCV_SEMIHOSTING_CALL_NUMBER) /* Inputs */
+      : "memory"                                           /* Clobbers */
+  );
+  return value;
+#else
+  return 0;
+#endif
+}
+
+int sh_errno(void) { return call_host(SEMIHOSTING_SYS_ERRNO, (void *)NULL); }
+
+int sh_time(void) { return call_host(SEMIHOSTING_SYS_TIME, (void *)NULL); }
+
+int sh_remove(char *path) {
+  size_t len = strlen(path);
+  RemoveVector vec = {path, len};
+  return call_host(SEMIHOSTING_SYS_REMOVE, &vec);
+}
+
+void sh_seek(int file_handle, off_t pos) {
+  SeekVector vec = {file_handle, pos};
+  call_host(SEMIHOSTING_SYS_SEEK, &vec);
+  return;
+}
+
+void sh_write(char *str, int file_handle) {
+  size_t length = strlen(str);
+  OpenVector vec = {str, file_handle, length};
+  call_host(SEMIHOSTING_SYS_WRITE, &vec);
+  return;
+}
+
+int sh_close(int file_handle) {
+  return call_host(SEMIHOSTING_SYS_CLOSE, file_handle);
+}
+
+void sh_exit(void) {
+  call_host(SEMIHOSTING_SYS_EXIT, (void *)NULL);
+  return;
+}
+
+void sh_exit_extended(void) {
+  call_host(SEMIHOSTING_SYS_EXIT_EXTENDED, (void *)NULL);
+  return;
+}
+
+int sh_flen(int file_handle) {
+  return call_host(SEMIHOSTING_SYS_FLEN, file_handle);
+}
+
+int sh_iserror(int num) { return call_host(SEMIHOSTING_SYS_ISERROR, num); }
+
+int sh_istty(int file_handle) {
+  return call_host(SEMIHOSTING_SYS_ISTTY, file_handle);
+}
+/*
+int sh_remove(char* path) {
+    size_t len = strlen(path);
+    RemoveVector vec = {path, len};
+    return call_host(SEMIHOSTING_SYS_REMOVE, &vec);
+}*/
+
+void sh_rename(char *old, char *new) {
+  int old_len = strlen(old);
+  int new_len = strlen(new);
+  RenameVector vec = {old, old_len, new, new_len};
+  call_host(SEMIHOSTING_SYS_RENAME, &vec);
+  return;
+}
+
+void sh_write0(const char *buf) {
+  // Print zero-terminated string
+  call_host(SEMIHOSTING_SYS_WRITE0, (void *)buf);
+}
+
+void sh_writec(char c) {
+  // Print single character
+  call_host(SEMIHOSTING_SYS_WRITEC, (void *)&c);
+}
+
+char sh_readc(void) {
+  // Read character from keyboard. (Blocking operation!)
+  char c = call_host(SEMIHOSTING_SYS_READC, (void *)NULL);
+  return c;
+}
+
+int sh_open(char *str, int mode) {
+  // mode = 0;
+  // int length = 44;
+  size_t length = strlen(str);
+  OpenVector vec = {str, mode, length};
+  return call_host(SEMIHOSTING_SYS_OPEN, &vec);
+}
+
+int sh_read(char *buf, int file_handle, size_t length) {
+  OpenVector vec = {buf, file_handle, length};
+  int i = call_host(SEMIHOSTING_SYS_READ, &vec);
+  return i;
+}
+
+int sh_clock(void) {
+  int clock = call_host(SEMIHOSTING_SYS_CLOCK, (void *)NULL);
+  return clock;
+}
+
+/*
+void sh_write(char* str, int file_handle) {
+    return;
+}*/

env/start.S

@@ -1,3 +1,4 @@
+#include "encoding.h"
 // See LICENSE for license details.
 
 	.section .init
@@ -5,14 +6,21 @@
 	.type _start,@function
 
 _start:
-    la gp, trap_entry
-    csrw mtvec, gp
 .option push
 .option norelax
+.option norvc
+//#ifdef WITH_SIGNATURE
+	j 1f
+	.2byte	0x4e4d
+	.2byte	0x5352
+	.4byte  0x669
+1:
+//#endif
     la gp, __global_pointer$
 .option pop
 	la sp, _sp
-
+    la t0, trap_entry
+    csrw mtvec, t0
 	/* Load data section */
 	la a0, _data_lma
 	la a1, _data
@@ -37,11 +45,11 @@ _start:
 2:
 
 	/* Call global constructors */
-//#ifdef HAVE_INIT_FINI
+#ifndef HAVE_NO_INIT_FINI
 	la a0, __libc_fini_array
 	call atexit
 	call __libc_init_array
-//#endif
+#endif
 #ifndef __riscv_float_abi_soft
 	/* Enable FPU */
 	li t0, MSTATUS_FS

env/testbench/TGCP/platform.h

@@ -7,7 +7,7 @@
 #define MCAUSE_INT         0x80000000
 #define MCAUSE_CAUSE       0x7FFFFFFF
 
-#include "rtl/const.h"
+#include "bits.h"
 /****************************************************************************
  * Platform definitions
  *****************************************************************************/

env/testbench/rtl/.gitignore

@@ -0,0 +1 @@
+/*.o

env/testbench/rtl/bsp_read.c

@@ -0,0 +1,19 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_read(int fd, void *ptr, size_t len) {
+  uint8_t *current = (uint8_t *)ptr;
+  volatile uint32_t *uart_rx = (uint32_t *)0xFFFF0000;
+  ssize_t result = 0;
+  if (isatty(fd)) {
+    for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len);
+         current++) {
+      *current = *uart_rx;
+      result++;
+    }
+    return result;
+  }
+  return EOF;
+}

env/testbench/rtl/bsp_write.c

@@ -0,0 +1,18 @@
+/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <stdint.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+ssize_t _bsp_write(int fd, const void *ptr, size_t len) {
+  const uint8_t *current = (const uint8_t *)ptr;
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      *((uint32_t *)0xFFFF0000) = current[jj];
+    }
+    return len;
+  }
+
+  return 1;
+}

env/testbench/rtl/platform.h

@@ -7,7 +7,18 @@
 #define MCAUSE_INT         0x80000000
 #define MCAUSE_CAUSE       0x7FFFFFFF
 
-#include "rtl/const.h"
+#define UART0_BASE_ADDR 0xffff0000ULL
+
+#define UART_REG_TXFIFO         0x00
+#define UART_REG_RXFIFO         0x04
+#define UART_REG_TXCTRL         0x08
+#define UART_REG_RXCTRL         0x0c
+#define UART_REG_IE             0x10
+#define UART_REG_IP             0x14
+#define UART_REG_DIV            0x18
+#define UART_TXEN               0x1
+
+#define UART0_REG(ADDR) *((volatile uint32_t*) (UART0_BASE_ADDR + ADDR))
 /****************************************************************************
  * Platform definitions
  *****************************************************************************/

env/tgc-vp/init.c

@@ -1,116 +0,0 @@
-#include <stdint.h>
-#include <stdio.h>
-#include <unistd.h>
-
-#include "platform.h"
-#include "encoding.h"
-
-extern int main(int argc, char** argv);
-extern void trap_entry();
-
-static unsigned long mtime_lo(void)
-{
-    unsigned long ret;
-    __asm volatile("rdtime %0":"=r"(ret));
-    return ret;
-}
-
-
-#if __riscv_xlen==32
-
-static uint32_t mtime_hi(void)
-{
-    unsigned long ret;
-    __asm volatile("rdtimeh %0":"=r"(ret));
-    return ret;
-}
-
-uint64_t get_timer_value()
-{
-  while (1) {
-    uint32_t hi = mtime_hi();
-    uint32_t lo = mtime_lo();
-    if (hi == mtime_hi())
-      return ((uint64_t)hi << 32) | lo;
-  }
-}
-
-#elif __riscv_xlen==64
-
-uint64_t get_timer_value()
-{
-  return mtime_lo();
-}
-
-#endif
-
-unsigned long get_timer_freq()
-{
-  return 32768;
-}
-
-unsigned long get_cpu_freq()
-{
-  return 10000000;
-}
-
-void init_pll(void){
-
-}
-
-static void uart_init(size_t baud_rate)
-{
-  GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
-  GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
-  UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
-  UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
-}
-
-#ifdef USE_PLIC
-extern void handle_m_ext_interrupt();
-#endif
-
-#ifdef USE_M_TIME
-extern void handle_m_time_interrupt();
-#endif
-
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
-{
-  if (0){
-#ifdef USE_PLIC
-    // External Machine-Level interrupt from PLIC
-  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
-    handle_m_ext_interrupt();
-#endif
-#ifdef USE_M_TIME
-    // External Machine-Level interrupt from PLIC
-  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
-    handle_m_time_interrupt();
-#endif
-  }
-  else {
-    write(1, "trap\n", 5);
-    _exit(1 + mcause);
-  }
-  return epc;
-}
-
-void _init()
-{
-  
-#ifndef NO_INIT
-  init_pll();
-  uart_init(115200);
-  printf("core freq at %d Hz\n", get_cpu_freq());
-  write_csr(mtvec, &trap_entry);
-  if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
-    write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
-    write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
-  }
-#endif
-  
-}
-
-void _fini()
-{
-}

env/tgc-vp/platform.h

@@ -1,127 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _ISS_PLATFORM_H
-#define _ISS_PLATFORM_H
-
-// Some things missing from the official encoding.h
-#define MCAUSE_INT         0x80000000
-#define MCAUSE_CAUSE       0x7FFFFFFF
-
-#include "tgc-vp/const.h"
-#include "tgc-vp/devices/aon.h"
-#include "tgc-vp/devices/clint.h"
-#include "tgc-vp/devices/gpio.h"
-#include "tgc-vp/devices/otp.h"
-#include "tgc-vp/devices/plic.h"
-#include "tgc-vp/devices/prci.h"
-#include "tgc-vp/devices/pwm.h"
-#include "tgc-vp/devices/spi.h"
-#include "tgc-vp/devices/uart.h"
-
-/****************************************************************************
- * Platform definitions
- *****************************************************************************/
-
-// Memory map
-#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
-#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
-#define OTP_MMAP_ADDR _AC(0x00020000,UL)
-#define CLINT_BASE_ADDR _AC(0x02000000,UL)
-#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
-#define AON_BASE_ADDR _AC(0x10000000,UL)
-#define PRCI_BASE_ADDR _AC(0x10008000,UL)
-#define OTP_BASE_ADDR _AC(0x10010000,UL)
-#define GPIO_BASE_ADDR _AC(0x10012000,UL)
-#define UART0_BASE_ADDR _AC(0x10013000,UL)
-#define SPI0_BASE_ADDR _AC(0x10014000,UL)
-#define PWM0_BASE_ADDR _AC(0x10015000,UL)
-#define UART1_BASE_ADDR _AC(0x10023000,UL)
-#define SPI1_BASE_ADDR _AC(0x10024000,UL)
-#define PWM1_BASE_ADDR _AC(0x10025000,UL)
-#define SPI2_BASE_ADDR _AC(0x10034000,UL)
-#define PWM2_BASE_ADDR _AC(0x10035000,UL)
-#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
-#define MEM_BASE_ADDR _AC(0x80000000,UL)
-
-// IOF masks
-#define IOF0_SPI1_MASK          _AC(0x000007FC,UL)
-#define SPI11_NUM_SS     (4)
-#define IOF_SPI1_SS0          (2u)
-#define IOF_SPI1_SS1          (8u)
-#define IOF_SPI1_SS2          (9u)
-#define IOF_SPI1_SS3          (10u)
-#define IOF_SPI1_MOSI         (3u)
-#define IOF_SPI1_MISO         (4u)
-#define IOF_SPI1_SCK          (5u)
-#define IOF_SPI1_DQ0          (3u)
-#define IOF_SPI1_DQ1          (4u)
-#define IOF_SPI1_DQ2          (6u)
-#define IOF_SPI1_DQ3          (7u)
-
-#define IOF0_SPI2_MASK          _AC(0xFC000000,UL)
-#define SPI2_NUM_SS       (1)
-#define IOF_SPI2_SS0          (26u)
-#define IOF_SPI2_MOSI         (27u)
-#define IOF_SPI2_MISO         (28u)
-#define IOF_SPI2_SCK          (29u)
-#define IOF_SPI2_DQ0          (27u)
-#define IOF_SPI2_DQ1          (28u)
-#define IOF_SPI2_DQ2          (30u)
-#define IOF_SPI2_DQ3          (31u)
-
-//#define IOF0_I2C_MASK          _AC(0x00003000,UL)
-
-#define IOF0_UART0_MASK         _AC(0x00030000, UL)
-#define IOF_UART0_RX   (16u)
-#define IOF_UART0_TX   (17u)
-
-#define IOF0_UART1_MASK         _AC(0x03000000, UL)
-#define IOF_UART1_RX (24u)
-#define IOF_UART1_TX (25u)
-
-#define IOF1_PWM0_MASK          _AC(0x0000000F, UL)
-#define IOF1_PWM1_MASK          _AC(0x00780000, UL)
-#define IOF1_PWM2_MASK          _AC(0x00003C00, UL)
-
-// Interrupt numbers
-#define INT_RESERVED 0
-#define INT_WDOGCMP 1
-#define INT_RTCCMP 2
-#define INT_UART0_BASE 3
-#define INT_UART1_BASE 4
-#define INT_SPI0_BASE 5
-#define INT_SPI1_BASE 6
-#define INT_SPI2_BASE 7
-#define INT_GPIO_BASE 8
-#define INT_PWM0_BASE 40
-#define INT_PWM1_BASE 44
-#define INT_PWM2_BASE 48
-
-// Helper functions
-#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
-#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
-#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
-#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
-#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
-#define OTP_REG(offset)  _REG32(OTP_BASE_ADDR, offset)
-#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
-#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
-#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
-#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
-#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
-#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
-#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
-#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
-#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
-#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
-
-// Misc
-
-#include <stdint.h>
-
-void init_pll(void);
-unsigned long get_cpu_freq(void);
-unsigned long get_timer_freq(void);
-uint64_t get_timer_value(void);
-
-#endif /* _ISS_PLATFORM_H */

env/tgc_vp

@@ -0,0 +1 @@
+moonlight/

env/trap.c

@@ -0,0 +1,60 @@
+#include <math.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "encoding.h"
+
+#if defined(SEMIHOSTING)
+#define EBREAK_OPCODE 0x00100073
+#define EBREAK_MCAUSE 0x00000003
+
+#define SLLI_X0_X0_0X1F_OPCODE 0x01f01013
+#define SRAI_X0_X0_0X07_OPCODE 0x40705013
+
+int sh_missing_host = 0;
+
+void trap() { // ToDo: Check why macro CSR_MEPC and others are not
+              // resolved
+  uint32_t mepc = read_csr(0x341);   // Address of trap
+  uint32_t mtval = read_csr(0x343);  // Instruction value of trap
+  uint32_t mcause = read_csr(0x342); // Reason for the trap
+
+  if (mcause == EBREAK_MCAUSE && mtval == EBREAK_OPCODE) {
+    // This trap was caused by an EBREAK...
+
+    int aligned = ((mepc - 4) & 0x0f) == 0;
+    if (aligned && *(uint32_t *)mepc == EBREAK_OPCODE &&
+        *(uint32_t *)(mepc - 4) == SLLI_X0_X0_0X1F_OPCODE &&
+        *(uint32_t *)(mepc + 4) == SRAI_X0_X0_0X07_OPCODE) {
+      // The EBREAK was part of the semihosting call. (See semihosting.c)
+      //
+      // If a debugger were connected, this would have resulted in a CPU halt,
+      // and the debugger would have serviced the the semihosting call.
+      //
+      // However, the semihosting function was called without a debugger being
+      // attached. The best course of action is to simply return from the trap
+      // and let the semihosting function continue after the call to EBREAK to
+      // prevent the CPU from hanging in the trap handler.
+      write_csr(mepc, mepc + 4);
+
+      // Set a global variable to tell the semihosting code the the semihosting
+      // call
+      // didn't execute on the host.
+      sh_missing_host = 1;
+
+      return;
+    }
+
+    // EBREAK was not part of a semihosting call. This should not have happened.
+    // Hang forever.
+    while (1)
+      ;
+  }
+
+  // Trap was issued for another reason than an EBREAK.
+  // Replace the code below with whatever trap handler you'd normally use. (e.g.
+  // interrupt processing.)
+  while (1)
+    ;
+}
+#endif

include/bits.h

@@ -32,4 +32,15 @@
 #endif
 #define REGBYTES (1 << LOG_REGBYTES)
 
+#ifdef __ASSEMBLER__
+#define _AC(X,Y)        X
+#define _AT(T,X)        X
+#else
+#define _AC(X,Y)        (X##Y)
+#define _AT(T,X)        ((T)(X))
+#endif /* !__ASSEMBLER__*/
+
+#define _BITUL(x)       (_AC(1,UL) << (x))
+#define _BITULL(x)      (_AC(1,ULL) << (x))
+
 #endif

include/minres/devices/aclint.h

@@ -0,0 +1,29 @@
+#ifndef _DEVICES_ACLINT_H
+#define _DEVICES_ACLINT_H
+
+#include <stdint.h>
+#include "gen/aclint.h"
+
+
+static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value){
+    set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
+    set_aclint_mtime_lo(reg, (uint32_t)value);
+}
+
+static uint64_t get_aclint_mtime(volatile aclint_t* reg){
+    uint64_t value = ((uint64_t)get_aclint_mtime_hi(reg) << 32) | (uint64_t)get_aclint_mtime_lo(reg);
+    return value;
+}
+
+static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value){
+    set_aclint_mtimecmp0lo(reg, (uint32_t)0xFFFFFFFF);
+    set_aclint_mtimecmp0hi(reg, (uint32_t)(value >> 32));
+    set_aclint_mtimecmp0lo(reg, (uint32_t)value);
+}
+
+static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg){
+    uint64_t value = ((uint64_t)get_aclint_mtimecmp0hi(reg) << 32) | (uint64_t)get_aclint_mtimecmp0lo(reg);
+    return value;
+}
+
+#endif /* _DEVICES_ACLINT_H */

include/minres/devices/camera.h

@@ -0,0 +1,6 @@
+#ifndef _DEVICES_CAM_H
+#define _DEVICES_CAM_H
+
+#include "gen/camera.h"
+
+#endif /* _DEVICES_CAM_H */

include/minres/devices/dma.h

@@ -0,0 +1,11 @@
+#ifndef _DEVICES_DMA_H
+#define _DEVICES_DMA_H
+
+#include "gen/dma.h"
+
+#define EVENT_UART 1
+#define I2S_LEFT_SAMPLE_AVAIL 2
+#define I2S_RIGHT_SAMPLE_AVAIL 4
+#define CAMERA_PIXEL_AVAIL 8
+
+#endif /* _BSP_DMA_H */

include/minres/devices/fki_cluster_info.h

@@ -0,0 +1,388 @@
+#ifndef _FKI_CLUSTER_INFO_H
+#define _FKI_CLUSTER_INFO_H
+
+
+static uint8_t fki_ccc(uint8_t cluster);
+static uint8_t fki_dma(uint8_t cluster);
+static uint8_t fki_axi2stream(uint8_t cluster);
+static uint8_t fki_stream2axi(uint8_t cluster);
+static uint8_t fki_dma_adapter(uint8_t cluster);
+static inline uint32_t fki_addr_ccc_peMapping(uint8_t cluster);
+static inline uint32_t fki_addr_sram1(uint8_t cluster);
+static inline uint32_t fki_addr_sram2(uint8_t cluster);
+static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster);
+static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster);
+static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster);
+static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster);
+static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster);
+static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster);
+static inline uint32_t fki_addr_ccc_configMem(uint8_t cluster);
+static inline uint32_t fki_addr_aes_adapter(uint8_t cluster);
+static inline uint32_t fki_addr_ut_adapter(uint8_t cluster);
+static inline uint32_t fki_addr_sram0(uint8_t cluster);
+static inline uint32_t fki_addr_sram3(uint8_t cluster);
+
+#define Compute0 2
+#define Compute0_ccc 2,0
+#define Compute0_stream2axi 2,1
+#define Compute0_axi2stream 2,2
+#define Compute0_dma 2,4
+#define Compute0_dma_adapter 2,5
+#define ADDR_Compute0_ccc_idxJobs 0x80004000
+#define BYTES_Compute0_ccc_idxJobs 4096
+#define HIGH_Compute0_ccc_idxJobs 0x80004fff
+#define ADDR_Compute0_ccc_idxTasks 0x80005000
+#define BYTES_Compute0_ccc_idxTasks 4096
+#define HIGH_Compute0_ccc_idxTasks 0x80005fff
+#define ADDR_Compute0_ccc_configMem 0x80000000
+#define BYTES_Compute0_ccc_configMem 16384
+#define HIGH_Compute0_ccc_configMem 0x80003fff
+#define ADDR_Compute0_ccc_peMapping 0x80006000
+#define BYTES_Compute0_ccc_peMapping 4096
+#define HIGH_Compute0_ccc_peMapping 0x80006fff
+#define ADDR_Compute0_aes_adapter 0x80007000
+#define BYTES_Compute0_aes_adapter 4096
+#define HIGH_Compute0_aes_adapter 0x80007fff
+#define ADDR_Compute0_cntrl_cva5_clusterReg 0x8000a000
+#define BYTES_Compute0_cntrl_cva5_clusterReg 4096
+#define HIGH_Compute0_cntrl_cva5_clusterReg 0x8000afff
+#define ADDR_Compute0_cntrl_cva5 0x80008000
+#define BYTES_Compute0_cntrl_cva5 8192
+#define HIGH_Compute0_cntrl_cva5 0x80009fff
+#define ADDR_Compute0_cntrl_tgc_clusterReg 0x8000d000
+#define BYTES_Compute0_cntrl_tgc_clusterReg 4096
+#define HIGH_Compute0_cntrl_tgc_clusterReg 0x8000dfff
+#define ADDR_Compute0_cntrl_tgc 0x8000b000
+#define BYTES_Compute0_cntrl_tgc 8192
+#define HIGH_Compute0_cntrl_tgc 0x8000cfff
+#define ADDR_Compute0_ut_adapter 0x8000e000
+#define BYTES_Compute0_ut_adapter 8192
+#define HIGH_Compute0_ut_adapter 0x8000ffff
+#define ADDR_Compute0_sram0 0x80010000
+#define BYTES_Compute0_sram0 524288
+#define HIGH_Compute0_sram0 0x8008ffff
+#define ADDR_Compute0_sram1 0x80090000
+#define BYTES_Compute0_sram1 262144
+#define HIGH_Compute0_sram1 0x800cffff
+#define ADDR_Compute0_sram2 0x800d0000
+#define BYTES_Compute0_sram2 262144
+#define HIGH_Compute0_sram2 0x8010ffff
+#define ADDR_Compute0_sram3 0x80110000
+#define BYTES_Compute0_sram3 262144
+#define HIGH_Compute0_sram3 0x8014ffff
+#define Compute1 3
+#define Compute1_ccc 3,0
+#define Compute1_stream2axi 3,1
+#define Compute1_axi2stream 3,2
+#define Compute1_dma 3,4
+#define Compute1_dma_adapter 3,5
+#define ADDR_Compute1_ccc_idxJobs 0x90004000
+#define BYTES_Compute1_ccc_idxJobs 4096
+#define HIGH_Compute1_ccc_idxJobs 0x90004fff
+#define ADDR_Compute1_ccc_idxTasks 0x90005000
+#define BYTES_Compute1_ccc_idxTasks 4096
+#define HIGH_Compute1_ccc_idxTasks 0x90005fff
+#define ADDR_Compute1_ccc_configMem 0x90000000
+#define BYTES_Compute1_ccc_configMem 16384
+#define HIGH_Compute1_ccc_configMem 0x90003fff
+#define ADDR_Compute1_ccc_peMapping 0x90006000
+#define BYTES_Compute1_ccc_peMapping 4096
+#define HIGH_Compute1_ccc_peMapping 0x90006fff
+#define ADDR_Compute1_aes_adapter 0x90007000
+#define BYTES_Compute1_aes_adapter 4096
+#define HIGH_Compute1_aes_adapter 0x90007fff
+#define ADDR_Compute1_cntrl_cva5_clusterReg 0x8000a000
+#define BYTES_Compute1_cntrl_cva5_clusterReg 4096
+#define HIGH_Compute1_cntrl_cva5_clusterReg 0x8000afff
+#define ADDR_Compute1_cntrl_cva5 0x90008000
+#define BYTES_Compute1_cntrl_cva5 12288
+#define HIGH_Compute1_cntrl_cva5 0x9000afff
+#define ADDR_Compute1_cntrl_tgc_clusterReg 0x8000d000
+#define BYTES_Compute1_cntrl_tgc_clusterReg 4096
+#define HIGH_Compute1_cntrl_tgc_clusterReg 0x8000dfff
+#define ADDR_Compute1_cntrl_tgc 0x9000b000
+#define BYTES_Compute1_cntrl_tgc 12288
+#define HIGH_Compute1_cntrl_tgc 0x9000dfff
+#define ADDR_Compute1_ut_adapter 0x9000e000
+#define BYTES_Compute1_ut_adapter 8192
+#define HIGH_Compute1_ut_adapter 0x9000ffff
+#define ADDR_Compute1_sram0 0x90010000
+#define BYTES_Compute1_sram0 524288
+#define HIGH_Compute1_sram0 0x9008ffff
+#define ADDR_Compute1_sram1 0x90090000
+#define BYTES_Compute1_sram1 262144
+#define HIGH_Compute1_sram1 0x900cffff
+#define ADDR_Compute1_sram2 0x900d0000
+#define BYTES_Compute1_sram2 262144
+#define HIGH_Compute1_sram2 0x9010ffff
+#define ADDR_Compute1_sram3 0x90110000
+#define BYTES_Compute1_sram3 262144
+#define HIGH_Compute1_sram3 0x9014ffff
+
+static uint8_t fki_ccc(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0;
+		}
+		case 3: {
+			return 0;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_dma(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 4;
+		}
+		case 2: {
+			return 4;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_axi2stream(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 2;
+		}
+		case 2: {
+			return 2;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_stream2axi(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 1;
+		}
+		case 2: {
+			return 1;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_dma_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 5;
+		}
+		case 3: {
+			return 5;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ccc_peMapping(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80006000;
+		}
+		case 3: {
+			return 0x90006000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_sram1(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x90090000;
+		}
+		case 2: {
+			return 0x80090000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_sram2(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x800d0000;
+		}
+		case 3: {
+			return 0x900d0000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80008000;
+		}
+		case 3: {
+			return 0x90008000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8000b000;
+		}
+		case 3: {
+			return 0x9000b000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80005000;
+		}
+		case 3: {
+			return 0x90005000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x8000d000;
+		}
+		case 2: {
+			return 0x8000d000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80004000;
+		}
+		case 3: {
+			return 0x90004000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8000a000;
+		}
+		case 3: {
+			return 0x8000a000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ccc_configMem(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x90000000;
+		}
+		case 2: {
+			return 0x80000000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_aes_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80007000;
+		}
+		case 3: {
+			return 0x90007000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ut_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x9000e000;
+		}
+		case 2: {
+			return 0x8000e000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_sram0(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80010000;
+		}
+		case 3: {
+			return 0x90010000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_sram3(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80110000;
+		}
+		case 3: {
+			return 0x90110000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+#endif //_FKI_CLUSTER_INFO_H

include/minres/devices/flexki_messages.h

@@ -0,0 +1,77 @@
+#ifndef _FLEXKI_MESSAGES_H
+#define _FLEXKI_MESSAGES_H
+
+#include "fki_cluster_info.h"
+
+#include <stdbool.h>
+
+static void send_msg(uint32_t cluster, uint32_t component, uint32_t msg_len, uint32_t msg_id, uint32_t* words) {
+    set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(msgif, component);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(msgif, cluster);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(msgif, msg_len);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(msgif, msg_id);
+    for (uint32_t i = 0; i < msg_len; i = i + 1) {
+        switch (i) {
+            case 0:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(msgif, words[i]);
+                break;
+            case 1:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(msgif, words[i]);
+                break;
+            case 2:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(msgif, words[i]);
+                break;
+            case 3:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(msgif, words[i]);
+                break;
+            case 4:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(msgif, words[i]);
+                break;
+            case 5:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(msgif, words[i]);
+                break;
+            case 6:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(msgif, words[i]);
+                break;
+            case 7:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(msgif, words[i]);
+                break;
+            default:
+                break;
+        }
+    }
+    set_mkcontrolclusterstreamcontroller_REG_SEND(msgif, 1);
+}
+
+static uint32_t check_response(void) {
+    while (true) {
+        if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
+            return get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif);
+        }
+    }
+}
+
+static uint32_t wait_response(uint32_t msg_id) {
+    while (true) {
+        if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
+            if (get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif) == msg_id) {
+                break;
+            }
+        }
+    }
+	uint32_t response_payload = get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(msgif);
+	set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(msgif, 1);
+	return response_payload;
+}
+
+static void fki_dma_transfer(uint32_t cluster, uint32_t msg_id, uint32_t srcAddr, uint32_t destAddr, uint32_t bytes) {
+    uint32_t values[] = {
+        0,
+        srcAddr,
+        destAddr,
+        bytes
+    };
+    send_msg(cluster, fki_dma(cluster), 4, msg_id, values);
+}
+
+#endif /* _FLEXKI_MESSAGES_H */

include/minres/devices/gen/aclint.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2024-08-02 08:46:07 UTC
+ * by peakrdl_mnrs version 1.2.7
+ */
+
+#ifndef _BSP_ACLINT_H
+#define _BSP_ACLINT_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t MSIP0;
+  uint8_t fill0[16380];
+  volatile uint32_t MTIMECMP0LO;
+  volatile uint32_t MTIMECMP0HI;
+  uint8_t fill1[32752];
+  volatile uint32_t MTIME_LO;
+  volatile uint32_t MTIME_HI;
+} aclint_t;
+
+#define ACLINT_MSIP0_OFFS 0
+#define ACLINT_MSIP0_MASK 0x1
+#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
+
+#define ACLINT_MTIMECMP0LO_OFFS 0
+#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
+#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
+
+#define ACLINT_MTIMECMP0HI_OFFS 0
+#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
+#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
+
+#define ACLINT_MTIME_LO_OFFS 0
+#define ACLINT_MTIME_LO_MASK 0xffffffff
+#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
+
+#define ACLINT_MTIME_HI_OFFS 0
+#define ACLINT_MTIME_HI_MASK 0xffffffff
+#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
+
+// ACLINT_MSIP0
+static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; }
+static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; }
+static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; }
+static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); }
+
+// ACLINT_MTIMECMP0LO
+static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; }
+static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
+  reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// ACLINT_MTIMECMP0HI
+static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; }
+static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
+  reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// ACLINT_MTIME_LO
+static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
+static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
+  reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// ACLINT_MTIME_HI
+static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
+static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
+  reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_ACLINT_H */

include/minres/devices/gen/apb3spi.h

@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2025-02-17 15:56:47 UTC
+ * by peakrdl_mnrs version 1.2.9
+ */
+
+#ifndef _BSP_APB3SPI_H
+#define _BSP_APB3SPI_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t DATA;
+  volatile uint32_t STATUS;
+  volatile uint32_t CONFIG;
+  volatile uint32_t INTR;
+  uint8_t fill0[16];
+  volatile uint32_t SCLK_CONFIG;
+  volatile uint32_t SSGEN_SETUP;
+  volatile uint32_t SSGEN_HOLD;
+  volatile uint32_t SSGEN_DISABLE;
+  volatile uint32_t SSGEN_ACTIVE_HIGH;
+  uint8_t fill1[12];
+  volatile uint32_t XIP_ENABLE;
+  volatile uint32_t XIP_CONFIG;
+  volatile uint32_t XIP_MODE;
+  uint8_t fill2[4];
+  volatile uint32_t XIP_WRITE;
+  volatile uint32_t XIP_READ_WRITE;
+  volatile uint32_t XIP_READ;
+} apb3spi_t;
+
+#define APB3SPI_DATA_DATA_OFFS 0
+#define APB3SPI_DATA_DATA_MASK 0xff
+#define APB3SPI_DATA_DATA(V) ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS)
+
+#define APB3SPI_DATA_WRITE_OFFS 8
+#define APB3SPI_DATA_WRITE_MASK 0x1
+#define APB3SPI_DATA_WRITE(V) ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS)
+
+#define APB3SPI_DATA_READ_OFFS 9
+#define APB3SPI_DATA_READ_MASK 0x1
+#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
+
+#define APB3SPI_DATA_SSGEN_OFFS 11
+#define APB3SPI_DATA_SSGEN_MASK 0x1
+#define APB3SPI_DATA_SSGEN(V) ((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS)
+
+#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
+#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
+#define APB3SPI_DATA_RX_DATA_INVALID(V) ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS)
+
+#define APB3SPI_STATUS_TX_FREE_OFFS 0
+#define APB3SPI_STATUS_TX_FREE_MASK 0x3f
+#define APB3SPI_STATUS_TX_FREE(V) ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS)
+
+#define APB3SPI_STATUS_RX_AVAIL_OFFS 16
+#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f
+#define APB3SPI_STATUS_RX_AVAIL(V) ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS)
+
+#define APB3SPI_CONFIG_KIND_OFFS 0
+#define APB3SPI_CONFIG_KIND_MASK 0x3
+#define APB3SPI_CONFIG_KIND(V) ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS)
+
+#define APB3SPI_CONFIG_MODE_OFFS 4
+#define APB3SPI_CONFIG_MODE_MASK 0x3
+#define APB3SPI_CONFIG_MODE(V) ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS)
+
+#define APB3SPI_INTR_TX_IE_OFFS 0
+#define APB3SPI_INTR_TX_IE_MASK 0x1
+#define APB3SPI_INTR_TX_IE(V) ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS)
+
+#define APB3SPI_INTR_RX_IE_OFFS 1
+#define APB3SPI_INTR_RX_IE_MASK 0x1
+#define APB3SPI_INTR_RX_IE(V) ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS)
+
+#define APB3SPI_INTR_TX_IP_OFFS 8
+#define APB3SPI_INTR_TX_IP_MASK 0x1
+#define APB3SPI_INTR_TX_IP(V) ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS)
+
+#define APB3SPI_INTR_RX_IP_OFFS 9
+#define APB3SPI_INTR_RX_IP_MASK 0x1
+#define APB3SPI_INTR_RX_IP(V) ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS)
+
+#define APB3SPI_INTR_TX_ACTIVE_OFFS 16
+#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1
+#define APB3SPI_INTR_TX_ACTIVE(V) ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS)
+
+#define APB3SPI_SCLK_CONFIG_OFFS 0
+#define APB3SPI_SCLK_CONFIG_MASK 0xfff
+#define APB3SPI_SCLK_CONFIG(V) ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS)
+
+#define APB3SPI_SSGEN_SETUP_OFFS 0
+#define APB3SPI_SSGEN_SETUP_MASK 0xfff
+#define APB3SPI_SSGEN_SETUP(V) ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS)
+
+#define APB3SPI_SSGEN_HOLD_OFFS 0
+#define APB3SPI_SSGEN_HOLD_MASK 0xfff
+#define APB3SPI_SSGEN_HOLD(V) ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS)
+
+#define APB3SPI_SSGEN_DISABLE_OFFS 0
+#define APB3SPI_SSGEN_DISABLE_MASK 0xfff
+#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
+
+#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
+#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
+#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
+
+#define APB3SPI_XIP_ENABLE_OFFS 0
+#define APB3SPI_XIP_ENABLE_MASK 0x1
+#define APB3SPI_XIP_ENABLE(V) ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
+#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
+#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS)
+
+#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8
+#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1
+#define APB3SPI_XIP_CONFIG_ENABLE(V) ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
+
+#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0
+#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3
+#define APB3SPI_XIP_MODE_INSTRUCTION(V) ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS)
+
+#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8
+#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3
+#define APB3SPI_XIP_MODE_ADDRESS(V) ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS)
+
+#define APB3SPI_XIP_MODE_DUMMY_OFFS 16
+#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3
+#define APB3SPI_XIP_MODE_DUMMY(V) ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS)
+
+#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24
+#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3
+#define APB3SPI_XIP_MODE_PAYLOAD(V) ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS)
+
+#define APB3SPI_XIP_WRITE_OFFS 0
+#define APB3SPI_XIP_WRITE_MASK 0xff
+#define APB3SPI_XIP_WRITE(V) ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS)
+
+#define APB3SPI_XIP_READ_WRITE_OFFS 0
+#define APB3SPI_XIP_READ_WRITE_MASK 0xff
+#define APB3SPI_XIP_READ_WRITE(V) ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS)
+
+#define APB3SPI_XIP_READ_OFFS 0
+#define APB3SPI_XIP_READ_MASK 0xff
+#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
+
+// APB3SPI_DATA
+static inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg) { return reg->DATA; }
+static inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value) { reg->DATA = value; }
+static inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); }
+static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg) { return (reg->DATA >> 8) & 0x1; }
+static inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); }
+static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg) { return (reg->DATA >> 9) & 0x1; }
+static inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); }
+static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg) { return (reg->DATA >> 11) & 0x1; }
+static inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value) {
+  reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
+}
+static inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg) { return (reg->DATA >> 31) & 0x1; }
+
+// APB3SPI_STATUS
+static inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg) { return reg->STATUS; }
+static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg) { return (reg->STATUS >> 0) & 0x3f; }
+static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg) { return (reg->STATUS >> 16) & 0x3f; }
+
+// APB3SPI_CONFIG
+static inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg) { return reg->CONFIG; }
+static inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value) { reg->CONFIG = value; }
+static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
+static inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
+}
+static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
+static inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
+}
+
+// APB3SPI_INTR
+static inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg) { return reg->INTR; }
+static inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value) { reg->INTR = value; }
+static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 0) & 0x1; }
+static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); }
+static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 1) & 0x1; }
+static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); }
+static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 8) & 0x1; }
+static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8); }
+static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 9) & 0x1; }
+static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9); }
+static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg) { return (reg->INTR >> 16) & 0x1; }
+
+// APB3SPI_SCLK_CONFIG
+static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg) { return reg->SCLK_CONFIG; }
+static inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value) { reg->SCLK_CONFIG = value; }
+static inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg) { return (reg->SCLK_CONFIG >> 0) & 0xfff; }
+static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value) {
+  reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
+}
+
+// APB3SPI_SSGEN_SETUP
+static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg) { return reg->SSGEN_SETUP; }
+static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_SETUP = value; }
+static inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_SETUP >> 0) & 0xfff; }
+static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value) {
+  reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
+}
+
+// APB3SPI_SSGEN_HOLD
+static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg) { return reg->SSGEN_HOLD; }
+static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_HOLD = value; }
+static inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_HOLD >> 0) & 0xfff; }
+static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value) {
+  reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
+}
+
+// APB3SPI_SSGEN_DISABLE
+static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg) { return reg->SSGEN_DISABLE; }
+static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_DISABLE = value; }
+static inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_DISABLE >> 0) & 0xfff; }
+static inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value) {
+  reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
+}
+
+// APB3SPI_SSGEN_ACTIVE_HIGH
+static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg) { return reg->SSGEN_ACTIVE_HIGH; }
+static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_ACTIVE_HIGH = value; }
+static inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg) {
+  return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
+}
+static inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value) {
+  reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
+}
+
+// APB3SPI_XIP_ENABLE
+static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg) { return reg->XIP_ENABLE; }
+static inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_ENABLE = value; }
+static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg) { return (reg->XIP_ENABLE >> 0) & 0x1; }
+static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
+}
+
+// APB3SPI_XIP_CONFIG
+static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg) { return reg->XIP_CONFIG; }
+static inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_CONFIG = value; }
+static inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 0) & 0xff; }
+static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
+}
+static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 8) & 0x1; }
+static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
+}
+static inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 16) & 0xff; }
+static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
+}
+static inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 24) & 0xf; }
+static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
+}
+
+// APB3SPI_XIP_MODE
+static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg) { return reg->XIP_MODE; }
+static inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_MODE = value; }
+static inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 0) & 0x3; }
+static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
+}
+static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 8) & 0x3; }
+static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
+}
+static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 16) & 0x3; }
+static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
+}
+static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 24) & 0x3; }
+static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
+}
+
+// APB3SPI_XIP_WRITE
+static inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_WRITE = value; }
+static inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+
+// APB3SPI_XIP_READ_WRITE
+static inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_READ_WRITE = value; }
+static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value) {
+  reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+
+// APB3SPI_XIP_READ
+static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg) { return reg->XIP_READ; }
+static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg) { return (reg->XIP_READ >> 0) & 0xff; }
+
+#endif /* _BSP_APB3SPI_H */

include/minres/devices/gen/camera.h

@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2025-02-28 17:25:03 UTC
+ * by peakrdl_mnrs version 1.2.9
+ */
+
+#ifndef _BSP_CAMERA_H
+#define _BSP_CAMERA_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t PIXEL;
+  volatile uint32_t CONFIG;
+  volatile uint32_t CONFIG2;
+  volatile uint32_t DATA_SIZE;
+  volatile uint32_t START;
+  volatile uint32_t STATUS;
+  volatile uint32_t CAMERA_CLOCK_CTRL;
+  volatile uint32_t IE;
+  volatile uint32_t IP;
+} camera_t;
+
+#define CAMERA_PIXEL_OFFS 0
+#define CAMERA_PIXEL_MASK 0xffffffff
+#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
+
+#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0
+#define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3
+#define CAMERA_CONFIG_OUTPUT_CURR(V) ((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS)
+
+#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2
+#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
+#define CAMERA_CONFIG_OFFSET_RAMP(V) ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
+
+#define CAMERA_CONFIG_RAMP_GAIN_OFFS 4
+#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
+#define CAMERA_CONFIG_RAMP_GAIN(V) ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
+
+#define CAMERA_CONFIG_VRST_PIX_OFFS 6
+#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
+#define CAMERA_CONFIG_VRST_PIX(V) ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
+
+#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8
+#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
+#define CAMERA_CONFIG_ROWS_IN_RESET(V) ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
+
+#define CAMERA_CONFIG_HIGH_SPEED_OFFS 16
+#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
+#define CAMERA_CONFIG_HIGH_SPEED(V) ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
+
+#define CAMERA_CONFIG_IDLE_MODE_OFFS 17
+#define CAMERA_CONFIG_IDLE_MODE_MASK 0x1
+#define CAMERA_CONFIG_IDLE_MODE(V) ((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS)
+
+#define CAMERA_CONFIG_CVC_CURR_OFFS 18
+#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
+#define CAMERA_CONFIG_CVC_CURR(V) ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
+
+#define CAMERA_CONFIG_VREF_OFFS 20
+#define CAMERA_CONFIG_VREF_MASK 0x3
+#define CAMERA_CONFIG_VREF(V) ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
+
+#define CAMERA_CONFIG_MCLK_MODE_OFFS 22
+#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
+#define CAMERA_CONFIG_MCLK_MODE(V) ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
+
+#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24
+#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
+#define CAMERA_CONFIG_OUTPUT_MODE(V) ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
+
+#define CAMERA_CONFIG_CDS_GAIN_OFFS 25
+#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
+#define CAMERA_CONFIG_CDS_GAIN(V) ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
+
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
+
+#define CAMERA_CONFIG_ROWS_DELAY_OFFS 27
+#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
+#define CAMERA_CONFIG_ROWS_DELAY(V) ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
+
+#define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0
+#define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1
+#define CAMERA_CONFIG2_AUTO_IDLE(V) ((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS)
+
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) ((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) << CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS)
+
+#define CAMERA_DATA_SIZE_OFFS 0
+#define CAMERA_DATA_SIZE_MASK 0x3
+#define CAMERA_DATA_SIZE(V) ((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS)
+
+#define CAMERA_START_OFFS 0
+#define CAMERA_START_MASK 0x1
+#define CAMERA_START(V) ((V & CAMERA_START_MASK) << CAMERA_START_OFFS)
+
+#define CAMERA_STATUS_OFFS 0
+#define CAMERA_STATUS_MASK 0x1
+#define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
+
+#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
+#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff
+#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
+
+#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
+#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1
+#define CAMERA_IE_EN_PIXEL_AVAIL(V) ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS)
+
+#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1
+#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1
+#define CAMERA_IE_EN_FRAME_FINISHED(V) ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS)
+
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS)
+
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
+
+// CAMERA_PIXEL
+static inline uint32_t get_camera_pixel(volatile camera_t* reg) { return (reg->PIXEL >> 0) & 0xffffffff; }
+static inline void set_camera_pixel(volatile camera_t* reg, uint32_t value) {
+  reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// CAMERA_CONFIG
+static inline uint32_t get_camera_config(volatile camera_t* reg) { return reg->CONFIG; }
+static inline void set_camera_config(volatile camera_t* reg, uint32_t value) { reg->CONFIG = value; }
+static inline uint32_t get_camera_config_output_curr(volatile camera_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
+static inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
+}
+static inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg) { return (reg->CONFIG >> 2) & 0x3; }
+static inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
+}
+static inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
+static inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
+}
+static inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg) { return (reg->CONFIG >> 6) & 0x3; }
+static inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
+}
+static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg) { return (reg->CONFIG >> 8) & 0xff; }
+static inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
+}
+static inline uint32_t get_camera_config_high_speed(volatile camera_t* reg) { return (reg->CONFIG >> 16) & 0x1; }
+static inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
+}
+static inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg) { return (reg->CONFIG >> 17) & 0x1; }
+static inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
+}
+static inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg) { return (reg->CONFIG >> 18) & 0x3; }
+static inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
+}
+static inline uint32_t get_camera_config_vref(volatile camera_t* reg) { return (reg->CONFIG >> 20) & 0x3; }
+static inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
+}
+static inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg) { return (reg->CONFIG >> 22) & 0x3; }
+static inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
+}
+static inline uint32_t get_camera_config_output_mode(volatile camera_t* reg) { return (reg->CONFIG >> 24) & 0x1; }
+static inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
+}
+static inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg) { return (reg->CONFIG >> 25) & 0x1; }
+static inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
+}
+static inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg) { return (reg->CONFIG >> 26) & 0x1; }
+static inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
+}
+static inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg) { return (reg->CONFIG >> 27) & 0x1f; }
+static inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
+}
+
+// CAMERA_CONFIG2
+static inline uint32_t get_camera_config2(volatile camera_t* reg) { return reg->CONFIG2; }
+static inline void set_camera_config2(volatile camera_t* reg, uint32_t value) { reg->CONFIG2 = value; }
+static inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg) { return (reg->CONFIG2 >> 0) & 0x1; }
+static inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg) { return (reg->CONFIG2 >> 1) & 0x1; }
+static inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value) {
+  reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
+}
+
+// CAMERA_DATA_SIZE
+static inline uint32_t get_camera_data_size(volatile camera_t* reg) { return reg->DATA_SIZE; }
+static inline void set_camera_data_size(volatile camera_t* reg, uint32_t value) { reg->DATA_SIZE = value; }
+static inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg) { return (reg->DATA_SIZE >> 0) & 0x3; }
+static inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value) {
+  reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
+}
+
+// CAMERA_START
+static inline uint32_t get_camera_start(volatile camera_t* reg) { return reg->START; }
+static inline void set_camera_start(volatile camera_t* reg, uint32_t value) { reg->START = value; }
+static inline uint32_t get_camera_start_start(volatile camera_t* reg) { return (reg->START >> 0) & 0x1; }
+static inline void set_camera_start_start(volatile camera_t* reg, uint8_t value) {
+  reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
+}
+
+// CAMERA_STATUS
+static inline uint32_t get_camera_status(volatile camera_t* reg) { return reg->STATUS; }
+static inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg) { return (reg->STATUS >> 0) & 0x1; }
+
+// CAMERA_CAMERA_CLOCK_CTRL
+static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg) { return reg->CAMERA_CLOCK_CTRL; }
+static inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value) { reg->CAMERA_CLOCK_CTRL = value; }
+static inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg) { return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff; }
+static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value) {
+  reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
+}
+
+// CAMERA_IE
+static inline uint32_t get_camera_ie(volatile camera_t* reg) { return reg->IE; }
+static inline void set_camera_ie(volatile camera_t* reg, uint32_t value) { reg->IE = value; }
+static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg) { return (reg->IE >> 0) & 0x1; }
+static inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value) {
+  reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg) { return (reg->IE >> 1) & 0x1; }
+static inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value) {
+  reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+
+// CAMERA_IP
+static inline uint32_t get_camera_ip(volatile camera_t* reg) { return reg->IP; }
+static inline void set_camera_ip(volatile camera_t* reg, uint32_t value) { reg->IP = value; }
+static inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg) { return (reg->IP >> 0) & 0x1; }
+static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value) {
+  reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg) { return (reg->IP >> 1) & 0x1; }
+static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value) {
+  reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
+}
+
+#endif /* _BSP_CAMERA_H */

include/minres/devices/gen/dma.h

@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2024-08-02 08:46:07 UTC
+ * by peakrdl_mnrs version 1.2.7
+ */
+
+#ifndef _BSP_DMA_H
+#define _BSP_DMA_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t CONTROL;
+  volatile uint32_t STATUS;
+  volatile uint32_t IE;
+  volatile uint32_t IP;
+  volatile uint32_t CH0_EVENT;
+  volatile uint32_t CH0_TRANSFER;
+  volatile uint32_t CH0_SRC_START_ADDR;
+  volatile uint32_t CH0_SRC_ADDR_INC;
+  volatile uint32_t CH0_DST_START_ADDR;
+  volatile uint32_t CH0_DST_ADDR_INC;
+  volatile uint32_t CH1_EVENT;
+  volatile uint32_t CH1_TRANSFER;
+  volatile uint32_t CH1_SRC_START_ADDR;
+  volatile uint32_t CH1_SRC_ADDR_INC;
+  volatile uint32_t CH1_DST_START_ADDR;
+  volatile uint32_t CH1_DST_ADDR_INC;
+} dma_t;
+
+#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
+#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
+#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
+
+#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
+#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
+#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
+
+#define DMA_STATUS_CH0_BUSY_OFFS 0
+#define DMA_STATUS_CH0_BUSY_MASK 0x1
+#define DMA_STATUS_CH0_BUSY(V) ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)
+
+#define DMA_STATUS_CH1_BUSY_OFFS 1
+#define DMA_STATUS_CH1_BUSY_MASK 0x1
+#define DMA_STATUS_CH1_BUSY(V) ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)
+
+#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
+#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
+#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
+
+#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
+#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
+#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
+#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
+#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
+#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
+#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
+
+#define DMA_CH0_EVENT_SELECT_OFFS 0
+#define DMA_CH0_EVENT_SELECT_MASK 0x1f
+#define DMA_CH0_EVENT_SELECT(V) ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)
+
+#define DMA_CH0_EVENT_COMBINE_OFFS 31
+#define DMA_CH0_EVENT_COMBINE_MASK 0x1
+#define DMA_CH0_EVENT_COMBINE(V) ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)
+
+#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
+#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
+#define DMA_CH0_TRANSFER_WIDTH(V) ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)
+
+#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
+#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
+#define DMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
+
+#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
+#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
+#define DMA_CH0_TRANSFER_SEG_COUNT(V) ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)
+
+#define DMA_CH0_SRC_START_ADDR_OFFS 0
+#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
+#define DMA_CH0_SRC_START_ADDR(V) ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)
+
+#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
+#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
+#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
+
+#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
+#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
+#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
+
+#define DMA_CH0_DST_START_ADDR_OFFS 0
+#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
+#define DMA_CH0_DST_START_ADDR(V) ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)
+
+#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
+#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
+#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
+
+#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
+#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
+#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
+
+#define DMA_CH1_EVENT_SELECT_OFFS 0
+#define DMA_CH1_EVENT_SELECT_MASK 0x1f
+#define DMA_CH1_EVENT_SELECT(V) ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)
+
+#define DMA_CH1_EVENT_COMBINE_OFFS 31
+#define DMA_CH1_EVENT_COMBINE_MASK 0x1
+#define DMA_CH1_EVENT_COMBINE(V) ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)
+
+#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
+#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
+#define DMA_CH1_TRANSFER_WIDTH(V) ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)
+
+#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
+#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
+#define DMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
+
+#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
+#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
+#define DMA_CH1_TRANSFER_SEG_COUNT(V) ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)
+
+#define DMA_CH1_SRC_START_ADDR_OFFS 0
+#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
+#define DMA_CH1_SRC_START_ADDR(V) ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)
+
+#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
+#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
+#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
+
+#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
+#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
+#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
+
+#define DMA_CH1_DST_START_ADDR_OFFS 0
+#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
+#define DMA_CH1_DST_START_ADDR(V) ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)
+
+#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
+#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
+#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
+
+#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
+#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
+#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
+
+// DMA_CONTROL
+static inline uint32_t get_dma_control(volatile dma_t* reg) { return reg->CONTROL; }
+static inline void set_dma_control(volatile dma_t* reg, uint32_t value) { reg->CONTROL = value; }
+static inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 0) & 0x1; }
+static inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value) {
+  reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 1) & 0x1; }
+static inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value) {
+  reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
+}
+
+// DMA_STATUS
+static inline uint32_t get_dma_status(volatile dma_t* reg) { return reg->STATUS; }
+static inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg) { return (reg->STATUS >> 0) & 0x1; }
+static inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg) { return (reg->STATUS >> 1) & 0x1; }
+
+// DMA_IE
+static inline uint32_t get_dma_ie(volatile dma_t* reg) { return reg->IE; }
+static inline void set_dma_ie(volatile dma_t* reg, uint32_t value) { reg->IE = value; }
+static inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 0) & 0x1; }
+static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
+  reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 1) & 0x1; }
+static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
+  reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+static inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 2) & 0x1; }
+static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
+  reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
+}
+static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 3) & 0x1; }
+static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
+  reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
+}
+
+// DMA_IP
+static inline uint32_t get_dma_ip(volatile dma_t* reg) { return reg->IP; }
+static inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 0) & 0x1; }
+static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 1) & 0x1; }
+static inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 2) & 0x1; }
+static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 3) & 0x1; }
+
+// DMA_CH0_EVENT
+static inline uint32_t get_dma_ch0_event(volatile dma_t* reg) { return reg->CH0_EVENT; }
+static inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value) { reg->CH0_EVENT = value; }
+static inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg) { return (reg->CH0_EVENT >> 0) & 0x1f; }
+static inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value) {
+  reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg) { return (reg->CH0_EVENT >> 31) & 0x1; }
+static inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value) {
+  reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
+}
+
+// DMA_CH0_TRANSFER
+static inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg) { return reg->CH0_TRANSFER; }
+static inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = value; }
+static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 0) & 0x3; }
+static inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value) {
+  reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 2) & 0x3ff; }
+static inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
+  reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
+}
+static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 12) & 0xfffff; }
+static inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
+  reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
+}
+
+// DMA_CH0_SRC_START_ADDR
+static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg) { return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; }
+static inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value) {
+  reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// DMA_CH0_SRC_ADDR_INC
+static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg) { return reg->CH0_SRC_ADDR_INC; }
+static inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_SRC_ADDR_INC = value; }
+static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff; }
+static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
+  reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; }
+static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
+  reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+// DMA_CH0_DST_START_ADDR
+static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg) { return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; }
+static inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value) {
+  reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// DMA_CH0_DST_ADDR_INC
+static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg) { return reg->CH0_DST_ADDR_INC; }
+static inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_DST_ADDR_INC = value; }
+static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff; }
+static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
+  reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; }
+static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
+  reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+// DMA_CH1_EVENT
+static inline uint32_t get_dma_ch1_event(volatile dma_t* reg) { return reg->CH1_EVENT; }
+static inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value) { reg->CH1_EVENT = value; }
+static inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg) { return (reg->CH1_EVENT >> 0) & 0x1f; }
+static inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value) {
+  reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg) { return (reg->CH1_EVENT >> 31) & 0x1; }
+static inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value) {
+  reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
+}
+
+// DMA_CH1_TRANSFER
+static inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg) { return reg->CH1_TRANSFER; }
+static inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = value; }
+static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 0) & 0x3; }
+static inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value) {
+  reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 2) & 0x3ff; }
+static inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
+  reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
+}
+static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 12) & 0xfffff; }
+static inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
+  reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
+}
+
+// DMA_CH1_SRC_START_ADDR
+static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg) { return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; }
+static inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value) {
+  reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// DMA_CH1_SRC_ADDR_INC
+static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg) { return reg->CH1_SRC_ADDR_INC; }
+static inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_SRC_ADDR_INC = value; }
+static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff; }
+static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
+  reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; }
+static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
+  reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+// DMA_CH1_DST_START_ADDR
+static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg) { return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; }
+static inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value) {
+  reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// DMA_CH1_DST_ADDR_INC
+static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg) { return reg->CH1_DST_ADDR_INC; }
+static inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_DST_ADDR_INC = value; }
+static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff; }
+static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
+  reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+static inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; }
+static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
+  reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+#endif /* _BSP_DMA_H */

include/minres/devices/gen/gpio.h

@@ -0,0 +1,393 @@
+/*
+ * Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2024-12-06 09:43:24 UTC
+ * by peakrdl_mnrs version 1.2.9
+ */
+
+#ifndef _BSP_GPIO_H
+#define _BSP_GPIO_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t VALUE;
+  volatile uint32_t WRITE;
+  volatile uint32_t WRITEENABLE;
+  volatile uint32_t PULLUP;
+  volatile uint32_t PULDOWN;
+  volatile uint32_t DRIVESTRENGTH_0;
+  volatile uint32_t DRIVESTRENGTH_1;
+  volatile uint32_t DRIVESTRENGTH_2;
+  volatile uint32_t DRIVESTRENGTH_3;
+  volatile uint32_t IE;
+  volatile uint32_t IP;
+  volatile uint32_t IRQ_TRIGGER;
+  volatile uint32_t IRQ_TYPE;
+  volatile uint32_t BOOT_SEL;
+} gpio_t;
+
+#define GPIO_VALUE_OFFS 0
+#define GPIO_VALUE_MASK 0xffffffff
+#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
+
+#define GPIO_WRITE_OFFS 0
+#define GPIO_WRITE_MASK 0xffffffff
+#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
+
+#define GPIO_WRITEENABLE_OFFS 0
+#define GPIO_WRITEENABLE_MASK 0xffffffff
+#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
+
+#define GPIO_PULLUP_OFFS 0
+#define GPIO_PULLUP_MASK 0xffffffff
+#define GPIO_PULLUP(V) ((V & GPIO_PULLUP_MASK) << GPIO_PULLUP_OFFS)
+
+#define GPIO_PULDOWN_OFFS 0
+#define GPIO_PULDOWN_MASK 0xffffffff
+#define GPIO_PULDOWN(V) ((V & GPIO_PULDOWN_MASK) << GPIO_PULDOWN_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0
+#define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_0(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4
+#define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_1(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8
+#define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_2(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12
+#define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_3(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16
+#define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_4(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20
+#define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_5(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24
+#define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_6(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS)
+
+#define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28
+#define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7
+#define GPIO_DRIVESTRENGTH_0_PIN_7(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0
+#define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_8(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4
+#define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_9(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8
+#define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_10(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12
+#define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_11(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16
+#define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_12(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20
+#define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_13(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24
+#define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_14(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS)
+
+#define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28
+#define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7
+#define GPIO_DRIVESTRENGTH_1_PIN_15(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0
+#define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_16(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4
+#define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_17(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8
+#define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_18(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12
+#define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_19(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16
+#define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_20(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20
+#define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_21(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24
+#define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_22(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS)
+
+#define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28
+#define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7
+#define GPIO_DRIVESTRENGTH_2_PIN_23(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0
+#define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_24(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4
+#define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_25(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8
+#define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_26(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12
+#define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_27(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16
+#define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_28(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20
+#define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_29(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24
+#define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_30(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS)
+
+#define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28
+#define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7
+#define GPIO_DRIVESTRENGTH_3_PIN_31(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS)
+
+#define GPIO_IE_OFFS 0
+#define GPIO_IE_MASK 0xffffffff
+#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
+
+#define GPIO_IP_OFFS 0
+#define GPIO_IP_MASK 0xffffffff
+#define GPIO_IP(V) ((V & GPIO_IP_MASK) << GPIO_IP_OFFS)
+
+#define GPIO_IRQ_TRIGGER_OFFS 0
+#define GPIO_IRQ_TRIGGER_MASK 0xffffffff
+#define GPIO_IRQ_TRIGGER(V) ((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS)
+
+#define GPIO_IRQ_TYPE_OFFS 0
+#define GPIO_IRQ_TYPE_MASK 0xffffffff
+#define GPIO_IRQ_TYPE(V) ((V & GPIO_IRQ_TYPE_MASK) << GPIO_IRQ_TYPE_OFFS)
+
+#define GPIO_BOOT_SEL_OFFS 0
+#define GPIO_BOOT_SEL_MASK 0x7
+#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
+
+// GPIO_VALUE
+static inline uint32_t get_gpio_value(volatile gpio_t* reg) { return (reg->VALUE >> 0) & 0xffffffff; }
+
+// GPIO_WRITE
+static inline uint32_t get_gpio_write(volatile gpio_t* reg) { return (reg->WRITE >> 0) & 0xffffffff; }
+static inline void set_gpio_write(volatile gpio_t* reg, uint32_t value) { reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); }
+
+// GPIO_WRITEENABLE
+static inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg) { return (reg->WRITEENABLE >> 0) & 0xffffffff; }
+static inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value) {
+  reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// GPIO_PULLUP
+static inline uint32_t get_gpio_pullup(volatile gpio_t* reg) { return (reg->PULLUP >> 0) & 0xffffffff; }
+static inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value) {
+  reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// GPIO_PULDOWN
+static inline uint32_t get_gpio_puldown(volatile gpio_t* reg) { return (reg->PULDOWN >> 0) & 0xffffffff; }
+static inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value) {
+  reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// GPIO_DRIVESTRENGTH_0
+static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_0; }
+static inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_0 = value; }
+static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 0) & 0x7; }
+static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
+}
+static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; }
+static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
+}
+static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; }
+static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
+}
+static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; }
+static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
+}
+static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; }
+static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
+}
+static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; }
+static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
+}
+static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; }
+static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
+}
+static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; }
+static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
+}
+
+// GPIO_DRIVESTRENGTH_1
+static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_1; }
+static inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_1 = value; }
+static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 0) & 0x7; }
+static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
+}
+static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; }
+static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
+}
+static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; }
+static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
+}
+static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; }
+static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
+}
+static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; }
+static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
+}
+static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; }
+static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
+}
+static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; }
+static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
+}
+static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; }
+static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
+}
+
+// GPIO_DRIVESTRENGTH_2
+static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_2; }
+static inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_2 = value; }
+static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 0) & 0x7; }
+static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
+}
+static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; }
+static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
+}
+static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; }
+static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
+}
+static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; }
+static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
+}
+static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; }
+static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
+}
+static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; }
+static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
+}
+static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; }
+static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
+}
+static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; }
+static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
+}
+
+// GPIO_DRIVESTRENGTH_3
+static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_3; }
+static inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_3 = value; }
+static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 0) & 0x7; }
+static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
+}
+static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; }
+static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
+}
+static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; }
+static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
+}
+static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; }
+static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
+}
+static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; }
+static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
+}
+static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; }
+static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
+}
+static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; }
+static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
+}
+static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; }
+static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value) {
+  reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
+}
+
+// GPIO_IE
+static inline uint32_t get_gpio_ie(volatile gpio_t* reg) { return (reg->IE >> 0) & 0xffffffff; }
+static inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value) { reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0); }
+
+// GPIO_IP
+static inline uint32_t get_gpio_ip(volatile gpio_t* reg) { return (reg->IP >> 0) & 0xffffffff; }
+static inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value) { reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0); }
+
+// GPIO_IRQ_TRIGGER
+static inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg) { return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; }
+static inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value) {
+  reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// GPIO_IRQ_TYPE
+static inline uint32_t get_gpio_irq_type(volatile gpio_t* reg) { return (reg->IRQ_TYPE >> 0) & 0xffffffff; }
+static inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value) {
+  reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// GPIO_BOOT_SEL
+static inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg) { return reg->BOOT_SEL; }
+static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg) { return (reg->BOOT_SEL >> 0) & 0x7; }
+
+#endif /* _BSP_GPIO_H */

include/minres/devices/gen/i2s.h

@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2024-12-28 11:01:24 UTC
+ * by peakrdl_mnrs version 1.2.9
+ */
+
+#ifndef _BSP_I2S_H
+#define _BSP_I2S_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t LEFT_CH;
+  volatile uint32_t RIGHT_CH;
+  volatile uint32_t CONTROL;
+  volatile uint32_t STATUS;
+  volatile uint32_t I2S_CLOCK_CTRL;
+  volatile uint32_t PDM_CLOCK_CTRL;
+  volatile uint32_t PDM_FILTER_CTRL;
+  volatile uint32_t IE;
+  volatile uint32_t IP;
+} i2s_t;
+
+#define I2S_LEFT_CH_OFFS 0
+#define I2S_LEFT_CH_MASK 0xffffffff
+#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
+
+#define I2S_RIGHT_CH_OFFS 0
+#define I2S_RIGHT_CH_MASK 0xffffffff
+#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
+
+#define I2S_CONTROL_MODE_OFFS 0
+#define I2S_CONTROL_MODE_MASK 0x3
+#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
+
+#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
+#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
+#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
+
+#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
+#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
+#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
+
+#define I2S_CONTROL_IS_MASTER_OFFS 4
+#define I2S_CONTROL_IS_MASTER_MASK 0x1
+#define I2S_CONTROL_IS_MASTER(V) ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)
+
+#define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
+#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
+#define I2S_CONTROL_SAMPLE_SIZE(V) ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)
+
+#define I2S_CONTROL_PDM_SCALE_OFFS 7
+#define I2S_CONTROL_PDM_SCALE_MASK 0x7
+#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
+
+#define I2S_STATUS_ENABLED_OFFS 0
+#define I2S_STATUS_ENABLED_MASK 0x1
+#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
+
+#define I2S_STATUS_ACTIVE_OFFS 1
+#define I2S_STATUS_ACTIVE_MASK 0x1
+#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
+
+#define I2S_STATUS_LEFT_AVAIL_OFFS 2
+#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
+#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
+
+#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
+#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
+#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
+
+#define I2S_STATUS_LEFT_OVERFLOW_OFFS 4
+#define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1
+#define I2S_STATUS_LEFT_OVERFLOW(V) ((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS)
+
+#define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5
+#define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1
+#define I2S_STATUS_RIGHT_OVERFLOW(V) ((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS)
+
+#define I2S_I2S_CLOCK_CTRL_OFFS 0
+#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
+#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
+
+#define I2S_PDM_CLOCK_CTRL_OFFS 0
+#define I2S_PDM_CLOCK_CTRL_MASK 0xff
+#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
+
+#define I2S_PDM_FILTER_CTRL_OFFS 0
+#define I2S_PDM_FILTER_CTRL_MASK 0x3ff
+#define I2S_PDM_FILTER_CTRL(V) ((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS)
+
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
+#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
+#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
+
+// I2S_LEFT_CH
+static inline uint32_t get_i2s_left_ch(volatile i2s_t* reg) { return (reg->LEFT_CH >> 0) & 0xffffffff; }
+
+// I2S_RIGHT_CH
+static inline uint32_t get_i2s_right_ch(volatile i2s_t* reg) { return (reg->RIGHT_CH >> 0) & 0xffffffff; }
+
+// I2S_CONTROL
+static inline uint32_t get_i2s_control(volatile i2s_t* reg) { return reg->CONTROL; }
+static inline void set_i2s_control(volatile i2s_t* reg, uint32_t value) { reg->CONTROL = value; }
+static inline uint32_t get_i2s_control_mode(volatile i2s_t* reg) { return (reg->CONTROL >> 0) & 0x3; }
+static inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); }
+static inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg) { return (reg->CONTROL >> 2) & 0x1; }
+static inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value) {
+  reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
+}
+static inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg) { return (reg->CONTROL >> 3) & 0x1; }
+static inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value) {
+  reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
+}
+static inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg) { return (reg->CONTROL >> 4) & 0x1; }
+static inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value) {
+  reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
+}
+static inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg) { return (reg->CONTROL >> 5) & 0x3; }
+static inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value) {
+  reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
+}
+static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg) { return (reg->CONTROL >> 7) & 0x7; }
+static inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value) {
+  reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
+}
+
+// I2S_STATUS
+static inline uint32_t get_i2s_status(volatile i2s_t* reg) { return reg->STATUS; }
+static inline void set_i2s_status(volatile i2s_t* reg, uint32_t value) { reg->STATUS = value; }
+static inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg) { return (reg->STATUS >> 0) & 0x1; }
+static inline uint32_t get_i2s_status_active(volatile i2s_t* reg) { return (reg->STATUS >> 1) & 0x1; }
+static inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg) { return (reg->STATUS >> 2) & 0x1; }
+static inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg) { return (reg->STATUS >> 3) & 0x1; }
+static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 4) & 0x1; }
+static inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value) {
+  reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
+}
+static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 5) & 0x1; }
+static inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value) {
+  reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
+}
+
+// I2S_I2S_CLOCK_CTRL
+static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg) { return reg->I2S_CLOCK_CTRL; }
+static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->I2S_CLOCK_CTRL = value; }
+static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; }
+static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value) {
+  reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
+}
+
+// I2S_PDM_CLOCK_CTRL
+static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg) { return reg->PDM_CLOCK_CTRL; }
+static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_CLOCK_CTRL = value; }
+static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->PDM_CLOCK_CTRL >> 0) & 0xff; }
+static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value) {
+  reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
+}
+
+// I2S_PDM_FILTER_CTRL
+static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg) { return reg->PDM_FILTER_CTRL; }
+static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_FILTER_CTRL = value; }
+static inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg) { return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff; }
+static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value) {
+  reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
+}
+
+// I2S_IE
+static inline uint32_t get_i2s_ie(volatile i2s_t* reg) { return reg->IE; }
+static inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value) { reg->IE = value; }
+static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 0) & 0x1; }
+static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value) {
+  reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 1) & 0x1; }
+static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value) {
+  reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+
+// I2S_IP
+static inline uint32_t get_i2s_ip(volatile i2s_t* reg) { return reg->IP; }
+static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 0) & 0x1; }
+static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 1) & 0x1; }
+
+#endif /* _BSP_I2S_H */

include/minres/devices/gen/mkcontrolclusterstreamcontroller.h

@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2025-02-18 11:11:47 UTC
+ * by peakrdl_mnrs version 1.2.9
+ */
+
+#ifndef _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+#define _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t REG_SEND;
+  volatile uint32_t REG_HEADER;
+  volatile uint32_t REG_ACK;
+  volatile uint32_t REG_RECV_ID;
+  volatile uint32_t REG_RECV_PAYLOAD;
+  uint8_t fill0[12];
+  volatile uint32_t REG_PAYLOAD_0;
+  volatile uint32_t REG_PAYLOAD_1;
+  volatile uint32_t REG_PAYLOAD_2;
+  volatile uint32_t REG_PAYLOAD_3;
+  volatile uint32_t REG_PAYLOAD_4;
+  volatile uint32_t REG_PAYLOAD_5;
+  volatile uint32_t REG_PAYLOAD_6;
+  volatile uint32_t REG_PAYLOAD_7;
+} mkcontrolclusterstreamcontroller_t;
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V)    \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) \
+   << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V)    \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) \
+   << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) \
+  ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
+static inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_SEND = value;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
+  reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return reg->REG_HEADER;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_HEADER = value;
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_HEADER >> 0) & 0xf;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg,
+                                                                              uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_HEADER >> 4) & 0xf;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg,
+                                                                                  uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(
+    volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_HEADER >> 8) & 0x7;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg,
+                                                                                       uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_HEADER >> 11) & 0x3;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg,
+                                                                                     uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return reg->REG_ACK;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_ACK = value;
+}
+static inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
+  reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_ACK >> 1) & 0x1;
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return reg->REG_RECV_ID;
+}
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_RECV_ID >> 0) & 0xf;
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
+static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg) {
+  return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
+static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */

include/minres/devices/gen/msgif.h

@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2024-11-20 11:54:52 UTC
+ * by peakrdl_mnrs version 1.2.7
+ */
+
+#ifndef _BSP_MSGIF_H
+#define _BSP_MSGIF_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t REG_SEND;
+  volatile uint32_t REG_HEADER;
+  volatile uint32_t REG_ACK;
+  volatile uint32_t REG_RECV_ID;
+  volatile uint32_t REG_RECV_PAYLOAD;
+  uint8_t fill0[12];
+  volatile uint32_t REG_PAYLOAD_0;
+  volatile uint32_t REG_PAYLOAD_1;
+  volatile uint32_t REG_PAYLOAD_2;
+  volatile uint32_t REG_PAYLOAD_3;
+  volatile uint32_t REG_PAYLOAD_4;
+  volatile uint32_t REG_PAYLOAD_5;
+  volatile uint32_t REG_PAYLOAD_6;
+  volatile uint32_t REG_PAYLOAD_7;
+} msgif_t;
+
+#define MSGIF_REG_SEND_OFFS 0
+#define MSGIF_REG_SEND_MASK 0x1
+#define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
+
+#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 0
+#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
+#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
+
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 4
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
+
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \
+  ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
+
+#define MSGIF_REG_ACK_OFFS 0
+#define MSGIF_REG_ACK_MASK 0x1
+#define MSGIF_REG_ACK(V) ((V & MSGIF_REG_ACK_MASK) << MSGIF_REG_ACK_OFFS)
+
+#define MSGIF_REG_RECV_ID_OFFS 0
+#define MSGIF_REG_RECV_ID_MASK 0xf
+#define MSGIF_REG_RECV_ID(V) ((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS)
+
+#define MSGIF_REG_RECV_PAYLOAD_OFFS 0
+#define MSGIF_REG_RECV_PAYLOAD_MASK 0xffffffff
+#define MSGIF_REG_RECV_PAYLOAD(V) ((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS)
+
+#define MSGIF_REG_PAYLOAD_0_OFFS 0
+#define MSGIF_REG_PAYLOAD_0_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_0(V) ((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS)
+
+#define MSGIF_REG_PAYLOAD_1_OFFS 0
+#define MSGIF_REG_PAYLOAD_1_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_1(V) ((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS)
+
+#define MSGIF_REG_PAYLOAD_2_OFFS 0
+#define MSGIF_REG_PAYLOAD_2_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_2(V) ((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS)
+
+#define MSGIF_REG_PAYLOAD_3_OFFS 0
+#define MSGIF_REG_PAYLOAD_3_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_3(V) ((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS)
+
+#define MSGIF_REG_PAYLOAD_4_OFFS 0
+#define MSGIF_REG_PAYLOAD_4_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_4(V) ((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS)
+
+#define MSGIF_REG_PAYLOAD_5_OFFS 0
+#define MSGIF_REG_PAYLOAD_5_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_5(V) ((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS)
+
+#define MSGIF_REG_PAYLOAD_6_OFFS 0
+#define MSGIF_REG_PAYLOAD_6_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_6(V) ((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS)
+
+#define MSGIF_REG_PAYLOAD_7_OFFS 0
+#define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
+
+// MSGIF_REG_SEND
+static inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value) { reg->REG_SEND = value; }
+static inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value) {
+  reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
+}
+
+// MSGIF_REG_HEADER
+static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg) { return reg->REG_HEADER; }
+static inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value) { reg->REG_HEADER = value; }
+static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg) { return (reg->REG_HEADER >> 0) & 0xf; }
+static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
+}
+static inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg) { return (reg->REG_HEADER >> 4) & 0xf; }
+static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
+}
+static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg) { return (reg->REG_HEADER >> 8) & 0x7; }
+static inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
+}
+static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg) { return (reg->REG_HEADER >> 11) & 0x3; }
+static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
+}
+
+// MSGIF_REG_ACK
+static inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value) { reg->REG_ACK = value; }
+static inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value) {
+  reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
+}
+
+// MSGIF_REG_RECV_ID
+static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg) { return reg->REG_RECV_ID; }
+static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg) { return (reg->REG_RECV_ID >> 0) & 0xf; }
+
+// MSGIF_REG_RECV_PAYLOAD
+static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg) { return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; }
+
+// MSGIF_REG_PAYLOAD_0
+static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MSGIF_REG_PAYLOAD_1
+static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MSGIF_REG_PAYLOAD_2
+static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MSGIF_REG_PAYLOAD_3
+static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MSGIF_REG_PAYLOAD_4
+static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MSGIF_REG_PAYLOAD_5
+static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MSGIF_REG_PAYLOAD_6
+static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// MSGIF_REG_PAYLOAD_7
+static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_MSGIF_H */

include/minres/devices/gen/sysctrl.h

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2025-02-19 17:15:41 UTC
+ * by peakrdl_mnrs version 1.2.9
+ */
+
+#ifndef _BSP_SYSCTRL_H
+#define _BSP_SYSCTRL_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t SYSCTRL;
+  volatile uint32_t PLLCTRL;
+  volatile uint32_t AXI_BACKUP;
+} sysctrl_t;
+
+#define SYSCTRL_SYSCTRL_CC0_RESET_OFFS 0
+#define SYSCTRL_SYSCTRL_CC0_RESET_MASK 0x3
+#define SYSCTRL_SYSCTRL_CC0_RESET(V) ((V & SYSCTRL_SYSCTRL_CC0_RESET_MASK) << SYSCTRL_SYSCTRL_CC0_RESET_OFFS)
+
+#define SYSCTRL_SYSCTRL_CC1_RESET_OFFS 2
+#define SYSCTRL_SYSCTRL_CC1_RESET_MASK 0x3
+#define SYSCTRL_SYSCTRL_CC1_RESET(V) ((V & SYSCTRL_SYSCTRL_CC1_RESET_MASK) << SYSCTRL_SYSCTRL_CC1_RESET_OFFS)
+
+#define SYSCTRL_SYSCTRL_MEM_RESET_OFFS 4
+#define SYSCTRL_SYSCTRL_MEM_RESET_MASK 0x1
+#define SYSCTRL_SYSCTRL_MEM_RESET(V) ((V & SYSCTRL_SYSCTRL_MEM_RESET_MASK) << SYSCTRL_SYSCTRL_MEM_RESET_OFFS)
+
+#define SYSCTRL_PLLCTRL_P_COUNTER_OFFS 0
+#define SYSCTRL_PLLCTRL_P_COUNTER_MASK 0x3f
+#define SYSCTRL_PLLCTRL_P_COUNTER(V) ((V & SYSCTRL_PLLCTRL_P_COUNTER_MASK) << SYSCTRL_PLLCTRL_P_COUNTER_OFFS)
+
+#define SYSCTRL_PLLCTRL_S_COUNTER_OFFS 6
+#define SYSCTRL_PLLCTRL_S_COUNTER_MASK 0x3
+#define SYSCTRL_PLLCTRL_S_COUNTER(V) ((V & SYSCTRL_PLLCTRL_S_COUNTER_MASK) << SYSCTRL_PLLCTRL_S_COUNTER_OFFS)
+
+#define SYSCTRL_PLLCTRL_CLK_SEL_OFFS 8
+#define SYSCTRL_PLLCTRL_CLK_SEL_MASK 0x3
+#define SYSCTRL_PLLCTRL_CLK_SEL(V) ((V & SYSCTRL_PLLCTRL_CLK_SEL_MASK) << SYSCTRL_PLLCTRL_CLK_SEL_OFFS)
+
+#define SYSCTRL_PLLCTRL_LOCKED_OFFS 31
+#define SYSCTRL_PLLCTRL_LOCKED_MASK 0x1
+#define SYSCTRL_PLLCTRL_LOCKED(V) ((V & SYSCTRL_PLLCTRL_LOCKED_MASK) << SYSCTRL_PLLCTRL_LOCKED_OFFS)
+
+#define SYSCTRL_AXI_BACKUP_OFFS 0
+#define SYSCTRL_AXI_BACKUP_MASK 0x1f
+#define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS)
+
+// SYSCTRL_SYSCTRL
+static inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg) { return reg->SYSCTRL; }
+static inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value) { reg->SYSCTRL = value; }
+static inline uint32_t get_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg) { return (reg->SYSCTRL >> 0) & 0x3; }
+static inline void set_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg, uint8_t value) {
+  reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0);
+}
+static inline uint32_t get_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg) { return (reg->SYSCTRL >> 2) & 0x3; }
+static inline void set_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg, uint8_t value) {
+  reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 2)) | (value << 2);
+}
+static inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg) { return (reg->SYSCTRL >> 4) & 0x1; }
+static inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value) {
+  reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 4)) | (value << 4);
+}
+
+// SYSCTRL_PLLCTRL
+static inline uint32_t get_sysctrl_pllctrl(volatile sysctrl_t* reg) { return reg->PLLCTRL; }
+static inline void set_sysctrl_pllctrl(volatile sysctrl_t* reg, uint32_t value) { reg->PLLCTRL = value; }
+static inline uint32_t get_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg) { return (reg->PLLCTRL >> 0) & 0x3f; }
+static inline void set_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg, uint8_t value) {
+  reg->PLLCTRL = (reg->PLLCTRL & ~(0x3fU << 0)) | (value << 0);
+}
+static inline uint32_t get_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg) { return (reg->PLLCTRL >> 6) & 0x3; }
+static inline void set_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg, uint8_t value) {
+  reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 6)) | (value << 6);
+}
+static inline uint32_t get_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg) { return (reg->PLLCTRL >> 8) & 0x3; }
+static inline void set_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg, uint8_t value) {
+  reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 8)) | (value << 8);
+}
+static inline uint32_t get_sysctrl_pllctrl_locked(volatile sysctrl_t* reg) { return (reg->PLLCTRL >> 31) & 0x1; }
+
+// SYSCTRL_AXI_BACKUP
+static inline uint32_t get_sysctrl_axi_backup(volatile sysctrl_t* reg) { return reg->AXI_BACKUP; }
+static inline void set_sysctrl_axi_backup(volatile sysctrl_t* reg, uint32_t value) { reg->AXI_BACKUP = value; }
+static inline uint32_t get_sysctrl_axi_backup_page(volatile sysctrl_t* reg) { return (reg->AXI_BACKUP >> 0) & 0x1f; }
+static inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value) {
+  reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_SYSCTRL_H */

include/minres/devices/gen/timercounter.h

@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2024-12-26 18:07:07 UTC
+ * by peakrdl_mnrs version 1.2.9
+ */
+
+#ifndef _BSP_TIMERCOUNTER_H
+#define _BSP_TIMERCOUNTER_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t PRESCALER;
+  volatile uint32_t T0_CTRL;
+  volatile uint32_t T0_OVERFLOW;
+  volatile uint32_t T0_COUNTER;
+  volatile uint32_t T1_CTRL;
+  volatile uint32_t T1_OVERFLOW;
+  volatile uint32_t T1_COUNTER;
+} timercounter_t;
+
+#define TIMERCOUNTER_PRESCALER_OFFS 0
+#define TIMERCOUNTER_PRESCALER_MASK 0xffff
+#define TIMERCOUNTER_PRESCALER(V) ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS)
+
+#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0
+#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7
+#define TIMERCOUNTER_T0_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS)
+
+#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3
+#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3
+#define TIMERCOUNTER_T0_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS)
+
+#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0
+#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
+#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
+
+#define TIMERCOUNTER_T0_COUNTER_OFFS 0
+#define TIMERCOUNTER_T0_COUNTER_MASK 0xffffffff
+#define TIMERCOUNTER_T0_COUNTER(V) ((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS)
+
+#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
+#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
+#define TIMERCOUNTER_T1_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS)
+
+#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3
+#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3
+#define TIMERCOUNTER_T1_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS)
+
+#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0
+#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
+#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
+
+#define TIMERCOUNTER_T1_COUNTER_OFFS 0
+#define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff
+#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
+
+// TIMERCOUNTER_PRESCALER
+static inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg) { return reg->PRESCALER; }
+static inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value) { reg->PRESCALER = value; }
+static inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg) { return (reg->PRESCALER >> 0) & 0xffff; }
+static inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value) {
+  reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
+}
+
+// TIMERCOUNTER_T0_CTRL
+static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg) { return reg->T0_CTRL; }
+static inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T0_CTRL = value; }
+static inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 0) & 0x7; }
+static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
+  reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+static inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 3) & 0x3; }
+static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
+  reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+
+// TIMERCOUNTER_T0_OVERFLOW
+static inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg) { return (reg->T0_OVERFLOW >> 0) & 0xffffffff; }
+static inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value) {
+  reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// TIMERCOUNTER_T0_COUNTER
+static inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg) { return (reg->T0_COUNTER >> 0) & 0xffffffff; }
+
+// TIMERCOUNTER_T1_CTRL
+static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg) { return reg->T1_CTRL; }
+static inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T1_CTRL = value; }
+static inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 0) & 0x7; }
+static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
+  reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+static inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 3) & 0x3; }
+static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
+  reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+
+// TIMERCOUNTER_T1_OVERFLOW
+static inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg) { return (reg->T1_OVERFLOW >> 0) & 0xffffffff; }
+static inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value) {
+  reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// TIMERCOUNTER_T1_COUNTER
+static inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg) { return (reg->T1_COUNTER >> 0) & 0xffffffff; }
+
+#endif /* _BSP_TIMERCOUNTER_H */

include/minres/devices/gen/uart.h

@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated at 2024-08-02 08:46:07 UTC
+ * by peakrdl_mnrs version 1.2.7
+ */
+
+#ifndef _BSP_UART_H
+#define _BSP_UART_H
+
+#include <stdint.h>
+
+typedef struct {
+  volatile uint32_t RX_TX_REG;
+  volatile uint32_t INT_CTRL_REG;
+  volatile uint32_t CLK_DIVIDER_REG;
+  volatile uint32_t FRAME_CONFIG_REG;
+  volatile uint32_t STATUS_REG;
+} uart_t;
+
+#define UART_RX_TX_REG_DATA_OFFS 0
+#define UART_RX_TX_REG_DATA_MASK 0xff
+#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
+
+#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
+#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
+#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
+
+#define UART_RX_TX_REG_TX_FREE_OFFS 15
+#define UART_RX_TX_REG_TX_FREE_MASK 0x1
+#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
+
+#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
+#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
+#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
+#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
+
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
+
+#define UART_CLK_DIVIDER_REG_OFFS 0
+#define UART_CLK_DIVIDER_REG_MASK 0xfffff
+#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
+
+#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
+#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
+#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
+
+#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
+#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
+#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
+
+#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
+#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
+#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
+
+#define UART_STATUS_REG_READ_ERROR_OFFS 0
+#define UART_STATUS_REG_READ_ERROR_MASK 0x1
+#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
+
+#define UART_STATUS_REG_STALL_OFFS 1
+#define UART_STATUS_REG_STALL_MASK 0x1
+#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
+
+#define UART_STATUS_REG_BREAK_LINE_OFFS 8
+#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
+#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
+
+#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
+#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
+#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
+
+#define UART_STATUS_REG_SET_BREAK_OFFS 10
+#define UART_STATUS_REG_SET_BREAK_MASK 0x1
+#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
+
+#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
+#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
+#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
+
+// UART_RX_TX_REG
+static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
+static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
+static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
+static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
+  reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
+}
+static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
+static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
+static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
+
+// UART_INT_CTRL_REG
+static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
+static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
+static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
+static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
+  reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
+static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
+  reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
+}
+static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
+static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
+  reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
+}
+static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
+static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
+static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
+
+// UART_CLK_DIVIDER_REG
+static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
+static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
+static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
+static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
+  reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
+}
+
+// UART_FRAME_CONFIG_REG
+static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
+static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
+static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
+static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
+  reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
+}
+static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
+static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
+  reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
+}
+static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
+static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
+  reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
+}
+
+// UART_STATUS_REG
+static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
+static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
+static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
+static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
+static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
+static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
+static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
+  reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
+}
+static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
+static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
+  reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
+}
+static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
+static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
+  reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
+}
+
+#endif /* _BSP_UART_H */

include/minres/devices/gpio.h

@@ -0,0 +1,13 @@
+#ifndef _DEVICES_GPIO_H
+#define _DEVICES_GPIO_H
+
+#include <stdint.h>
+
+#include "gen/gpio.h"
+
+static inline void gpio_init(volatile gpio_t* reg) {
+  set_gpio_write(reg, 0);
+  set_gpio_writeEnable(reg, 0);
+}
+
+#endif /* _DEVICES_GPIO_H */

include/minres/devices/i2s.h

@@ -0,0 +1,9 @@
+#ifndef _DEVICES_IIS_H
+#define _DEVICES_IIS_H
+
+#include "gen/i2s.h"
+
+#define MODE_I2S 1
+#define MODE_PDM 2
+
+#endif /* _DEVICES_IIS_H */

include/minres/devices/interrupt.h

@@ -0,0 +1,10 @@
+#ifndef _DEVICES_INTERRUPT_H
+#define _DEVICES_INTERRUPT_H
+
+#include <stdint.h>
+
+#define irq_t void*
+
+static inline void irq_init(volatile irq_t* reg) {}
+
+#endif /* _DEVICES_INTERRUPT_H */

include/minres/devices/msg_if.h

@@ -0,0 +1,6 @@
+#ifndef _DEVICES_MSG_IF_H
+#define _DEVICES_MSG_IF_H
+
+#include "gen/mkcontrolclusterstreamcontroller.h"
+
+#endif /* _DEVICES_MSG_IF_H */

include/minres/devices/qspi.h

@@ -0,0 +1,92 @@
+#ifndef _DEVICES_QSPI_H
+#define _DEVICES_QSPI_H
+
+#include "gen/apb3spi.h"
+#include <stdint.h>
+
+#define qspi_t apb3spi_t
+typedef struct {
+  uint32_t cpol;
+  uint32_t cpha;
+  uint32_t mode;
+  uint32_t clkDivider;
+  uint32_t ssSetup;
+  uint32_t ssHold;
+  uint32_t ssDisable;
+} spi_cfg;
+
+#define SPI_CMD_WRITE (1 << 8)
+#define SPI_CMD_READ (1 << 9)
+#define SPI_CMD_SS (1 << 11)
+
+#define SPI_RSP_VALID (1 << 31)
+
+#define SPI_STATUS_CMD_INT_ENABLE = (1 << 0)
+#define SPI_STATUS_RSP_INT_ENABLE = (1 << 1)
+#define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
+#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
+
+static inline void spi_configure(volatile qspi_t *qspi, spi_cfg *config) {
+  set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) |
+                               (config->mode << 4));
+  set_apb3spi_sclk_config(qspi, config->clkDivider);
+  set_apb3spi_ssgen_setup(qspi, config->ssSetup);
+  set_apb3spi_ssgen_hold(qspi, config->ssHold);
+  set_apb3spi_ssgen_disable(qspi, config->ssDisable);
+}
+
+static inline void spi_init(volatile qspi_t *spi) {
+  spi_cfg spiCfg;
+  spiCfg.cpol = 0;
+  spiCfg.cpha = 0;
+  spiCfg.mode = 0;
+  spiCfg.clkDivider = 2;
+  spiCfg.ssSetup = 2;
+  spiCfg.ssHold = 2;
+  spiCfg.ssDisable = 2;
+  spi_configure(spi, &spiCfg);
+}
+
+static inline uint32_t spi_cmd_avail(volatile qspi_t *qspi) {
+  return qspi->STATUS & 0xFFFF;
+}
+static inline uint32_t spi_rsp_occupied(volatile qspi_t *qspi) {
+  return qspi->STATUS >> 16;
+}
+
+static inline void spi_write(volatile qspi_t *qspi, uint8_t data) {
+  while (spi_cmd_avail(qspi) == 0)
+    ;
+  qspi->DATA = data | SPI_CMD_WRITE;
+}
+
+static inline uint8_t spi_read(volatile qspi_t *qspi) {
+  while (spi_cmd_avail(qspi) == 0)
+    ;
+  qspi->DATA = SPI_CMD_READ;
+  while (spi_rsp_occupied(qspi) == 0)
+    ;
+  int32_t data;
+  do {
+      data = qspi->DATA ;
+  } while (data<0);
+  return data;
+}
+
+static inline void spi_select(volatile qspi_t *qspi, uint32_t slaveId) {
+  while (spi_cmd_avail(qspi) == 0)
+    ;
+  qspi->DATA = (slaveId & 0x3) | 0x80 | SPI_CMD_SS;
+}
+
+static inline void spi_deselect(volatile qspi_t *qspi, uint32_t slaveId) {
+  while (spi_cmd_avail(qspi) == 0)
+    ;
+  qspi->DATA = (slaveId & 0x3) | SPI_CMD_SS;
+}
+
+static inline void spi_wait_tx_idle(volatile qspi_t *qspi) {
+  while (spi_cmd_avail(qspi) < 0x20)
+    ;
+}
+#endif /* _DEVICES_QSPI_H */

include/minres/devices/sysctrl.h

@@ -0,0 +1,6 @@
+#ifndef _DEVICES_SYSCTRL_IF_H
+#define _DEVICES_SYSCTRL_IF_H
+
+#include "gen/sysctrl.h"
+
+#endif /* _DEVICES_sysctrl_IF_H */

include/minres/devices/timer.h

@@ -0,0 +1,14 @@
+#ifndef _DEVICES_TIMER_H
+#define _DEVICES_TIMER_H
+
+#include <stdint.h>
+
+#include "gen/timercounter.h"
+
+static inline void prescaler_init(timercounter_t *reg, uint16_t value) { set_timercounter_prescaler(reg, value); }
+
+static inline void timer_t0__init(timercounter_t *reg) { set_timercounter_t0_overflow(reg, 0xffffffff); }
+
+static inline void timer_t1__init(timercounter_t *reg) { set_timercounter_t1_overflow(reg, 0xffffffff); }
+
+#endif /* _DEVICES_TIMER_H */

include/minres/devices/uart.h

@@ -0,0 +1,30 @@
+#ifndef _DEVICES_UART_H
+#define _DEVICES_UART_H
+
+#include <stdint.h>
+#include "gen/uart.h"
+
+static inline uint32_t uart_get_tx_free(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_tx_free(reg);
+}
+
+static inline uint32_t uart_get_tx_empty(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_tx_empty(reg);
+}
+
+static inline uint32_t uart_get_rx_avail(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_rx_avail(reg);
+}
+
+static inline void uart_write(volatile uart_t* reg, uint8_t data){
+    while(get_uart_rx_tx_reg_tx_free(reg) == 0);
+    set_uart_rx_tx_reg_data(reg, data);
+}
+
+static inline uint8_t uart_read(volatile uart_t* reg){
+    uint32_t res = get_uart_rx_tx_reg_data(reg);
+    while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
+    return res;
+}
+
+#endif /* _DEVICES_UART_H */

include/rtl/const.h

@@ -1,27 +0,0 @@
-#ifndef _RTL_CONST_H
-#define _RTL_CONST_H
-
-#ifdef __ASSEMBLER__
-#define _AC(X,Y)        X
-#define _AT(T,X)        X
-#else
-#define _AC(X,Y)        (X##Y)
-#define _AT(T,X)        ((T)(X))
-#endif /* !__ASSEMBLER__*/
-
-#define _BITUL(x)       (_AC(1,UL) << (x))
-#define _BITULL(x)      (_AC(1,ULL) << (x))
-
-#define UART0_BASE_ADDR 0xffff0000ULL
-
-#define UART_REG_TXFIFO         0x00
-#define UART_REG_RXFIFO         0x04
-#define UART_REG_TXCTRL         0x08
-#define UART_REG_RXCTRL         0x0c
-#define UART_REG_IE             0x10
-#define UART_REG_IP             0x14
-#define UART_REG_DIV            0x18
-#define UART_TXEN               0x1
-
-#define UART0_REG(ADDR) *((volatile uint32_t*) (UART0_BASE_ADDR + ADDR))
-#endif /* _RTL_CONST_H */

include/semihosting.h

@@ -0,0 +1,31 @@
+#ifndef SEMIHOSTING_H
+#define SEMIHOSTING_H
+
+#include <sys/types.h>
+#include <unistd.h>
+// int32_t trace_write(const char* buf, uint32_t nbyte);
+
+void sh_seek(int, off_t);
+void sh_write0(const char *buf);
+void sh_writec(char c);
+char sh_readc(void);
+int sh_clock(void);
+int sh_read(char *, int, size_t);
+void sh_write(char *, int);
+int sh_open(char *, int);
+void sh_rename(char *, char *);
+int sh_remove(char *);
+int sh_istty(int);
+int sh_iserror(int);
+int sh_flen(int);
+void sh_exit(void);
+void sh_exit_extended(void);
+int sh_close(int);
+int sh_time(void);
+int sh_errno(void);
+
+int getchar(void);
+
+extern int sh_missing_host;
+
+#endif

include/sifive/bits.h

@@ -1,36 +0,0 @@
-// See LICENSE for license details.
-#ifndef _RISCV_BITS_H
-#define _RISCV_BITS_H
-
-#define likely(x) __builtin_expect((x), 1)
-#define unlikely(x) __builtin_expect((x), 0)
-
-#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
-#define ROUNDDOWN(a, b) ((a)/(b)*(b))
-
-#define MAX(a, b) ((a) > (b) ? (a) : (b))
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
-#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
-
-#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
-#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
-
-#define STR(x) XSTR(x)
-#define XSTR(x) #x
-
-#if __riscv_xlen == 64
-# define SLL32    sllw
-# define STORE    sd
-# define LOAD     ld
-# define LWU      lwu
-# define LOG_REGBYTES 3
-#else
-# define SLL32    sll
-# define STORE    sw
-# define LOAD     lw
-# define LWU      lw
-# define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-#endif

include/sifive/const.h

@@ -1,18 +0,0 @@
-// See LICENSE for license details.
-/* Derived from <linux/const.h> */
-
-#ifndef _SIFIVE_CONST_H
-#define _SIFIVE_CONST_H
-
-#ifdef __ASSEMBLER__
-#define _AC(X,Y)        X
-#define _AT(T,X)        X
-#else
-#define _AC(X,Y)        (X##Y)
-#define _AT(T,X)        ((T)(X))
-#endif /* !__ASSEMBLER__*/
-
-#define _BITUL(x)       (_AC(1,UL) << (x))
-#define _BITULL(x)      (_AC(1,ULL) << (x))
-
-#endif /* _SIFIVE_CONST_H */

include/sifive/devices/aon.h

@@ -1,88 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_AON_H
-#define _SIFIVE_AON_H
-
-/* Register offsets */
-
-#define AON_WDOGCFG     0x000
-#define AON_WDOGCOUNT   0x008
-#define AON_WDOGS       0x010
-#define AON_WDOGFEED    0x018
-#define AON_WDOGKEY     0x01C
-#define AON_WDOGCMP     0x020
-
-#define AON_RTCCFG      0x040
-#define AON_RTCLO       0x048
-#define AON_RTCHI       0x04C
-#define AON_RTCS        0x050
-#define AON_RTCCMP      0x060
-
-#define AON_BACKUP0     0x080
-#define AON_BACKUP1     0x084
-#define AON_BACKUP2     0x088
-#define AON_BACKUP3     0x08C
-#define AON_BACKUP4     0x090
-#define AON_BACKUP5     0x094
-#define AON_BACKUP6     0x098
-#define AON_BACKUP7     0x09C
-#define AON_BACKUP8     0x0A0
-#define AON_BACKUP9     0x0A4
-#define AON_BACKUP10    0x0A8
-#define AON_BACKUP11    0x0AC
-#define AON_BACKUP12    0x0B0
-#define AON_BACKUP13    0x0B4
-#define AON_BACKUP14    0x0B8
-#define AON_BACKUP15    0x0BC
-
-#define AON_PMUWAKEUPI0 0x100
-#define AON_PMUWAKEUPI1 0x104
-#define AON_PMUWAKEUPI2 0x108
-#define AON_PMUWAKEUPI3 0x10C
-#define AON_PMUWAKEUPI4 0x110
-#define AON_PMUWAKEUPI5 0x114
-#define AON_PMUWAKEUPI6 0x118
-#define AON_PMUWAKEUPI7 0x11C
-#define AON_PMUSLEEPI0  0x120
-#define AON_PMUSLEEPI1  0x124
-#define AON_PMUSLEEPI2  0x128
-#define AON_PMUSLEEPI3  0x12C
-#define AON_PMUSLEEPI4  0x130
-#define AON_PMUSLEEPI5  0x134
-#define AON_PMUSLEEPI6  0x138
-#define AON_PMUSLEEPI7  0x13C
-#define AON_PMUIE       0x140
-#define AON_PMUCAUSE    0x144
-#define AON_PMUSLEEP    0x148
-#define AON_PMUKEY      0x14C
-
-#define AON_LFROSC      0x070
-/* Constants */
-
-#define AON_WDOGKEY_VALUE  0x51F15E
-#define AON_WDOGFEED_VALUE 0xD09F00D
-
-#define AON_WDOGCFG_SCALE       0x0000000F
-#define AON_WDOGCFG_RSTEN       0x00000100
-#define AON_WDOGCFG_ZEROCMP     0x00000200
-#define AON_WDOGCFG_ENALWAYS    0x00001000
-#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
-#define AON_WDOGCFG_CMPIP       0x10000000
-
-#define AON_RTCCFG_SCALE     0x0000000F
-#define AON_RTCCFG_ENALWAYS  0x00001000
-#define AON_RTCCFG_CMPIP     0x10000000
-
-#define AON_WAKEUPCAUSE_RESET   0x00
-#define AON_WAKEUPCAUSE_RTC     0x01
-#define AON_WAKEUPCAUSE_DWAKEUP 0x02
-#define AON_WAKEUPCAUSE_AWAKEUP 0x03
-
-#define AON_RESETCAUSE_POWERON  0x0000
-#define AON_RESETCAUSE_EXTERNAL 0x0100
-#define AON_RESETCAUSE_WATCHDOG 0x0200
-
-#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
-#define AON_PMUCAUSE_RESETCAUSE  0xFF00
-
-#endif /* _SIFIVE_AON_H */

include/sifive/devices/clic.h

@@ -1,30 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_CLIC_H
-#define _SIFIVE_CLIC_H
-
-#define CLIC_HART0          0x00800000
-#define CLIC_MSIP           0x0000
-#define CLIC_MSIP_size      0x4
-#define CLIC_MTIMECMP       0x4000
-#define CLIC_MTIMECMP_size  0x8
-#define CLIC_MTIME          0xBFF8
-#define CLIC_MTIME_size     0x8
-
-#define CLIC_INTIP          0x000
-#define CLIC_INTIE          0x400
-#define CLIC_INTCFG         0x800
-#define CLIC_CFG            0xc00
-
-// These interrupt IDs are consistent across old and new mtvec modes
-#define SSIPID              1
-#define MSIPID              3
-#define STIPID              5
-#define MTIPID              7
-#define SEIPID              9
-#define MEIPID              11
-#define CSIPID              12
-#define LOCALINTIDBASE      16
-
-
-#endif /* _SIFIVE_CLIC_H */ 

include/sifive/devices/clint.h

@@ -1,14 +0,0 @@
-// See LICENSE for license details
-
-#ifndef _SIFIVE_CLINT_H
-#define _SIFIVE_CLINT_H
-
-
-#define CLINT_MSIP 0x0000
-#define CLINT_MSIP_size   0x4
-#define CLINT_MTIMECMP 0x4000
-#define CLINT_MTIMECMP_size 0x8
-#define CLINT_MTIME 0xBFF8
-#define CLINT_MTIME_size 0x8
-
-#endif /* _SIFIVE_CLINT_H */ 

include/sifive/devices/gpio.h

@@ -1,24 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_GPIO_H
-#define _SIFIVE_GPIO_H
-
-#define GPIO_INPUT_VAL  (0x00)
-#define GPIO_INPUT_EN   (0x04)
-#define GPIO_OUTPUT_EN  (0x08)
-#define GPIO_OUTPUT_VAL (0x0C)
-#define GPIO_PULLUP_EN  (0x10)
-#define GPIO_DRIVE      (0x14)
-#define GPIO_RISE_IE    (0x18)
-#define GPIO_RISE_IP    (0x1C)
-#define GPIO_FALL_IE    (0x20)
-#define GPIO_FALL_IP    (0x24)
-#define GPIO_HIGH_IE    (0x28)
-#define GPIO_HIGH_IP    (0x2C)
-#define GPIO_LOW_IE     (0x30)
-#define GPIO_LOW_IP     (0x34)
-#define GPIO_IOF_EN     (0x38)
-#define GPIO_IOF_SEL    (0x3C)
-#define GPIO_OUTPUT_XOR    (0x40)
-
-#endif /* _SIFIVE_GPIO_H */

include/sifive/devices/otp.h

@@ -1,23 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_OTP_H
-#define _SIFIVE_OTP_H
-
-/* Register offsets */
-
-#define OTP_LOCK         0x00
-#define OTP_CK           0x04
-#define OTP_OE           0x08
-#define OTP_SEL          0x0C
-#define OTP_WE           0x10
-#define OTP_MR           0x14
-#define OTP_MRR          0x18
-#define OTP_MPP          0x1C
-#define OTP_VRREN        0x20
-#define OTP_VPPEN        0x24
-#define OTP_A            0x28
-#define OTP_D            0x2C
-#define OTP_Q            0x30
-#define OTP_READ_TIMINGS 0x34
-
-#endif

include/sifive/devices/plic.h

@@ -1,31 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef PLIC_H
-#define PLIC_H
-
-#include <sifive/const.h>
-
-// 32 bits per source
-#define PLIC_PRIORITY_OFFSET            _AC(0x0000,UL)
-#define PLIC_PRIORITY_SHIFT_PER_SOURCE  2
-// 1 bit per source (1 address)
-#define PLIC_PENDING_OFFSET             _AC(0x1000,UL)
-#define PLIC_PENDING_SHIFT_PER_SOURCE   0
-
-//0x80 per target
-#define PLIC_ENABLE_OFFSET              _AC(0x2000,UL)
-#define PLIC_ENABLE_SHIFT_PER_TARGET    7
-
-
-#define PLIC_THRESHOLD_OFFSET           _AC(0x200000,UL)
-#define PLIC_CLAIM_OFFSET               _AC(0x200004,UL)
-#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
-#define PLIC_CLAIM_SHIFT_PER_TARGET     12
-
-#define PLIC_MAX_SOURCE                 1023
-#define PLIC_SOURCE_MASK                0x3FF
-
-#define PLIC_MAX_TARGET                 15871
-#define PLIC_TARGET_MASK                0x3FFF
-
-#endif /* PLIC_H */

include/sifive/devices/prci.h

@@ -1,56 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PRCI_H
-#define _SIFIVE_PRCI_H
-
-/* Register offsets */
-
-#define PRCI_HFROSCCFG   (0x0000)
-#define PRCI_HFXOSCCFG   (0x0004)
-#define PRCI_PLLCFG      (0x0008)
-#define PRCI_PLLDIV      (0x000C)
-#define PRCI_PROCMONCFG  (0x00F0)
-
-/* Fields */
-#define ROSC_DIV(x)    (((x) & 0x2F) << 0 ) 
-#define ROSC_TRIM(x)   (((x) & 0x1F) << 16)
-#define ROSC_EN(x)     (((x) & 0x1 ) << 30) 
-#define ROSC_RDY(x)    (((x) & 0x1 ) << 31)
-
-#define XOSC_EN(x)     (((x) & 0x1) << 30)
-#define XOSC_RDY(x)    (((x) & 0x1) << 31)
-
-#define PLL_R(x)       (((x) & 0x7)  << 0)
-// single reserved bit for F LSB.
-#define PLL_F(x)       (((x) & 0x3F) << 4)
-#define PLL_Q(x)       (((x) & 0x3)  << 10)
-#define PLL_SEL(x)     (((x) & 0x1)  << 16)
-#define PLL_REFSEL(x)  (((x) & 0x1)  << 17)
-#define PLL_BYPASS(x)  (((x) & 0x1)  << 18)
-#define PLL_LOCK(x)    (((x) & 0x1)  << 31)
-
-#define PLL_R_default 0x1
-#define PLL_F_default 0x1F
-#define PLL_Q_default 0x3
-
-#define PLL_REFSEL_HFROSC 0x0
-#define PLL_REFSEL_HFXOSC 0x1
-
-#define PLL_SEL_HFROSC 0x0
-#define PLL_SEL_PLL    0x1
-
-#define PLL_FINAL_DIV(x)      (((x) & 0x3F) << 0)
-#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
-
-#define PROCMON_DIV(x)   (((x) & 0x1F) << 0)
-#define PROCMON_TRIM(x)  (((x) & 0x1F) << 8)
-#define PROCMON_EN(x)    (((x) & 0x1)  << 16)
-#define PROCMON_SEL(x)   (((x) & 0x3)  << 24)
-#define PROCMON_NT_EN(x) (((x) & 0x1)  << 28)
-
-#define PROCMON_SEL_HFCLK     0
-#define PROCMON_SEL_HFXOSCIN  1
-#define PROCMON_SEL_PLLOUTDIV 2
-#define PROCMON_SEL_PROCMON   3
-
-#endif // _SIFIVE_PRCI_H

include/sifive/devices/pwm.h

@@ -1,37 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PWM_H
-#define _SIFIVE_PWM_H
-
-/* Register offsets */
-
-#define PWM_CFG   0x00
-#define PWM_COUNT 0x08
-#define PWM_S     0x10
-#define PWM_CMP0  0x20
-#define PWM_CMP1  0x24
-#define PWM_CMP2  0x28
-#define PWM_CMP3  0x2C
-
-/* Constants */
-
-#define PWM_CFG_SCALE       0x0000000F
-#define PWM_CFG_STICKY      0x00000100
-#define PWM_CFG_ZEROCMP     0x00000200
-#define PWM_CFG_DEGLITCH    0x00000400
-#define PWM_CFG_ENALWAYS    0x00001000
-#define PWM_CFG_ONESHOT     0x00002000
-#define PWM_CFG_CMP0CENTER  0x00010000
-#define PWM_CFG_CMP1CENTER  0x00020000
-#define PWM_CFG_CMP2CENTER  0x00040000
-#define PWM_CFG_CMP3CENTER  0x00080000
-#define PWM_CFG_CMP0GANG    0x01000000
-#define PWM_CFG_CMP1GANG    0x02000000
-#define PWM_CFG_CMP2GANG    0x04000000
-#define PWM_CFG_CMP3GANG    0x08000000
-#define PWM_CFG_CMP0IP      0x10000000
-#define PWM_CFG_CMP1IP      0x20000000
-#define PWM_CFG_CMP2IP      0x40000000
-#define PWM_CFG_CMP3IP      0x80000000
-
-#endif /* _SIFIVE_PWM_H */

include/sifive/devices/spi.h

@@ -1,80 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_SPI_H
-#define _SIFIVE_SPI_H
-
-/* Register offsets */
-
-#define SPI_REG_SCKDIV          0x00
-#define SPI_REG_SCKMODE         0x04
-#define SPI_REG_CSID            0x10
-#define SPI_REG_CSDEF           0x14
-#define SPI_REG_CSMODE          0x18
-
-#define SPI_REG_DCSSCK          0x28
-#define SPI_REG_DSCKCS          0x2a
-#define SPI_REG_DINTERCS        0x2c
-#define SPI_REG_DINTERXFR       0x2e
-
-#define SPI_REG_FMT             0x40
-#define SPI_REG_TXFIFO          0x48
-#define SPI_REG_RXFIFO          0x4c
-#define SPI_REG_TXCTRL          0x50
-#define SPI_REG_RXCTRL          0x54
-
-#define SPI_REG_FCTRL           0x60
-#define SPI_REG_FFMT            0x64
-
-#define SPI_REG_IE              0x70
-#define SPI_REG_IP              0x74
-
-/* Fields */
-
-#define SPI_SCK_PHA             0x1
-#define SPI_SCK_POL             0x2
-
-#define SPI_FMT_PROTO(x)        ((x) & 0x3)
-#define SPI_FMT_ENDIAN(x)       (((x) & 0x1) << 2)
-#define SPI_FMT_DIR(x)          (((x) & 0x1) << 3)
-#define SPI_FMT_LEN(x)          (((x) & 0xf) << 16)
-
-/* TXCTRL register */
-#define SPI_TXWM(x)             ((x) & 0xffff)
-/* RXCTRL register */
-#define SPI_RXWM(x)             ((x) & 0xffff)
-
-#define SPI_IP_TXWM             0x1
-#define SPI_IP_RXWM             0x2
-
-#define SPI_FCTRL_EN            0x1
-
-#define SPI_INSN_CMD_EN         0x1
-#define SPI_INSN_ADDR_LEN(x)    (((x) & 0x7) << 1)
-#define SPI_INSN_PAD_CNT(x)     (((x) & 0xf) << 4)
-#define SPI_INSN_CMD_PROTO(x)   (((x) & 0x3) << 8)
-#define SPI_INSN_ADDR_PROTO(x)  (((x) & 0x3) << 10)
-#define SPI_INSN_DATA_PROTO(x)  (((x) & 0x3) << 12)
-#define SPI_INSN_CMD_CODE(x)    (((x) & 0xff) << 16)
-#define SPI_INSN_PAD_CODE(x)    (((x) & 0xff) << 24)
-
-#define SPI_TXFIFO_FULL  (1 << 31)   
-#define SPI_RXFIFO_EMPTY (1 << 31)   
-
-/* Values */
-
-#define SPI_CSMODE_AUTO         0
-#define SPI_CSMODE_HOLD         2
-#define SPI_CSMODE_OFF          3
-
-#define SPI_DIR_RX              0
-#define SPI_DIR_TX              1
-
-#define SPI_PROTO_S             0
-#define SPI_PROTO_D             1
-#define SPI_PROTO_Q             2
-
-#define SPI_ENDIAN_MSB          0
-#define SPI_ENDIAN_LSB          1
-
-
-#endif /* _SIFIVE_SPI_H */

include/sifive/devices/uart.h

@@ -1,27 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_UART_H
-#define _SIFIVE_UART_H
-
-/* Register offsets */
-#define UART_REG_TXFIFO         0x00
-#define UART_REG_RXFIFO         0x04
-#define UART_REG_TXCTRL         0x08
-#define UART_REG_RXCTRL         0x0c
-#define UART_REG_IE             0x10
-#define UART_REG_IP             0x14
-#define UART_REG_DIV            0x18
-
-/* TXCTRL register */
-#define UART_TXEN               0x1
-#define UART_TXWM(x)            (((x) & 0xffff) << 16)
-
-/* RXCTRL register */
-#define UART_RXEN               0x1
-#define UART_RXWM(x)            (((x) & 0xffff) << 16)
-
-/* IP register */
-#define UART_IP_TXWM            0x1
-#define UART_IP_RXWM            0x2
-
-#endif /* _SIFIVE_UART_H */

include/sifive/sections.h

@@ -1,17 +0,0 @@
-// See LICENSE for license details.
-#ifndef _SECTIONS_H
-#define _SECTIONS_H
-
-extern unsigned char _rom[];
-extern unsigned char _rom_end[];
-
-extern unsigned char _ram[];
-extern unsigned char _ram_end[];
-
-extern unsigned char _ftext[];
-extern unsigned char _etext[];
-extern unsigned char _fbss[];
-extern unsigned char _ebss[];
-extern unsigned char _end[];
-
-#endif /* _SECTIONS_H */

include/sifive/smp.h

@@ -1,65 +0,0 @@
-#ifndef SIFIVE_SMP
-#define SIFIVE_SMP
-
-// The maximum number of HARTs this code supports
-#ifndef MAX_HARTS
-#define MAX_HARTS 32
-#endif
-#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
-
-// The hart that non-SMP tests should run on
-#ifndef NONSMP_HART
-#define NONSMP_HART 0
-#endif
-
-/* If your test cannot handle multiple-threads, use this: 
- *   smp_disable(reg1)
- */
-#define smp_disable(reg1, reg2)			 \
-  csrr reg1, mhartid				;\
-  li   reg2, NONSMP_HART			;\
-  beq  reg1, reg2, hart0_entry			;\
-42:						;\
-  wfi    					;\
-  j 42b						;\
-hart0_entry:
-
-/* If your test needs to temporarily block multiple-threads, do this:
- *    smp_pause(reg1, reg2)
- *    ... single-threaded work ...
- *    smp_resume(reg1, reg2)
- *    ... multi-threaded work ...
- */
-
-#define smp_pause(reg1, reg2)	 \
-  li reg2, 0x8			;\
-  csrw mie, reg2		;\
-  csrr reg2, mhartid		;\
-  bnez reg2, 42f
-
-#define smp_resume(reg1, reg2)	 \
-  li reg1, CLINT_CTRL_ADDR	;\
-41:				;\
-  li reg2, 1			;\
-  sw reg2, 0(reg1)		;\
-  addi reg1, reg1, 4		;\
-  li reg2, CLINT_END_HART_IPI	;\
-  blt reg1, reg2, 41b		;\
-42:				;\
-  wfi    			;\
-  csrr reg2, mip		;\
-  andi reg2, reg2, 0x8		;\
-  beqz reg2, 42b		;\
-  li reg1, CLINT_CTRL_ADDR	;\
-  csrr reg2, mhartid		;\
-  slli reg2, reg2, 2		;\
-  add reg2, reg2, reg1		;\
-  sw zero, 0(reg2)		;\
-41:				;\
-  lw reg2, 0(reg1)		;\
-  bnez reg2, 41b		;\
-  addi reg1, reg1, 4		;\
-  li reg2, CLINT_END_HART_IPI	;\
-  blt reg1, reg2, 41b
-
-#endif

include/tgc-vp/bits.h

@@ -1,35 +0,0 @@
-#ifndef _RISCV_BITS_H
-#define _RISCV_BITS_H
-
-#define likely(x) __builtin_expect((x), 1)
-#define unlikely(x) __builtin_expect((x), 0)
-
-#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
-#define ROUNDDOWN(a, b) ((a)/(b)*(b))
-
-#define MAX(a, b) ((a) > (b) ? (a) : (b))
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
-#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
-
-#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
-#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
-
-#define STR(x) XSTR(x)
-#define XSTR(x) #x
-
-#ifdef __riscv64
-# define SLL32    sllw
-# define STORE    sd
-# define LOAD     ld
-# define LWU      lwu
-# define LOG_REGBYTES 3
-#else
-# define SLL32    sll
-# define STORE    sw
-# define LOAD     lw
-# define LWU      lw
-# define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-#endif

include/tgc-vp/const.h

@@ -1,17 +0,0 @@
-/* Derived from <linux/const.h> */
-
-#ifndef _SIFIVE_CONST_H
-#define _SIFIVE_CONST_H
-
-#ifdef __ASSEMBLER__
-#define _AC(X,Y)        X
-#define _AT(T,X)        X
-#else
-#define _AC(X,Y)        (X##Y)
-#define _AT(T,X)        ((T)(X))
-#endif /* !__ASSEMBLER__*/
-
-#define _BITUL(x)       (_AC(1,UL) << (x))
-#define _BITULL(x)      (_AC(1,ULL) << (x))
-
-#endif /* _SIFIVE_CONST_H */

include/tgc-vp/devices/plic.h

@@ -3,7 +3,7 @@
 #ifndef PLIC_H
 #define PLIC_H
 
-#include <tgc-vp/const.h>
+//#include <tgc-vp/const.h>
 
 // 32 bits per source
 #define PLIC_PRIORITY_OFFSET            _AC(0x0000,UL)