Firmware/MNRS-BM-BSP
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updates BSP definitions for Ehrenberg

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This commit is contained in:
Eyck Jentzsch 2024-07-01 11:41:28 +02:00
parent daa1ed184d
commit 9d607e932a
4 changed files with 107 additions and 47 deletions
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5
include/ehrenberg/devices/dma.h
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@ -3,4 +3,9 @@
#include "gen/simpledma.h"
#define EVENT_UART 1
#define I2S_LEFT_SAMPLE_AVAIL 2
#define I2S_RIGHT_SAMPLE_AVAIL 4
#define CAMERA_PIXEL_AVAIL 8
#endif /* _BSP_DMA_H */

8
include/ehrenberg/devices/gen/i2s.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-06-08 13:20:02 UTC
* Generated at 2024-06-16 13:56:44 UTC
* by peakrdl_mnrs version 1.2.5
*/
@ -99,17 +99,11 @@ typedef struct __attribute((__packed__)) {
inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
return (reg->LEFT_CH >> 0) & 0xffffffff;
}
inline void set_i2s_left_ch(volatile i2s_t* reg, uint32_t value){
reg->LEFT_CH = (reg->LEFT_CH & ~(0xffffffffU << 0)) | (value << 0);
}
//I2S_RIGHT_CH
inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
return (reg->RIGHT_CH >> 0) & 0xffffffff;
}
inline void set_i2s_right_ch(volatile i2s_t* reg, uint32_t value){
reg->RIGHT_CH = (reg->RIGHT_CH & ~(0xffffffffU << 0)) | (value << 0);
}
//I2S_CONTROL
inline uint32_t get_i2s_control(volatile i2s_t* reg){

138
include/ehrenberg/devices/gen/simpledma.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-06-08 13:20:02 UTC
* Generated at 2024-06-16 13:56:44 UTC
* by peakrdl_mnrs version 1.2.5
*/
@ -15,14 +15,14 @@
typedef struct __attribute((__packed__)) {
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t EVENT_SEL;
volatile uint32_t EVENT;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t TRANSFER;
volatile uint32_t SRC_START_ADDR;
volatile uint32_t SRC_STRIDE;
volatile uint32_t SRC_ADDR_INC;
volatile uint32_t DST_START_ADDR;
volatile uint32_t DST_STRIDE;
volatile uint32_t DST_ADDR_INC;
}simpledma_t;
#define SIMPLEDMA_CONTROL_OFFS 0
@ -33,9 +33,13 @@ typedef struct __attribute((__packed__)) {
#define SIMPLEDMA_STATUS_MASK 0x1
#define SIMPLEDMA_STATUS(V) ((V & SIMPLEDMA_STATUS_MASK) << SIMPLEDMA_STATUS_OFFS)
#define SIMPLEDMA_EVENT_SEL_OFFS 0
#define SIMPLEDMA_EVENT_SEL_MASK 0x3
#define SIMPLEDMA_EVENT_SEL(V) ((V & SIMPLEDMA_EVENT_SEL_MASK) << SIMPLEDMA_EVENT_SEL_OFFS)
#define SIMPLEDMA_EVENT_SELECT_OFFS 0
#define SIMPLEDMA_EVENT_SELECT_MASK 0x1f
#define SIMPLEDMA_EVENT_SELECT(V) ((V & SIMPLEDMA_EVENT_SELECT_MASK) << SIMPLEDMA_EVENT_SELECT_OFFS)
#define SIMPLEDMA_EVENT_COMBINE_OFFS 31
#define SIMPLEDMA_EVENT_COMBINE_MASK 0x1
#define SIMPLEDMA_EVENT_COMBINE(V) ((V & SIMPLEDMA_EVENT_COMBINE_MASK) << SIMPLEDMA_EVENT_COMBINE_OFFS)
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS 0
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK 0x1
@ -53,29 +57,41 @@ typedef struct __attribute((__packed__)) {
#define SIMPLEDMA_IP_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_TRANSFER_LENGTH_OFFS 0
#define SIMPLEDMA_TRANSFER_LENGTH_MASK 0x3ff
#define SIMPLEDMA_TRANSFER_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_LENGTH_MASK) << SIMPLEDMA_TRANSFER_LENGTH_OFFS)
#define SIMPLEDMA_TRANSFER_WIDTH_OFFS 0
#define SIMPLEDMA_TRANSFER_WIDTH_MASK 0x3
#define SIMPLEDMA_TRANSFER_WIDTH(V) ((V & SIMPLEDMA_TRANSFER_WIDTH_MASK) << SIMPLEDMA_TRANSFER_WIDTH_OFFS)
#define SIMPLEDMA_TRANSFER_COUNT_OFFS 12
#define SIMPLEDMA_TRANSFER_COUNT_MASK 0xfffff
#define SIMPLEDMA_TRANSFER_COUNT(V) ((V & SIMPLEDMA_TRANSFER_COUNT_MASK) << SIMPLEDMA_TRANSFER_COUNT_OFFS)
#define SIMPLEDMA_TRANSFER_SEG_LENGTH_OFFS 2
#define SIMPLEDMA_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define SIMPLEDMA_TRANSFER_SEG_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_SEG_LENGTH_MASK) << SIMPLEDMA_TRANSFER_SEG_LENGTH_OFFS)
#define SIMPLEDMA_TRANSFER_SEG_COUNT_OFFS 12
#define SIMPLEDMA_TRANSFER_SEG_COUNT_MASK 0xfffff
#define SIMPLEDMA_TRANSFER_SEG_COUNT(V) ((V & SIMPLEDMA_TRANSFER_SEG_COUNT_MASK) << SIMPLEDMA_TRANSFER_SEG_COUNT_OFFS)
#define SIMPLEDMA_SRC_START_ADDR_OFFS 0
#define SIMPLEDMA_SRC_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_SRC_START_ADDR(V) ((V & SIMPLEDMA_SRC_START_ADDR_MASK) << SIMPLEDMA_SRC_START_ADDR_OFFS)
#define SIMPLEDMA_SRC_STRIDE_OFFS 0
#define SIMPLEDMA_SRC_STRIDE_MASK 0xffffffff
#define SIMPLEDMA_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_STRIDE_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STEP(V) ((V & SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_MASK) << SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define SIMPLEDMA_DST_START_ADDR_OFFS 0
#define SIMPLEDMA_DST_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_DST_START_ADDR(V) ((V & SIMPLEDMA_DST_START_ADDR_MASK) << SIMPLEDMA_DST_START_ADDR_OFFS)
#define SIMPLEDMA_DST_STRIDE_OFFS 0
#define SIMPLEDMA_DST_STRIDE_MASK 0xffffffff
#define SIMPLEDMA_DST_STRIDE(V) ((V & SIMPLEDMA_DST_STRIDE_MASK) << SIMPLEDMA_DST_STRIDE_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_DST_STEP_OFFS 0
#define SIMPLEDMA_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define SIMPLEDMA_DST_ADDR_INC_DST_STEP(V) ((V & SIMPLEDMA_DST_ADDR_INC_DST_STEP_MASK) << SIMPLEDMA_DST_ADDR_INC_DST_STEP_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define SIMPLEDMA_DST_ADDR_INC_DST_STRIDE(V) ((V & SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_MASK) << SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_OFFS)
//SIMPLEDMA_CONTROL
inline uint32_t get_simpledma_control(volatile simpledma_t* reg){
@ -90,12 +106,24 @@ inline uint32_t get_simpledma_status(volatile simpledma_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
//SIMPLEDMA_EVENT_SEL
inline uint32_t get_simpledma_event_sel(volatile simpledma_t* reg){
return (reg->EVENT_SEL >> 0) & 0x3;
//SIMPLEDMA_EVENT
inline uint32_t get_simpledma_event(volatile simpledma_t* reg){
return reg->EVENT;
}
inline void set_simpledma_event_sel(volatile simpledma_t* reg, uint8_t value){
reg->EVENT_SEL = (reg->EVENT_SEL & ~(0x3U << 0)) | (value << 0);
inline void set_simpledma_event(volatile simpledma_t* reg, uint32_t value){
reg->EVENT = value;
}
inline uint32_t get_simpledma_event_select(volatile simpledma_t* reg){
return (reg->EVENT >> 0) & 0x1f;
}
inline void set_simpledma_event_select(volatile simpledma_t* reg, uint8_t value){
reg->EVENT = (reg->EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_event_combine(volatile simpledma_t* reg){
return (reg->EVENT >> 31) & 0x1;
}
inline void set_simpledma_event_combine(volatile simpledma_t* reg, uint8_t value){
reg->EVENT = (reg->EVENT & ~(0x1U << 31)) | (value << 31);
}
//SIMPLEDMA_IE
@ -139,16 +167,22 @@ inline uint32_t get_simpledma_transfer(volatile simpledma_t* reg){
inline void set_simpledma_transfer(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER = value;
}
inline uint32_t get_simpledma_transfer_length(volatile simpledma_t* reg){
return (reg->TRANSFER >> 0) & 0x3ff;
inline uint32_t get_simpledma_transfer_width(volatile simpledma_t* reg){
return (reg->TRANSFER >> 0) & 0x3;
}
inline void set_simpledma_transfer_length(volatile simpledma_t* reg, uint16_t value){
reg->TRANSFER = (reg->TRANSFER & ~(0x3ffU << 0)) | (value << 0);
inline void set_simpledma_transfer_width(volatile simpledma_t* reg, uint8_t value){
reg->TRANSFER = (reg->TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_simpledma_transfer_count(volatile simpledma_t* reg){
inline uint32_t get_simpledma_transfer_seg_length(volatile simpledma_t* reg){
return (reg->TRANSFER >> 2) & 0x3ff;
}
inline void set_simpledma_transfer_seg_length(volatile simpledma_t* reg, uint16_t value){
reg->TRANSFER = (reg->TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_simpledma_transfer_seg_count(volatile simpledma_t* reg){
return (reg->TRANSFER >> 12) & 0xfffff;
}
inline void set_simpledma_transfer_count(volatile simpledma_t* reg, uint32_t value){
inline void set_simpledma_transfer_seg_count(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER = (reg->TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
@ -160,12 +194,24 @@ inline void set_simpledma_src_start_addr(volatile simpledma_t* reg, uint32_t val
reg->SRC_START_ADDR = (reg->SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
//SIMPLEDMA_SRC_STRIDE
inline uint32_t get_simpledma_src_stride(volatile simpledma_t* reg){
return (reg->SRC_STRIDE >> 0) & 0xffffffff;
//SIMPLEDMA_SRC_ADDR_INC
inline uint32_t get_simpledma_src_addr_inc(volatile simpledma_t* reg){
return reg->SRC_ADDR_INC;
}
inline void set_simpledma_src_stride(volatile simpledma_t* reg, uint32_t value){
reg->SRC_STRIDE = (reg->SRC_STRIDE & ~(0xffffffffU << 0)) | (value << 0);
inline void set_simpledma_src_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC = value;
}
inline uint32_t get_simpledma_src_addr_inc_src_step(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_simpledma_src_addr_inc_src_step(volatile simpledma_t* reg, uint16_t value){
reg->SRC_ADDR_INC = (reg->SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_src_addr_inc_src_stride(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_simpledma_src_addr_inc_src_stride(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC = (reg->SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
//SIMPLEDMA_DST_START_ADDR
@ -176,12 +222,24 @@ inline void set_simpledma_dst_start_addr(volatile simpledma_t* reg, uint32_t val
reg->DST_START_ADDR = (reg->DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
//SIMPLEDMA_DST_STRIDE
inline uint32_t get_simpledma_dst_stride(volatile simpledma_t* reg){
return (reg->DST_STRIDE >> 0) & 0xffffffff;
//SIMPLEDMA_DST_ADDR_INC
inline uint32_t get_simpledma_dst_addr_inc(volatile simpledma_t* reg){
return reg->DST_ADDR_INC;
}
inline void set_simpledma_dst_stride(volatile simpledma_t* reg, uint32_t value){
reg->DST_STRIDE = (reg->DST_STRIDE & ~(0xffffffffU << 0)) | (value << 0);
inline void set_simpledma_dst_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC = value;
}
inline uint32_t get_simpledma_dst_addr_inc_dst_step(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_simpledma_dst_addr_inc_dst_step(volatile simpledma_t* reg, uint16_t value){
reg->DST_ADDR_INC = (reg->DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_dst_addr_inc_dst_stride(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_simpledma_dst_addr_inc_dst_stride(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC = (reg->DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
#endif /* _BSP_SIMPLEDMA_H */

3
include/ehrenberg/devices/i2s.h
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@ -3,4 +3,7 @@
#include "gen/i2s.h"
#define MODE_I2S 1
#define MODE_PDM 2
#endif /* _BSP_IIS_H */