adds ehrenberg platform
This commit is contained in:
parent
1d55083a55
commit
13cd5cc76d
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@ -1,8 +1,10 @@
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ifndef _MK_COMMON
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_MK_COMMON := # defined
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.PHONY: all
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all: $(TARGET)
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TL_TARGET?=all
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.PHONY: $(TL_TARGET)
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$(TL_TARGET): $(TARGET)
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include $(BSP_BASE)/libwrap/libwrap.mk
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@ -14,17 +16,17 @@ ASM_SRCS += $(ENV_DIR)/start.S
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ASM_SRCS += $(ENV_DIR)/entry.S
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C_SRCS += $(PLATFORM_DIR)/init.c
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LINKER_SCRIPT := $(PLATFORM_DIR)/$(LINK_TARGET).lds
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LINKER_SCRIPT ?= $(PLATFORM_DIR)/$(LINK_TARGET).lds
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INCLUDES += -I$(BSP_BASE)/include
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INCLUDES += -I$(BSP_BASE)/drivers/
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INCLUDES += -I$(ENV_DIR)
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INCLUDES += -I$(PLATFORM_DIR)
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TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin/
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LDFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
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ifndef NO_DEFAULT_LINK
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LDFLAGS += -T $(LINKER_SCRIPT) -Wl,--no-warn-rwx-segments -Wl,-Map=$(TARGET).map -nostartfiles
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endif
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LDFLAGS += -L$(ENV_DIR)
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# --specs=nano.specs
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@ -53,12 +55,14 @@ CC=$(TOOL_DIR)$(TRIPLET)-gcc
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LD=$(TOOL_DIR)$(TRIPLET)-gcc
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AR=$(TOOL_DIR)$(TRIPLET)-ar
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OBJDUMP := $(TOOL_DIR)$(TRIPLET)-objdump
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OBJCOPY := $(TOOL_DIR)$(TRIPLET)-objcopy
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$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
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ifndef NO_DEFAULT_LINK
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$(TARGET).elf: $(LINK_OBJS) $(LINK_DEPS)
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$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP) -o $@
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$(OBJDUMP) -d -S $(TARGET) > $(TARGET).dis
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$(OBJDUMP) -d -S $@ > $(TARGET).dis
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endif
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$(ASM_OBJS): %.o: %.S $(HEADERS)
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$(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
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@ -0,0 +1 @@
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/*.o
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@ -0,0 +1,140 @@
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#include <stdint.h>
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#include <stdio.h>
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#include <unistd.h>
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#include "platform.h"
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#include "encoding.h"
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#include <ehrenberg/devices.h>
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#if __riscv_xlen == 32
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#define MCAUSE_INT 0x80000000UL
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#define MCAUSE_CAUSE 0x000003FFUL
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#else
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#define MCAUSE_INT 0x8000000000000000UL
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#define MCAUSE_CAUSE 0x00000000000003FFUL
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#endif
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extern int main(int argc, char** argv);
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extern void trap_entry();
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#define IRQ_M_SOFT 3
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#define IRQ_M_TIMER 7
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#define IRQ_M_EXT 11
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#define NUM_INTERRUPTS 16
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#define MTIMER_NEXT_TICK_INC 1000
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void handle_m_ext_interrupt(void);
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void handle_m_time_interrupt(void);
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uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp);
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void default_handler(void);
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void _init(void);
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typedef void (*my_interrupt_function_ptr_t) (void);
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my_interrupt_function_ptr_t localISR[NUM_INTERRUPTS] __attribute__((aligned(64)));
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static unsigned long mtime_lo(void)
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{
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unsigned long ret;
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__asm volatile("rdtime %0":"=r"(ret));
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return ret;
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}
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#if __riscv_xlen==32
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static uint32_t mtime_hi(void)
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{
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unsigned long ret;
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__asm volatile("rdtimeh %0":"=r"(ret));
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return ret;
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}
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uint64_t get_timer_value()
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{
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while (1) {
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uint32_t hi = mtime_hi();
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uint32_t lo = mtime_lo();
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if (hi == mtime_hi())
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return ((uint64_t)hi << 32) | lo;
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}
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}
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#elif __riscv_xlen==64
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uint64_t get_timer_value()
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{
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return mtime_lo();
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}
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#endif
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unsigned long get_timer_freq()
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{
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return 32768;
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}
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unsigned long get_cpu_freq()
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{
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return 100000000;
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}
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void init_pll(void){
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//TODO: implement initialization
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}
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static void uart_init(size_t baud_rate)
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{
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//TODO: implement initialization
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}
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void __attribute__((weak)) handle_m_ext_interrupt(){
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}
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void __attribute__((weak)) handle_m_time_interrupt(){
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uint64_t time = ((uint64_t)mtimer->mtimeh)<<32 || mtimer->mtime;
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time+=MTIMER_NEXT_TICK_INC;
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mtimer->mtimecmph = time>>32;
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mtimer->mtimecmp = time;
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}
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void __attribute__((weak)) default_handler(void) {
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puts("default handler\n");
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}
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uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp){
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if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
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handle_m_ext_interrupt();
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// External Machine-Level interrupt from PLIC
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} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
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handle_m_time_interrupt();
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} else {
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write(1, "trap\n", 5);
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_exit(1 + mcause);
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}
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return mepc;
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}
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void _init()
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{
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#ifndef NO_INIT
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init_pll();
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uart_init(115200);
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printf("core freq at %d Hz\n", get_cpu_freq());
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write_csr(mtvec, &trap_entry);
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if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
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write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
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write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
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}
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int i=0;
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while(i<NUM_INTERRUPTS) {
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localISR[i++] = default_handler;
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}
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#endif
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}
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void _fini()
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{
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}
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@ -0,0 +1,173 @@
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OUTPUT_ARCH( "riscv" )
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ENTRY( _start )
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MEMORY
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{
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flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 512M
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ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128K
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}
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PHDRS
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{
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flash PT_LOAD;
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ram_init PT_LOAD;
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ram PT_NULL;
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}
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SECTIONS
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{
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__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
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.init ORIGIN(flash) :
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{
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KEEP (*(SORT_NONE(.init)))
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} >flash AT>flash :flash
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.text :
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{
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*(.text.unlikely .text.unlikely.*)
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*(.text.startup .text.startup.*)
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*(.text .text.*)
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*(.gnu.linkonce.t.*)
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} >flash AT>flash :flash
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.fini :
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{
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KEEP (*(SORT_NONE(.fini)))
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} >flash AT>flash :flash
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PROVIDE (__etext = .);
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PROVIDE (_etext = .);
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rdata)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r.*)
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} >flash AT>flash :flash
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. = ALIGN(4);
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.preinit_array :
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{
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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} >flash AT>flash :flash
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.init_array :
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{
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
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PROVIDE_HIDDEN (__init_array_end = .);
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} >flash AT>flash :flash
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.fini_array :
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{
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
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KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
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PROVIDE_HIDDEN (__fini_array_end = .);
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} >flash AT>flash :flash
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.ctors :
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{
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/* gcc uses crtbegin.o to find the start of
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the constructors, so we make sure it is
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first. Because this is a wildcard, it
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doesn't matter if the user does not
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actually link against crtbegin.o; the
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linker won't look for a file to match a
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wildcard. The wildcard also means that it
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doesn't matter which directory crtbegin.o
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is in. */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*crtbegin?.o(.ctors))
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/* We don't want to include the .ctor section from
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the crtend.o file until after the sorted ctors.
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The .ctor section from the crtend file contains the
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end of ctors marker and it must be last */
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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} >flash AT>flash :flash
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.dtors :
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{
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KEEP (*crtbegin.o(.dtors))
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KEEP (*crtbegin?.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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} >flash AT>flash :flash
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.lalign :
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{
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. = ALIGN(4);
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PROVIDE( _data_lma = . );
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} >flash AT>flash :flash
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.dalign :
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{
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. = ALIGN(4);
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PROVIDE( _data = . );
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} >ram AT>flash :ram_init
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.data :
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{
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__DATA_BEGIN__ = .;
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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} >ram AT>flash :ram_init
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.srodata :
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{
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*(.srodata.cst16)
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*(.srodata.cst8)
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*(.srodata.cst4)
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*(.srodata.cst2)
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*(.srodata .srodata.*)
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} >ram AT>flash :ram_init
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.sdata :
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{
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__SDATA_BEGIN__ = .;
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*(.sdata .sdata.*)
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*(.gnu.linkonce.s.*)
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} >ram AT>flash :ram_init
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. = ALIGN(4);
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PROVIDE( _edata = . );
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PROVIDE( edata = . );
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PROVIDE( _fbss = . );
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PROVIDE( __bss_start = . );
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.bss :
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{
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*(.sbss*)
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*(.gnu.linkonce.sb.*)
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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} >ram AT>ram :ram
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. = ALIGN(8);
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__BSS_END__ = .;
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__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
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PROVIDE( _end = . );
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PROVIDE( end = . );
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.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
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{
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PROVIDE( _heap_end = . );
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. = __stack_size;
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PROVIDE( _sp = . );
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} >ram AT>ram :ram
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PROVIDE( tohost = 0xfffffff0 );
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PROVIDE( fromhost = 0xfffffff8 );
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}
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@ -0,0 +1,119 @@
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// See LICENSE for license details.
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#ifndef _ISS_PLATFORM_H
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#define _ISS_PLATFORM_H
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// Some things missing from the official encoding.h
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#define MCAUSE_INT 0x80000000
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#define MCAUSE_CAUSE 0x7FFFFFFF
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#include "ehrenberg/const.h"
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#include "ehrenberg/devices.h"
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/****************************************************************************
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* Platform definitions
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*****************************************************************************/
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// Memory map
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#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
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#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
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#define OTP_MMAP_ADDR _AC(0x00020000,UL)
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#define CLINT_BASE_ADDR _AC(0x02000000,UL)
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#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
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#define AON_BASE_ADDR _AC(0x10000000,UL)
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#define PRCI_BASE_ADDR _AC(0x10008000,UL)
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#define OTP_BASE_ADDR _AC(0x10010000,UL)
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#define GPIO_BASE_ADDR _AC(0x10012000,UL)
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#define UART0_BASE_ADDR _AC(0x10013000,UL)
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#define SPI0_BASE_ADDR _AC(0x10014000,UL)
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#define PWM0_BASE_ADDR _AC(0x10015000,UL)
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#define UART1_BASE_ADDR _AC(0x10023000,UL)
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#define SPI1_BASE_ADDR _AC(0x10024000,UL)
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#define PWM1_BASE_ADDR _AC(0x10025000,UL)
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#define SPI2_BASE_ADDR _AC(0x10034000,UL)
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#define PWM2_BASE_ADDR _AC(0x10035000,UL)
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#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
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#define MEM_BASE_ADDR _AC(0x80000000,UL)
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// IOF masks
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#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
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#define SPI11_NUM_SS (4)
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#define IOF_SPI1_SS0 (2u)
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#define IOF_SPI1_SS1 (8u)
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#define IOF_SPI1_SS2 (9u)
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#define IOF_SPI1_SS3 (10u)
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#define IOF_SPI1_MOSI (3u)
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#define IOF_SPI1_MISO (4u)
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#define IOF_SPI1_SCK (5u)
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#define IOF_SPI1_DQ0 (3u)
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#define IOF_SPI1_DQ1 (4u)
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#define IOF_SPI1_DQ2 (6u)
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#define IOF_SPI1_DQ3 (7u)
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#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
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#define SPI2_NUM_SS (1)
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#define IOF_SPI2_SS0 (26u)
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#define IOF_SPI2_MOSI (27u)
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#define IOF_SPI2_MISO (28u)
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#define IOF_SPI2_SCK (29u)
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#define IOF_SPI2_DQ0 (27u)
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#define IOF_SPI2_DQ1 (28u)
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#define IOF_SPI2_DQ2 (30u)
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#define IOF_SPI2_DQ3 (31u)
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//#define IOF0_I2C_MASK _AC(0x00003000,UL)
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#define IOF0_UART0_MASK _AC(0x00030000, UL)
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#define IOF_UART0_RX (16u)
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#define IOF_UART0_TX (17u)
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#define IOF0_UART1_MASK _AC(0x03000000, UL)
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#define IOF_UART1_RX (24u)
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#define IOF_UART1_TX (25u)
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#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
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#define IOF1_PWM1_MASK _AC(0x00780000, UL)
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#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
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// Interrupt numbers
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#define INT_RESERVED 0
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#define INT_WDOGCMP 1
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#define INT_RTCCMP 2
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#define INT_UART0_BASE 3
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#define INT_UART1_BASE 4
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#define INT_SPI0_BASE 5
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#define INT_SPI1_BASE 6
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#define INT_SPI2_BASE 7
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#define INT_GPIO_BASE 8
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#define INT_PWM0_BASE 40
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#define INT_PWM1_BASE 44
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#define INT_PWM2_BASE 48
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// Helper functions
|
||||
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
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#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
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#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
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#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
|
||||
#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
|
||||
#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
|
||||
#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
|
||||
#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
|
||||
#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
|
||||
#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
|
||||
#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void init_pll(void);
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _ISS_PLATFORM_H */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
// See LICENSE for license details.
|
||||
/* Derived from <linux/const.h> */
|
||||
|
||||
#ifndef _SIFIVE_CONST_H
|
||||
#define _SIFIVE_CONST_H
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#define _AC(X,Y) X
|
||||
#define _AT(T,X) X
|
||||
#else
|
||||
#define _AC(X,Y) (X##Y)
|
||||
#define _AT(T,X) ((T)(X))
|
||||
#endif /* !__ASSEMBLER__*/
|
||||
|
||||
#define _BITUL(x) (_AC(1,UL) << (x))
|
||||
#define _BITULL(x) (_AC(1,ULL) << (x))
|
||||
|
||||
#endif /* _SIFIVE_CONST_H */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* devices.c
|
||||
*
|
||||
* Created on: Aug 15, 2020
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef _BSP_EHRENBERG_DEVICES_C_
|
||||
#define _BSP_EHRENBERG_DEVICES_C_
|
||||
|
||||
#define APB_BUS
|
||||
|
||||
#include "devices/gpio.h"
|
||||
#include "devices/interrupt.h"
|
||||
#include "devices/timer.h"
|
||||
#include "devices/uart.h"
|
||||
#include "devices/qspi.h"
|
||||
|
||||
#define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR))
|
||||
|
||||
#define APB_BASE 0xF0000000
|
||||
#define TIMER_BASE (APB_BASE+0x30000)
|
||||
|
||||
#define gpio_a PERIPH(gpio_t, APB_BASE+0x00000)
|
||||
//#define gpio_b PERIPH(gpio_t, APB_BASE+0x10000)
|
||||
#define uart PERIPH(uart_t, APB_BASE+0x10000)
|
||||
#define prescaler PERIPH(uart_t, TIMER_BASE+0x0)
|
||||
#define timer_a PERIPH(uart_t, TIMER_BASE+0x10)
|
||||
#define timer_b PERIPH(uart_t, TIMER_BASE+0x20)
|
||||
#define mtimer PERIPH(mtimer_t, APB_BASE+0x30000)
|
||||
#define irq PERIPH(irq_t, APB_BASE+0x40000)
|
||||
#define qspi PERIPH(qspi_t, APB_BASE+0x50000)
|
||||
//volatile qspi_t* const qspi = (qspi_t*)(APB_BASE+0x50000);
|
||||
|
||||
#define XIP_START_LOC 0xE0040000
|
||||
|
||||
#endif /* _BSP_EHRENBERG_DEVICES_C_ */
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#ifndef _BSP_GPIO_H
|
||||
#define _BSP_GPIO_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint32_t pin_in;
|
||||
volatile uint32_t pin_out;
|
||||
volatile uint32_t out_en;
|
||||
} gpio_t;
|
||||
|
||||
inline void gpio_init(gpio_t* reg) {
|
||||
reg->out_en=0;
|
||||
reg->pin_out=0;
|
||||
}
|
||||
|
||||
#endif /* _BSP_GPIO_H */
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#ifndef _BSP_INTERRUPT_H
|
||||
#define _BSP_INTERRUPT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint32_t ip;
|
||||
volatile uint32_t ie;
|
||||
} irq_t;
|
||||
|
||||
inline void irq_init(irq_t* reg){
|
||||
reg->ie = 0;
|
||||
reg->ip = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
#endif /* _BSP_INTERRUPT_H */
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
#ifndef _BSP_QSPI_H
|
||||
#define _BSP_QSPI_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define __IO volatile
|
||||
|
||||
typedef struct {
|
||||
__IO uint32_t data; // 0x0/0: data, 8bits, 8:write, 9:read, 11:data/ctrl, 31:rxdata valid
|
||||
__IO uint32_t status; // 0x4/0: txavail, 16: rxused
|
||||
__IO uint32_t config; // 0x8/0:1 cpol/cpha, 4: transfer mode (0-FullDuplex)
|
||||
__IO uint32_t intr; // 0xc/0: txien, 1: rxien, 8: txip, 9: rxip, 16: valid?
|
||||
__IO uint32_t __fill0[4];
|
||||
__IO uint32_t clk_divider; // 0x20/0: sclkToogle
|
||||
// ssGen config
|
||||
__IO uint32_t ss_setup; // 0x24/0: setup
|
||||
__IO uint32_t ss_hold; // 0x28/0: hold
|
||||
__IO uint32_t ss_disable; // 0x2c/0: disable
|
||||
__IO uint32_t ss_activeHigh; // 0x30/0: disable
|
||||
__IO uint32_t __fill1[3];
|
||||
__IO uint32_t xip_enable; // 0x40/0: enable
|
||||
__IO uint32_t xip_instr; // 0x44/0:7 data, 8: enable, 16:23 dummy data, 24:27 dummy count
|
||||
__IO uint32_t xip_mode; // 0x48/0: instr transfer mode, 8: addr transfer mode, 16: dummy transfer mode, 24: data transfer mode
|
||||
__IO uint32_t __fill2[2];
|
||||
__IO uint32_t xip_write32; // 0x50
|
||||
__IO uint32_t xip_readwrite32; // 0x54
|
||||
__IO uint32_t xip_read32; // 0x58
|
||||
} __attribute((__packed__)) qspi_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t cpol;
|
||||
uint32_t cpha;
|
||||
uint32_t mode;
|
||||
uint32_t clkDivider;
|
||||
uint32_t ssSetup;
|
||||
uint32_t ssHold;
|
||||
uint32_t ssDisable;
|
||||
} spi_cfg;
|
||||
|
||||
#define SPI_CMD_WRITE (1 << 8)
|
||||
#define SPI_CMD_READ (1 << 9)
|
||||
#define SPI_CMD_SS (1 << 11)
|
||||
|
||||
#define SPI_RSP_VALID (1 << 31)
|
||||
|
||||
#define SPI_STATUS_CMD_INT_ENABLE = (1 << 0)
|
||||
#define SPI_STATUS_RSP_INT_ENABLE = (1 << 1)
|
||||
#define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
|
||||
#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
|
||||
|
||||
static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
|
||||
reg->config = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
|
||||
reg->clk_divider = config->clkDivider;
|
||||
reg->ss_setup = config->ssSetup;
|
||||
reg->ss_hold = config->ssHold;
|
||||
reg->ss_disable =config->ssDisable;
|
||||
}
|
||||
|
||||
static inline void spi_init(volatile qspi_t* spi){
|
||||
spi_cfg spiCfg;
|
||||
spiCfg.cpol = 0;
|
||||
spiCfg.cpha = 0;
|
||||
spiCfg.mode = 0;
|
||||
spiCfg.clkDivider = 2;
|
||||
spiCfg.ssSetup = 2;
|
||||
spiCfg.ssHold = 2;
|
||||
spiCfg.ssDisable = 2;
|
||||
spi_configure(spi, &spiCfg);
|
||||
}
|
||||
|
||||
static inline uint32_t spi_cmd_avail(volatile qspi_t* reg){
|
||||
return reg->status & 0xFFFF;
|
||||
}
|
||||
static inline uint32_t spi_rsp_occupied(volatile qspi_t* reg){
|
||||
return reg->status >> 16;
|
||||
}
|
||||
|
||||
static inline void spi_write(volatile qspi_t* reg, uint8_t data){
|
||||
while(spi_cmd_avail(reg) == 0);
|
||||
reg->data = data | SPI_CMD_WRITE;
|
||||
}
|
||||
|
||||
static inline uint8_t spi_write_read(volatile qspi_t* reg, uint8_t data){
|
||||
while(spi_cmd_avail(reg) == 0);
|
||||
reg->data = data | SPI_CMD_READ | SPI_CMD_WRITE;
|
||||
while(spi_rsp_occupied(reg) == 0);
|
||||
return reg->data;
|
||||
}
|
||||
|
||||
|
||||
static inline uint8_t spi_read(volatile qspi_t* reg){
|
||||
while(spi_cmd_avail(reg) == 0);
|
||||
reg->data = SPI_CMD_READ;
|
||||
while(spi_rsp_occupied(reg) == 0);
|
||||
while((reg->data & 0x80000000)==0);
|
||||
return reg->data;
|
||||
}
|
||||
|
||||
static inline void spi_select(volatile qspi_t* reg, uint32_t slaveId){
|
||||
while(spi_cmd_avail(reg) == 0);
|
||||
reg->data = slaveId | 0x80 | SPI_CMD_SS;
|
||||
}
|
||||
|
||||
static inline void spi_deselect(volatile qspi_t* reg, uint32_t slaveId){
|
||||
while(spi_cmd_avail(reg) == 0);
|
||||
reg->data = slaveId | SPI_CMD_SS;
|
||||
}
|
||||
|
||||
static inline void spi_wait_tx_idle(volatile qspi_t* reg){
|
||||
while(spi_cmd_avail(reg) < 0x20);
|
||||
}
|
||||
#endif /* _BSP_QSPI_H */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
#ifndef _BSP_TIMER_H
|
||||
#define _BSP_TIMER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint32_t mtime; // 0x0:0
|
||||
volatile uint32_t mtimeh; // 0x4:0
|
||||
volatile uint32_t mtimecmp; // 0x8:0
|
||||
volatile uint32_t mtimecmph; // 0xc:0
|
||||
} mtimer_t;
|
||||
|
||||
#ifndef APB_BUS
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint16_t count;
|
||||
} prescaler_t;
|
||||
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint16_t clk_en; // 0x0:0, 0->always, 1->prescaler
|
||||
volatile uint16_t clr_en; // 0x2:0, 0->on overflow
|
||||
volatile uint32_t limit; // 0x4:0, upper limit of counter
|
||||
volatile uint32_t timer_value; // 0x8:0 current timer value
|
||||
} timer_a_t;
|
||||
|
||||
#else
|
||||
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint32_t LIMIT;
|
||||
} prescaler_t;
|
||||
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint32_t CLEARS_TICKS; // 0x0/0:0->always, 1->prescaler; 16:0->on overflow
|
||||
volatile uint32_t LIMIT; // 0x4/0 upper limit of counter
|
||||
volatile uint32_t VALUE; // 0x8/0 current timer value
|
||||
} timer_a_t;
|
||||
|
||||
inline void prescaler_init(prescaler_t* reg){
|
||||
(void)reg;
|
||||
}
|
||||
|
||||
inline void timer_init(timer_a_t *reg){
|
||||
reg->CLEARS_TICKS = 0;
|
||||
reg->VALUE = 0;
|
||||
}
|
||||
|
||||
inline void mtimer_init(mtimer_t *reg){
|
||||
reg->mtimecmph = UINT32_MAX;
|
||||
reg->mtimecmp = UINT32_MAX;
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* _BSP_TIMER_H */
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
#ifndef _BSP_UART_H
|
||||
#define _BSP_UART_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
enum uart_parity_e {NONE = 0, EVEN = 1, ODD = 2};
|
||||
enum uart_stop_e {ONE = 0, TWO = 1};
|
||||
|
||||
#ifndef APB_BUS
|
||||
typedef struct __attribute((__packed__)){
|
||||
// 0x0
|
||||
volatile uint16_t rx_tx_reg; // 8bit, 0x0
|
||||
volatile uint16_t rx_avail; // 1bit, 0x0:16
|
||||
// 0x4
|
||||
volatile uint16_t irq_ctrl; // 0->tx_ie, 1->rx_ie, 8->tx_ip, 9->rx_ip
|
||||
volatile uint8_t num_tx_avail; // 8bit, 0x4:16
|
||||
volatile uint8_t num_rx_avail; // 8bit, 0x4:24
|
||||
volatile uint32_t dummy;
|
||||
// 0xc
|
||||
volatile uint8_t clock_div; // 3bit, 0xc:0
|
||||
volatile uint8_t frame; // 2bit, 0xc:8
|
||||
volatile uint8_t stop_bits; // 1bit, 0xc:16
|
||||
// 0x10
|
||||
volatile uint8_t status; // readError->0, readOverflowError->1,
|
||||
volatile uint8_t active; // rx_active->0, tx_active-1, set_tx_active->2, clear_tx_active->3
|
||||
} uart_t;
|
||||
#else
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint32_t DATA;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t CLOCK_DIVIDER;
|
||||
volatile uint32_t FRAME_CONFIG;
|
||||
} uart_t;
|
||||
|
||||
|
||||
typedef struct __attribute((__packed__)) {
|
||||
uint32_t data_length;
|
||||
enum uart_parity_e parity;
|
||||
enum uart_stop_e stop;
|
||||
uint32_t clock_divider;
|
||||
} uart_config_t;
|
||||
|
||||
static inline uint32_t uart_get_tx_free(volatile uart_t *reg){
|
||||
return (reg->STATUS >> 16) & 0xFF;
|
||||
}
|
||||
|
||||
static inline uint32_t uart_get_rx_avail(volatile uart_t *reg){
|
||||
return reg->STATUS >> 24;
|
||||
}
|
||||
|
||||
static void uart_write(volatile uart_t *reg, uint8_t data){
|
||||
while(uart_get_tx_free(reg) == 0);
|
||||
reg->DATA = data;
|
||||
}
|
||||
|
||||
static inline uint8_t uart_read(volatile uart_t *reg){
|
||||
uint32_t res = reg->DATA;
|
||||
while((res&0x10000) == 0) res = reg->DATA;
|
||||
return res;
|
||||
}
|
||||
|
||||
static inline void uart_set_config(volatile uart_t *reg, uart_config_t *config){
|
||||
reg->CLOCK_DIVIDER = config->clock_divider;
|
||||
reg->FRAME_CONFIG = ((config->data_length-1) << 0) | (config->parity << 8) | (config->stop << 16);
|
||||
}
|
||||
#endif
|
||||
#endif /* _BSP_UART_H */
|
||||
|
|
@ -21,6 +21,10 @@ size_t strnlen (const char *str, size_t n)
|
|||
return str - start;
|
||||
}
|
||||
|
||||
static void fprintf_putch(int ch, void** data)
|
||||
{
|
||||
putchar(ch);
|
||||
}
|
||||
static void sprintf_putch(int ch, void** data)
|
||||
{
|
||||
char** pstr = (char**)data;
|
||||
|
|
@ -100,13 +104,13 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
|
|||
{
|
||||
register const char* p;
|
||||
const char* last_fmt;
|
||||
register int ch, err;
|
||||
register int ch;
|
||||
unsigned long num;
|
||||
int base, lflag, width, precision, altflag;
|
||||
int base, lflag, width, precision;
|
||||
char padc;
|
||||
|
||||
while (1) {
|
||||
while ((ch = *(unsigned char *) fmt) != '%') {
|
||||
while ((ch = *(const char *) fmt) != '%') {
|
||||
if (ch == '\0')
|
||||
return;
|
||||
fmt++;
|
||||
|
|
@ -120,9 +124,8 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
|
|||
width = -1;
|
||||
precision = -1;
|
||||
lflag = 0;
|
||||
altflag = 0;
|
||||
reswitch:
|
||||
switch (ch = *(unsigned char *) fmt++) {
|
||||
switch (ch = *(const char *) fmt++) {
|
||||
|
||||
// flag to pad on the right
|
||||
case '-':
|
||||
|
|
@ -162,7 +165,6 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
|
|||
goto reswitch;
|
||||
|
||||
case '#':
|
||||
altflag = 1;
|
||||
goto reswitch;
|
||||
|
||||
process_precision:
|
||||
|
|
@ -170,24 +172,17 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
|
|||
width = precision, precision = -1;
|
||||
goto reswitch;
|
||||
|
||||
// long flag
|
||||
case 'l':
|
||||
case 'l': // long flag
|
||||
if (lflag)
|
||||
goto bad;
|
||||
goto reswitch;
|
||||
|
||||
// character
|
||||
case 'c':
|
||||
case 'c': // character
|
||||
putch(va_arg(ap, int), putdat);
|
||||
break;
|
||||
|
||||
// double
|
||||
case 'f':
|
||||
case 'f': // double
|
||||
print_double(putch, putdat, va_arg(ap, double), width, precision);
|
||||
break;
|
||||
|
||||
// string
|
||||
case 's':
|
||||
case 's': // string
|
||||
if ((p = va_arg(ap, char *)) == NULL)
|
||||
p = "(null)";
|
||||
if (width > 0 && padc != '-')
|
||||
|
|
@ -200,9 +195,7 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
|
|||
for (; width > 0; width--)
|
||||
putch(' ', putdat);
|
||||
break;
|
||||
|
||||
// (signed) decimal
|
||||
case 'd':
|
||||
case 'd': // (signed) decimal
|
||||
num = getint(&ap, lflag);
|
||||
if ((long) num < 0) {
|
||||
putch('-', putdat);
|
||||
|
|
@ -210,41 +203,30 @@ static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt
|
|||
}
|
||||
base = 10;
|
||||
goto signed_number;
|
||||
|
||||
// unsigned decimal
|
||||
case 'u':
|
||||
case 'u': // unsigned decimal
|
||||
base = 10;
|
||||
goto unsigned_number;
|
||||
|
||||
// (unsigned) octal
|
||||
case 'o':
|
||||
case 'o': // (unsigned) octal
|
||||
// should do something with padding so it's always 3 octits
|
||||
base = 8;
|
||||
goto unsigned_number;
|
||||
|
||||
// pointer
|
||||
case 'p':
|
||||
case 'p':// pointer
|
||||
lflag = 1;
|
||||
putch('0', putdat);
|
||||
putch('x', putdat);
|
||||
/* fall through to 'x' */
|
||||
|
||||
// (unsigned) hexadecimal
|
||||
case 'x':
|
||||
__attribute__((fallthrough));
|
||||
case 'x': // (unsigned) hexadecimal
|
||||
base = 16;
|
||||
unsigned_number:
|
||||
unsigned_number:
|
||||
num = getuint(&ap, lflag);
|
||||
signed_number:
|
||||
signed_number:
|
||||
printnum(putch, putdat, num, base, width, padc);
|
||||
break;
|
||||
|
||||
// escaped '%' character
|
||||
case '%':
|
||||
case '%': // escaped '%' character
|
||||
putch(ch, putdat);
|
||||
break;
|
||||
|
||||
// unrecognized escape sequence - just print it literally
|
||||
default:
|
||||
default: // unrecognized escape sequence - just print it literally
|
||||
bad:
|
||||
putch('%', putdat);
|
||||
fmt = last_fmt;
|
||||
|
|
@ -258,7 +240,7 @@ int __wrap_printf(const char* fmt, ...)
|
|||
va_list ap;
|
||||
va_start(ap, fmt);
|
||||
|
||||
vprintfmt((void*)putchar, 0, fmt, ap);
|
||||
vprintfmt(fprintf_putch, 0, fmt, ap);
|
||||
|
||||
va_end(ap);
|
||||
return 0; // incorrect return value, but who cares, anyway?
|
||||
|
|
|
|||
|
|
@ -12,6 +12,10 @@
|
|||
int __wrap_puts(const char *s)
|
||||
{
|
||||
while (*s != '\0') {
|
||||
#if defined(BOARD_ehrenberg)
|
||||
while (uart_get_tx_free(uart)==0) ;
|
||||
uart_write(uart, *s);
|
||||
#else
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = *s;
|
||||
|
||||
|
|
@ -19,7 +23,7 @@ int __wrap_puts(const char *s)
|
|||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = '\r';
|
||||
}
|
||||
|
||||
#endif
|
||||
++s;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -4,32 +4,40 @@
|
|||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#if defined(BOARD_ehrenberg)
|
||||
#include "platform.h"
|
||||
#endif
|
||||
#include "platform.h"
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
ssize_t __wrap_read(int fd, void* ptr, size_t len)
|
||||
{
|
||||
#if defined(BOARD_hifive1)
|
||||
uint8_t * current = (uint8_t *)ptr;
|
||||
#if defined(BOARD_hifive1)
|
||||
volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
|
||||
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
|
||||
#else
|
||||
uint8_t * current = (uint8_t *)ptr;
|
||||
#elif !defined(BOARD_ehrenberg)
|
||||
volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
|
||||
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
|
||||
#endif
|
||||
|
||||
ssize_t result = 0;
|
||||
|
||||
if (isatty(fd)) {
|
||||
#if defined(BOARD_ehrenberg)
|
||||
for (current = (uint8_t *)ptr;
|
||||
(current < ((uint8_t *)ptr) + len) && (uart_get_rx_avail(uart) > 0);
|
||||
current ++) {
|
||||
*current = uart_read(uart);
|
||||
result++;
|
||||
}
|
||||
#else
|
||||
for (current = (uint8_t *)ptr;
|
||||
(current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
|
||||
current ++) {
|
||||
*current = *uart_rx;
|
||||
result++;
|
||||
}
|
||||
#endif
|
||||
return result;
|
||||
}
|
||||
return _stub(EBADF);
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ void *__wrap_sbrk(ptrdiff_t incr)
|
|||
static char *curbrk = _end;
|
||||
|
||||
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
|
||||
return NULL - 1;
|
||||
return (void*)- 1;
|
||||
|
||||
curbrk += incr;
|
||||
return curbrk - incr;
|
||||
|
|
|
|||
|
|
@ -11,21 +11,29 @@
|
|||
|
||||
ssize_t __wrap_write(int fd, const void* ptr, size_t len)
|
||||
{
|
||||
const uint8_t * current = (const char *)ptr;
|
||||
const uint8_t * current = (const uint8_t *)ptr;
|
||||
if (isatty(fd)) {
|
||||
for (size_t jj = 0; jj < len; jj++) {
|
||||
#if defined(BOARD_ehrenberg)
|
||||
while (uart_get_tx_free(uart)==0) ;
|
||||
uart_write(uart, current[jj]);
|
||||
if (current[jj] == '\n') {
|
||||
while (uart_get_tx_free(uart)==0) ;
|
||||
uart_write(uart, '\r');
|
||||
}
|
||||
#else
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = current[jj];
|
||||
|
||||
if (isatty(fd)) {
|
||||
for (size_t jj = 0; jj < len; jj++) {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = current[jj];
|
||||
|
||||
if (current[jj] == '\n') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = '\r';
|
||||
}
|
||||
if (current[jj] == '\n') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = '\r';
|
||||
}
|
||||
#endif
|
||||
}
|
||||
return len;
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
return _stub(EBADF);
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(write);
|
||||
|
|
|
|||
Loading…
Reference in New Issue