113 lines
3.5 KiB
C
113 lines
3.5 KiB
C
#ifndef _BSP_QSPI_H
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#define _BSP_QSPI_H
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#include <stdint.h>
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#define __IO volatile
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typedef struct {
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__IO uint32_t data; // 0x0/0: data, 8bits, 8:write, 9:read, 11:data/ctrl, 31:rxdata valid
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__IO uint32_t status; // 0x4/0: txavail, 16: rxused
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__IO uint32_t config; // 0x8/0:1 cpol/cpha, 4: transfer mode (0-FullDuplex)
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__IO uint32_t intr; // 0xc/0: txien, 1: rxien, 8: txip, 9: rxip, 16: valid?
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__IO uint32_t __fill0[4];
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__IO uint32_t clk_divider; // 0x20/0: sclkToogle
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// ssGen config
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__IO uint32_t ss_setup; // 0x24/0: setup
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__IO uint32_t ss_hold; // 0x28/0: hold
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__IO uint32_t ss_disable; // 0x2c/0: disable
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__IO uint32_t ss_activeHigh; // 0x30/0: disable
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__IO uint32_t __fill1[3];
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__IO uint32_t xip_enable; // 0x40/0: enable
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__IO uint32_t xip_instr; // 0x44/0:7 data, 8: enable, 16:23 dummy data, 24:27 dummy count
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__IO uint32_t xip_mode; // 0x48/0: instr transfer mode, 8: addr transfer mode, 16: dummy transfer mode, 24: data transfer mode
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__IO uint32_t __fill2[2];
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__IO uint32_t xip_write32; // 0x50
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__IO uint32_t xip_readwrite32; // 0x54
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__IO uint32_t xip_read32; // 0x58
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} __attribute((__packed__)) qspi_t;
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typedef struct {
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uint32_t cpol;
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uint32_t cpha;
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uint32_t mode;
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uint32_t clkDivider;
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uint32_t ssSetup;
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uint32_t ssHold;
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uint32_t ssDisable;
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} spi_cfg;
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#define SPI_CMD_WRITE (1 << 8)
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#define SPI_CMD_READ (1 << 9)
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#define SPI_CMD_SS (1 << 11)
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#define SPI_RSP_VALID (1 << 31)
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#define SPI_STATUS_CMD_INT_ENABLE = (1 << 0)
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#define SPI_STATUS_RSP_INT_ENABLE = (1 << 1)
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#define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
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#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
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static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
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reg->config = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
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reg->clk_divider = config->clkDivider;
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reg->ss_setup = config->ssSetup;
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reg->ss_hold = config->ssHold;
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reg->ss_disable =config->ssDisable;
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}
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static inline void spi_init(volatile qspi_t* spi){
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spi_cfg spiCfg;
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spiCfg.cpol = 0;
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spiCfg.cpha = 0;
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spiCfg.mode = 0;
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spiCfg.clkDivider = 2;
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spiCfg.ssSetup = 2;
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spiCfg.ssHold = 2;
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spiCfg.ssDisable = 2;
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spi_configure(spi, &spiCfg);
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}
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static inline uint32_t spi_cmd_avail(volatile qspi_t* reg){
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return reg->status & 0xFFFF;
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}
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static inline uint32_t spi_rsp_occupied(volatile qspi_t* reg){
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return reg->status >> 16;
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}
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static inline void spi_write(volatile qspi_t* reg, uint8_t data){
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while(spi_cmd_avail(reg) == 0);
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reg->data = data | SPI_CMD_WRITE;
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}
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static inline uint8_t spi_write_read(volatile qspi_t* reg, uint8_t data){
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while(spi_cmd_avail(reg) == 0);
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reg->data = data | SPI_CMD_READ | SPI_CMD_WRITE;
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while(spi_rsp_occupied(reg) == 0);
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return reg->data;
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}
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static inline uint8_t spi_read(volatile qspi_t* reg){
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while(spi_cmd_avail(reg) == 0);
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reg->data = SPI_CMD_READ;
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while(spi_rsp_occupied(reg) == 0);
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while((reg->data & 0x80000000)==0);
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return reg->data;
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}
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static inline void spi_select(volatile qspi_t* reg, uint32_t slaveId){
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while(spi_cmd_avail(reg) == 0);
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reg->data = slaveId | 0x80 | SPI_CMD_SS;
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}
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static inline void spi_deselect(volatile qspi_t* reg, uint32_t slaveId){
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while(spi_cmd_avail(reg) == 0);
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reg->data = slaveId | SPI_CMD_SS;
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}
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static inline void spi_wait_tx_idle(volatile qspi_t* reg){
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while(spi_cmd_avail(reg) < 0x20);
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}
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#endif /* _BSP_QSPI_H */
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