adds missing peripheral header files

2025-02-12 08:58:43 +01:00 · 2025-02-12 08:58:43 +01:00 · bfc7e9f00b
commit bfc7e9f00b
parent fcf8543c06
2 changed files with 309 additions and 0 deletions
--- a/include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
+++ b/include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
@ -0,0 +1,197 @@
+/*
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2025-02-12 08:56:43 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+#define _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t REG_SEND;
+    volatile uint32_t REG_HEADER;
+    volatile uint32_t REG_ACK;
+    volatile uint32_t REG_RECV_ID;
+    volatile uint32_t REG_RECV_PAYLOAD;
+    uint8_t fill0[12];
+    volatile uint32_t REG_PAYLOAD_0;
+    volatile uint32_t REG_PAYLOAD_1;
+    volatile uint32_t REG_PAYLOAD_2;
+    volatile uint32_t REG_PAYLOAD_3;
+    volatile uint32_t REG_PAYLOAD_4;
+    volatile uint32_t REG_PAYLOAD_5;
+    volatile uint32_t REG_PAYLOAD_6;
+    volatile uint32_t REG_PAYLOAD_7;
+}mkcontrolclusterstreamcontroller_t;
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_MASK 0x1
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
+inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+     reg->REG_SEND = value;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg){
+     return reg->REG_HEADER;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+     reg->REG_HEADER = value;
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 0) & 0xf;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 4) & 0xf;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 8) & 0x7;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_HEADER >> 11) & 0x3;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
+inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+     reg->REG_ACK = value;
+}
+inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
+    reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
+     return reg->REG_RECV_ID;
+}
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_RECV_ID >> 0) & 0xf;
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
+inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg){
+    return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */
--- a/include/ehrenberg/devices/gen/sysctrl.h
+++ b/include/ehrenberg/devices/gen/sysctrl.h
@ -0,0 +1,112 @@
+/*
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2025-02-12 08:56:43 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_SYSCTRL_H
+#define _BSP_SYSCTRL_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t SYSCTRL;
+    volatile uint32_t PLLCTRL;
+    volatile uint32_t AXI_BACKUP;
+}sysctrl_t;
+
+#define SYSCTRL_SYSCTRL_CC_RESET_OFFS 0
+#define SYSCTRL_SYSCTRL_CC_RESET_MASK 0x3
+#define SYSCTRL_SYSCTRL_CC_RESET(V) ((V & SYSCTRL_SYSCTRL_CC_RESET_MASK) << SYSCTRL_SYSCTRL_CC_RESET_OFFS)
+
+#define SYSCTRL_SYSCTRL_MEM_RESET_OFFS 2
+#define SYSCTRL_SYSCTRL_MEM_RESET_MASK 0x1
+#define SYSCTRL_SYSCTRL_MEM_RESET(V) ((V & SYSCTRL_SYSCTRL_MEM_RESET_MASK) << SYSCTRL_SYSCTRL_MEM_RESET_OFFS)
+
+#define SYSCTRL_PLLCTRL_P_COUNTER_OFFS 0
+#define SYSCTRL_PLLCTRL_P_COUNTER_MASK 0x3f
+#define SYSCTRL_PLLCTRL_P_COUNTER(V) ((V & SYSCTRL_PLLCTRL_P_COUNTER_MASK) << SYSCTRL_PLLCTRL_P_COUNTER_OFFS)
+
+#define SYSCTRL_PLLCTRL_S_COUNTER_OFFS 6
+#define SYSCTRL_PLLCTRL_S_COUNTER_MASK 0x3
+#define SYSCTRL_PLLCTRL_S_COUNTER(V) ((V & SYSCTRL_PLLCTRL_S_COUNTER_MASK) << SYSCTRL_PLLCTRL_S_COUNTER_OFFS)
+
+#define SYSCTRL_PLLCTRL_CLK_SEL_OFFS 8
+#define SYSCTRL_PLLCTRL_CLK_SEL_MASK 0x3
+#define SYSCTRL_PLLCTRL_CLK_SEL(V) ((V & SYSCTRL_PLLCTRL_CLK_SEL_MASK) << SYSCTRL_PLLCTRL_CLK_SEL_OFFS)
+
+#define SYSCTRL_PLLCTRL_LOCKED_OFFS 31
+#define SYSCTRL_PLLCTRL_LOCKED_MASK 0x1
+#define SYSCTRL_PLLCTRL_LOCKED(V) ((V & SYSCTRL_PLLCTRL_LOCKED_MASK) << SYSCTRL_PLLCTRL_LOCKED_OFFS)
+
+#define SYSCTRL_AXI_BACKUP_OFFS 0
+#define SYSCTRL_AXI_BACKUP_MASK 0xf
+#define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS)
+
+//SYSCTRL_SYSCTRL
+inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){
+     return reg->SYSCTRL;
+}
+inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value){
+     reg->SYSCTRL = value;
+}
+inline uint32_t get_sysctrl_sysctrl_cc_reset(volatile sysctrl_t* reg){
+    return (reg->SYSCTRL >> 0) & 0x3;
+}
+inline void set_sysctrl_sysctrl_cc_reset(volatile sysctrl_t* reg, uint8_t value){
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg){
+    return (reg->SYSCTRL >> 2) & 0x1;
+}
+inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value){
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 2)) | (value << 2);
+}
+
+//SYSCTRL_PLLCTRL
+inline uint32_t get_sysctrl_pllctrl(volatile sysctrl_t* reg){
+     return reg->PLLCTRL;
+}
+inline void set_sysctrl_pllctrl(volatile sysctrl_t* reg, uint32_t value){
+     reg->PLLCTRL = value;
+}
+inline uint32_t get_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 0) & 0x3f;
+}
+inline void set_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg, uint8_t value){
+    reg->PLLCTRL = (reg->PLLCTRL & ~(0x3fU << 0)) | (value << 0);
+}
+inline uint32_t get_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 6) & 0x3;
+}
+inline void set_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg, uint8_t value){
+    reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 6)) | (value << 6);
+}
+inline uint32_t get_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 8) & 0x3;
+}
+inline void set_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg, uint8_t value){
+    reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 8)) | (value << 8);
+}
+inline uint32_t get_sysctrl_pllctrl_locked(volatile sysctrl_t* reg){
+    return (reg->PLLCTRL >> 31) & 0x1;
+}
+
+//SYSCTRL_AXI_BACKUP
+inline uint32_t get_sysctrl_axi_backup(volatile sysctrl_t* reg){
+     return reg->AXI_BACKUP;
+}
+inline void set_sysctrl_axi_backup(volatile sysctrl_t* reg, uint32_t value){
+     reg->AXI_BACKUP = value;
+}
+inline uint32_t get_sysctrl_axi_backup_page(volatile sysctrl_t* reg){
+    return (reg->AXI_BACKUP >> 0) & 0xf;
+}
+inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value){
+    reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0xfU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_SYSCTRL_H */