removes tgc-vp in favor of ehrenberg/tgc_vp
This commit is contained in:
parent
28bf59f0e3
commit
a45fee1f7e
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/*.o
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@ -1,116 +0,0 @@
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#include <stdint.h>
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#include <stdio.h>
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#include <unistd.h>
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#include "platform.h"
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#include "encoding.h"
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extern int main(int argc, char** argv);
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extern void trap_entry();
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static unsigned long mtime_lo(void)
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{
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unsigned long ret;
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__asm volatile("rdtime %0":"=r"(ret));
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return ret;
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}
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#if __riscv_xlen==32
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static uint32_t mtime_hi(void)
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{
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unsigned long ret;
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__asm volatile("rdtimeh %0":"=r"(ret));
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return ret;
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}
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uint64_t get_timer_value()
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{
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while (1) {
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uint32_t hi = mtime_hi();
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uint32_t lo = mtime_lo();
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if (hi == mtime_hi())
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return ((uint64_t)hi << 32) | lo;
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}
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}
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#elif __riscv_xlen==64
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uint64_t get_timer_value()
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{
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return mtime_lo();
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}
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#endif
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unsigned long get_timer_freq()
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{
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return 32768;
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}
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unsigned long get_cpu_freq()
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{
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return 10000000;
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}
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void init_pll(void){
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}
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static void uart_init(size_t baud_rate)
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{
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GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
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GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
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UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
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UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
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}
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#ifdef USE_PLIC
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extern void handle_m_ext_interrupt();
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#endif
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#ifdef USE_M_TIME
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extern void handle_m_time_interrupt();
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#endif
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uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
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{
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if (0){
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#ifdef USE_PLIC
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// External Machine-Level interrupt from PLIC
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} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
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handle_m_ext_interrupt();
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#endif
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#ifdef USE_M_TIME
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// External Machine-Level interrupt from PLIC
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} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
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handle_m_time_interrupt();
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#endif
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}
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else {
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write(1, "trap\n", 5);
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_exit(1 + mcause);
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}
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return epc;
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}
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void _init()
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{
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#ifndef NO_INIT
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init_pll();
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uart_init(115200);
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printf("core freq at %d Hz\n", get_cpu_freq());
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write_csr(mtvec, &trap_entry);
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if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
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write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
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write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
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}
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#endif
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}
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void _fini()
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{
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}
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@ -1,174 +0,0 @@
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OUTPUT_ARCH( "riscv" )
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ENTRY( _start )
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MEMORY
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{
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flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 512M
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ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128K
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}
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PHDRS
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{
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flash PT_LOAD;
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ram_init PT_LOAD;
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ram PT_NULL;
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}
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SECTIONS
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{
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__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
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.init ORIGIN(flash) :
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{
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KEEP (*(SORT_NONE(.init)))
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} >flash AT>flash :flash
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.text :
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{
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*(.text.unlikely .text.unlikely.*)
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*(.text.startup .text.startup.*)
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*(.text .text.*)
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*(.gnu.linkonce.t.*)
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} >flash AT>flash :flash
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.fini :
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{
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KEEP (*(SORT_NONE(.fini)))
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} >flash AT>flash :flash
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PROVIDE (__etext = .);
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PROVIDE (_etext = .);
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rdata)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r.*)
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} >flash AT>flash :flash
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. = ALIGN(4);
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.preinit_array :
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{
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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} >flash AT>flash :flash
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.init_array :
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{
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
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PROVIDE_HIDDEN (__init_array_end = .);
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} >flash AT>flash :flash
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.fini_array :
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{
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
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KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
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PROVIDE_HIDDEN (__fini_array_end = .);
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} >flash AT>flash :flash
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.ctors :
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{
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/* gcc uses crtbegin.o to find the start of
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the constructors, so we make sure it is
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first. Because this is a wildcard, it
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doesn't matter if the user does not
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actually link against crtbegin.o; the
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linker won't look for a file to match a
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wildcard. The wildcard also means that it
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doesn't matter which directory crtbegin.o
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is in. */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*crtbegin?.o(.ctors))
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/* We don't want to include the .ctor section from
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the crtend.o file until after the sorted ctors.
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The .ctor section from the crtend file contains the
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end of ctors marker and it must be last */
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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} >flash AT>flash :flash
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.dtors :
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{
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KEEP (*crtbegin.o(.dtors))
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KEEP (*crtbegin?.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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} >flash AT>flash :flash
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.lalign :
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{
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. = ALIGN(4);
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PROVIDE( _data_lma = . );
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} >flash AT>flash :flash
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.dalign :
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{
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. = ALIGN(4);
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PROVIDE( _data = . );
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} >ram AT>flash :ram_init
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.data :
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{
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__DATA_BEGIN__ = .;
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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} >ram AT>flash :ram_init
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.srodata :
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{
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PROVIDE( _gp = . + 0x800 );
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*(.srodata.cst16)
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*(.srodata.cst8)
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*(.srodata.cst4)
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*(.srodata.cst2)
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*(.srodata .srodata.*)
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} >ram AT>flash :ram_init
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.sdata :
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{
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__SDATA_BEGIN__ = .;
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*(.sdata .sdata.*)
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*(.gnu.linkonce.s.*)
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} >ram AT>flash :ram_init
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. = ALIGN(4);
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PROVIDE( _edata = . );
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PROVIDE( edata = . );
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PROVIDE( _fbss = . );
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PROVIDE( __bss_start = . );
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.bss :
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{
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*(.sbss*)
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*(.gnu.linkonce.sb.*)
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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} >ram AT>ram :ram
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. = ALIGN(8);
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__BSS_END__ = .;
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__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
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PROVIDE( _end = . );
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PROVIDE( end = . );
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.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
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{
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PROVIDE( _heap_end = . );
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. = __stack_size;
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PROVIDE( _sp = . );
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} >ram AT>ram :ram
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PROVIDE( tohost = 0xfffffff0 );
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PROVIDE( fromhost = 0xfffffff8 );
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}
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@ -1,127 +0,0 @@
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// See LICENSE for license details.
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#ifndef _ISS_PLATFORM_H
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#define _ISS_PLATFORM_H
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// Some things missing from the official encoding.h
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#define MCAUSE_INT 0x80000000
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#define MCAUSE_CAUSE 0x7FFFFFFF
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#include "bits.h"
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#include "tgc-vp/devices/aon.h"
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#include "tgc-vp/devices/clint.h"
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#include "tgc-vp/devices/gpio.h"
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#include "tgc-vp/devices/otp.h"
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#include "tgc-vp/devices/plic.h"
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#include "tgc-vp/devices/prci.h"
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#include "tgc-vp/devices/pwm.h"
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#include "tgc-vp/devices/spi.h"
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#include "tgc-vp/devices/uart.h"
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/****************************************************************************
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* Platform definitions
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*****************************************************************************/
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// Memory map
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#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
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#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
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#define OTP_MMAP_ADDR _AC(0x00020000,UL)
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#define CLINT_BASE_ADDR _AC(0x02000000,UL)
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#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
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#define AON_BASE_ADDR _AC(0x10000000,UL)
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#define PRCI_BASE_ADDR _AC(0x10008000,UL)
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#define OTP_BASE_ADDR _AC(0x10010000,UL)
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#define GPIO_BASE_ADDR _AC(0x10012000,UL)
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#define UART0_BASE_ADDR _AC(0x10013000,UL)
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#define SPI0_BASE_ADDR _AC(0x10014000,UL)
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#define PWM0_BASE_ADDR _AC(0x10015000,UL)
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#define UART1_BASE_ADDR _AC(0x10023000,UL)
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#define SPI1_BASE_ADDR _AC(0x10024000,UL)
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#define PWM1_BASE_ADDR _AC(0x10025000,UL)
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#define SPI2_BASE_ADDR _AC(0x10034000,UL)
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#define PWM2_BASE_ADDR _AC(0x10035000,UL)
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#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
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#define MEM_BASE_ADDR _AC(0x80000000,UL)
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// IOF masks
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#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
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#define SPI11_NUM_SS (4)
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#define IOF_SPI1_SS0 (2u)
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#define IOF_SPI1_SS1 (8u)
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#define IOF_SPI1_SS2 (9u)
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#define IOF_SPI1_SS3 (10u)
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#define IOF_SPI1_MOSI (3u)
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#define IOF_SPI1_MISO (4u)
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#define IOF_SPI1_SCK (5u)
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#define IOF_SPI1_DQ0 (3u)
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#define IOF_SPI1_DQ1 (4u)
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#define IOF_SPI1_DQ2 (6u)
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#define IOF_SPI1_DQ3 (7u)
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#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
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#define SPI2_NUM_SS (1)
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#define IOF_SPI2_SS0 (26u)
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#define IOF_SPI2_MOSI (27u)
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#define IOF_SPI2_MISO (28u)
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#define IOF_SPI2_SCK (29u)
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#define IOF_SPI2_DQ0 (27u)
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#define IOF_SPI2_DQ1 (28u)
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#define IOF_SPI2_DQ2 (30u)
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#define IOF_SPI2_DQ3 (31u)
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//#define IOF0_I2C_MASK _AC(0x00003000,UL)
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#define IOF0_UART0_MASK _AC(0x00030000, UL)
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#define IOF_UART0_RX (16u)
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#define IOF_UART0_TX (17u)
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#define IOF0_UART1_MASK _AC(0x03000000, UL)
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#define IOF_UART1_RX (24u)
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#define IOF_UART1_TX (25u)
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#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
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#define IOF1_PWM1_MASK _AC(0x00780000, UL)
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#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
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// Interrupt numbers
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#define INT_RESERVED 0
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#define INT_WDOGCMP 1
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#define INT_RTCCMP 2
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#define INT_UART0_BASE 3
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#define INT_UART1_BASE 4
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#define INT_SPI0_BASE 5
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#define INT_SPI1_BASE 6
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#define INT_SPI2_BASE 7
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#define INT_GPIO_BASE 8
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#define INT_PWM0_BASE 40
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#define INT_PWM1_BASE 44
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#define INT_PWM2_BASE 48
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// Helper functions
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#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
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#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
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#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
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#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
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#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
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#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
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#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
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#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
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#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
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#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
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#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
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#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
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#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
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#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
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#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
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#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
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// Misc
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#include <stdint.h>
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void init_pll(void);
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unsigned long get_cpu_freq(void);
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unsigned long get_timer_freq(void);
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uint64_t get_timer_value(void);
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#endif /* _ISS_PLATFORM_H */
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@ -0,0 +1 @@
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ehrenberg/
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@ -1,30 +1,32 @@
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/* See LICENSE of license details. */
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#include <stdint.h>
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#include <errno.h>
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#include <unistd.h>
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#include <stdint.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include "platform.h"
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#include "stub.h"
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#include "weak_under_alias.h"
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int __wrap_puts(const char *s)
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{
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int __wrap_puts(const char *s) {
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while (*s != '\0') {
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#if defined(BOARD_ehrenberg)
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while (get_uart_rx_tx_reg_tx_free(uart)==0) ;
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#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
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while (get_uart_rx_tx_reg_tx_free(uart) == 0)
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;
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uart_write(uart, *s);
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#elif defined(BOARD_iss)
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*((uint32_t*) 0xFFFF0000) = *s;
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*((uint32_t *)0xFFFF0000) = *s;
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#elif defined(BOARD_TGCP)
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//TODO: implement
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// TODO: implement
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#else
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while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
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while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
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;
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UART0_REG(UART_REG_TXFIFO) = *s;
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|
||||
if (*s == '\n') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
|
||||
;
|
||||
UART0_REG(UART_REG_TXFIFO) = '\r';
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,59 +1,54 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
#if defined(BOARD_ehrenberg)
|
||||
#include "platform.h"
|
||||
#endif
|
||||
#include "platform.h"
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
#include <errno.h>
|
||||
#include <stdint.h>
|
||||
#include <sys/types.h>
|
||||
#include <unistd.h>
|
||||
|
||||
ssize_t __wrap_read(int fd, void* ptr, size_t len)
|
||||
{
|
||||
uint8_t * current = (uint8_t *)ptr;
|
||||
ssize_t __wrap_read(int fd, void *ptr, size_t len) {
|
||||
uint8_t *current = (uint8_t *)ptr;
|
||||
#if defined(BOARD_hifive1)
|
||||
volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
|
||||
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
|
||||
volatile uint32_t *uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
|
||||
volatile uint8_t *uart_rx_cnt =
|
||||
(uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
|
||||
#elif defined(BOARD_iss)
|
||||
volatile uint32_t * uart_rx = (uint32_t*)0xFFFF0000;
|
||||
volatile uint32_t *uart_rx = (uint32_t *)0xFFFF0000;
|
||||
#elif defined(BOARD_TGCP)
|
||||
//TODO: implement
|
||||
#elif !defined(BOARD_ehrenberg)
|
||||
volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
|
||||
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
|
||||
// TODO: implement
|
||||
#elif !defined(BOARD_ehrenberg) && !defined(BOARD_tgc_vp)
|
||||
volatile uint32_t *uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
|
||||
volatile uint8_t *uart_rx_cnt =
|
||||
(uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
|
||||
#endif
|
||||
ssize_t result = 0;
|
||||
if (isatty(fd)) {
|
||||
#if defined(BOARD_ehrenberg)
|
||||
for (current = (uint8_t *)ptr;
|
||||
(current < ((uint8_t *)ptr) + len) && (get_uart_rx_tx_reg_rx_avail(uart) > 0);
|
||||
current ++) {
|
||||
*current = uart_read(uart);
|
||||
result++;
|
||||
}
|
||||
#elif defined(BOARD_iss)
|
||||
for (current = (uint8_t *)ptr;
|
||||
(current < ((uint8_t *)ptr) + len);
|
||||
current ++) {
|
||||
*current = *uart_rx;
|
||||
result++;
|
||||
}
|
||||
#elif defined(BOARD_TGCP)
|
||||
//TODO: implement
|
||||
#else
|
||||
for (current = (uint8_t *)ptr;
|
||||
(current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
|
||||
current ++) {
|
||||
*current = *uart_rx;
|
||||
result++;
|
||||
}
|
||||
#endif
|
||||
return result;
|
||||
ssize_t result = 0;
|
||||
if (isatty(fd)) {
|
||||
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
|
||||
for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
|
||||
(get_uart_rx_tx_reg_rx_avail(uart) > 0);
|
||||
current++) {
|
||||
*current = uart_read(uart);
|
||||
result++;
|
||||
}
|
||||
return _stub(EBADF);
|
||||
#elif defined(BOARD_iss)
|
||||
for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len);
|
||||
current++) {
|
||||
*current = *uart_rx;
|
||||
result++;
|
||||
}
|
||||
#elif defined(BOARD_TGCP)
|
||||
// TODO: implement
|
||||
#else
|
||||
for (current = (uint8_t *)ptr;
|
||||
(current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); current++) {
|
||||
*current = *uart_rx;
|
||||
result++;
|
||||
}
|
||||
#endif
|
||||
return result;
|
||||
}
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(read);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,42 +1,45 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <stdint.h>
|
||||
#include <sys/types.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
ssize_t __wrap_write(int fd, const void* ptr, size_t len)
|
||||
{
|
||||
const uint8_t * current = (const uint8_t *)ptr;
|
||||
if (isatty(fd)) {
|
||||
for (size_t jj = 0; jj < len; jj++) {
|
||||
#if defined(BOARD_ehrenberg)
|
||||
while (get_uart_rx_tx_reg_tx_free(uart)==0) ;
|
||||
uart_write(uart, current[jj]);
|
||||
if (current[jj] == '\n') {
|
||||
while (get_uart_rx_tx_reg_tx_free(uart)==0) ;
|
||||
uart_write(uart, '\r');
|
||||
}
|
||||
ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
|
||||
const uint8_t *current = (const uint8_t *)ptr;
|
||||
if (isatty(fd)) {
|
||||
for (size_t jj = 0; jj < len; jj++) {
|
||||
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
|
||||
while (get_uart_rx_tx_reg_tx_free(uart) == 0)
|
||||
;
|
||||
uart_write(uart, current[jj]);
|
||||
if (current[jj] == '\n') {
|
||||
while (get_uart_rx_tx_reg_tx_free(uart) == 0)
|
||||
;
|
||||
uart_write(uart, '\r');
|
||||
}
|
||||
#elif defined(BOARD_iss)
|
||||
*((uint32_t*) 0xFFFF0000) = current[jj];
|
||||
*((uint32_t *)0xFFFF0000) = current[jj];
|
||||
#elif defined(BOARD_TGCP)
|
||||
//TODO: implement
|
||||
// TODO: implement
|
||||
#else
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = current[jj];
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
|
||||
;
|
||||
UART0_REG(UART_REG_TXFIFO) = current[jj];
|
||||
|
||||
if (current[jj] == '\n') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = '\r';
|
||||
}
|
||||
if (current[jj] == '\n') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
|
||||
;
|
||||
UART0_REG(UART_REG_TXFIFO) = '\r';
|
||||
}
|
||||
#endif
|
||||
}
|
||||
return len;
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
return _stub(EBADF);
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(write);
|
||||
|
|
|
|||
Loading…
Reference in New Issue