Ehrenberg firmware headers generated with peakrdl 1.2.8
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@ -3,8 +3,8 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* Generated at 2024-08-02 08:46:07 UTC
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* by peakrdl_mnrs version 1.2.7
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*/
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#ifndef _BSP_ACLINT_H
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@ -44,9 +44,15 @@ typedef struct __attribute((__packed__)) {
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//ACLINT_MSIP0
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inline uint32_t get_aclint_msip0(volatile aclint_t* reg){
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return reg->MSIP0;
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}
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inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value){
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reg->MSIP0 = value;
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}
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inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg){
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return (reg->MSIP0 >> 0) & 0x1;
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}
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inline void set_aclint_msip0(volatile aclint_t* reg, uint8_t value){
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inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value){
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reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
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}
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@ -3,8 +3,8 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* Generated at 2024-08-02 08:46:07 UTC
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* by peakrdl_mnrs version 1.2.7
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*/
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#ifndef _BSP_APB3SPI_H
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@ -193,9 +193,6 @@ inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){
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inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){
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return reg->STATUS;
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}
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inline void set_apb3spi_status(volatile apb3spi_t* reg, uint32_t value){
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reg->STATUS = value;
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}
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inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){
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return (reg->STATUS >> 0) & 0x3f;
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}
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@ -254,49 +251,85 @@ inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
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//APB3SPI_SCLK_CONFIG
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inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){
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return reg->SCLK_CONFIG;
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}
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inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value){
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reg->SCLK_CONFIG = value;
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}
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inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg){
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return (reg->SCLK_CONFIG >> 0) & 0xfff;
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}
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inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint16_t value){
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inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value){
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reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
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}
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//APB3SPI_SSGEN_SETUP
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inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){
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return reg->SSGEN_SETUP;
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}
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inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value){
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reg->SSGEN_SETUP = value;
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}
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inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg){
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return (reg->SSGEN_SETUP >> 0) & 0xfff;
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}
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inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint16_t value){
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inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value){
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reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
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}
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//APB3SPI_SSGEN_HOLD
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inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){
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return reg->SSGEN_HOLD;
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}
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inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value){
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reg->SSGEN_HOLD = value;
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}
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inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg){
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return (reg->SSGEN_HOLD >> 0) & 0xfff;
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}
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inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint16_t value){
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inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value){
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reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
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}
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//APB3SPI_SSGEN_DISABLE
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inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){
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return reg->SSGEN_DISABLE;
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}
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inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value){
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reg->SSGEN_DISABLE = value;
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}
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inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg){
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return (reg->SSGEN_DISABLE >> 0) & 0xfff;
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}
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inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint16_t value){
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inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value){
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reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
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}
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//APB3SPI_SSGEN_ACTIVE_HIGH
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inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){
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return reg->SSGEN_ACTIVE_HIGH;
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}
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inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){
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reg->SSGEN_ACTIVE_HIGH = value;
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}
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inline uint32_t get_apb3spi_ssgen_active_high_high_cycles(volatile apb3spi_t* reg){
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return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
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}
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inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint8_t value){
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inline void set_apb3spi_ssgen_active_high_high_cycles(volatile apb3spi_t* reg, uint8_t value){
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reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
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}
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//APB3SPI_XIP_ENABLE
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inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){
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return reg->XIP_ENABLE;
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}
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inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value){
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reg->XIP_ENABLE = value;
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}
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inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg){
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return (reg->XIP_ENABLE >> 0) & 0x1;
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}
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inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint8_t value){
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inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value){
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reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
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}
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@ -365,17 +398,26 @@ inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value)
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}
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//APB3SPI_XIP_WRITE
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inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint8_t value){
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inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value){
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reg->XIP_WRITE = value;
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}
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inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value){
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reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
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}
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//APB3SPI_XIP_READ_WRITE
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inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint8_t value){
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inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value){
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reg->XIP_READ_WRITE = value;
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}
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inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value){
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reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
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}
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//APB3SPI_XIP_READ
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inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){
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return reg->XIP_READ;
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}
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inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg){
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return (reg->XIP_READ >> 0) & 0xff;
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}
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@ -3,8 +3,8 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* Generated at 2024-08-02 08:46:07 UTC
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* by peakrdl_mnrs version 1.2.7
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*/
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#ifndef _BSP_CAMERA_H
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@ -63,17 +63,29 @@ typedef struct __attribute((__packed__)) {
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//CAMERA_PIXEL
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inline uint32_t get_camera_pixel(volatile camera_t* reg){
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return reg->PIXEL;
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}
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inline void set_camera_pixel(volatile camera_t* reg, uint32_t value){
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reg->PIXEL = value;
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}
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inline uint32_t get_camera_pixel_data(volatile camera_t* reg){
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return (reg->PIXEL >> 0) & 0x7ff;
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}
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inline void set_camera_pixel(volatile camera_t* reg, uint16_t value){
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inline void set_camera_pixel_data(volatile camera_t* reg, uint16_t value){
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reg->PIXEL = (reg->PIXEL & ~(0x7ffU << 0)) | (value << 0);
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}
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//CAMERA_CONTROL
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inline uint32_t get_camera_control(volatile camera_t* reg){
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return reg->CONTROL;
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}
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inline void set_camera_control(volatile camera_t* reg, uint32_t value){
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reg->CONTROL = value;
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}
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inline uint32_t get_camera_control_active_clock(volatile camera_t* reg){
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return (reg->CONTROL >> 0) & 0x1;
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}
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inline void set_camera_control(volatile camera_t* reg, uint8_t value){
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inline void set_camera_control_active_clock(volatile camera_t* reg, uint8_t value){
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reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
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}
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@ -81,9 +93,6 @@ inline void set_camera_control(volatile camera_t* reg, uint8_t value){
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inline uint32_t get_camera_status(volatile camera_t* reg){
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return reg->STATUS;
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}
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inline void set_camera_status(volatile camera_t* reg, uint32_t value){
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reg->STATUS = value;
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}
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inline uint32_t get_camera_status_enabled(volatile camera_t* reg){
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return (reg->STATUS >> 0) & 0x1;
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}
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@ -96,9 +105,15 @@ inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
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//CAMERA_CAMERA_CLOCK_CTRL
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inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){
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return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfffff;
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return reg->CAMERA_CLOCK_CTRL;
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}
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inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){
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reg->CAMERA_CLOCK_CTRL = value;
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}
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inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
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return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfffff;
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}
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inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint32_t value){
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reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
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}
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@ -0,0 +1,454 @@
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/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-08-02 08:46:07 UTC
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* by peakrdl_mnrs version 1.2.7
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*/
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#ifndef _BSP_DMA_H
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#define _BSP_DMA_H
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#include <stdint.h>
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typedef struct __attribute((__packed__)) {
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volatile uint32_t CONTROL;
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volatile uint32_t STATUS;
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volatile uint32_t IE;
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volatile uint32_t IP;
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volatile uint32_t CH0_EVENT;
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volatile uint32_t CH0_TRANSFER;
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volatile uint32_t CH0_SRC_START_ADDR;
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volatile uint32_t CH0_SRC_ADDR_INC;
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volatile uint32_t CH0_DST_START_ADDR;
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volatile uint32_t CH0_DST_ADDR_INC;
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volatile uint32_t CH1_EVENT;
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volatile uint32_t CH1_TRANSFER;
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volatile uint32_t CH1_SRC_START_ADDR;
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volatile uint32_t CH1_SRC_ADDR_INC;
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volatile uint32_t CH1_DST_START_ADDR;
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volatile uint32_t CH1_DST_ADDR_INC;
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}dma_t;
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#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
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#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
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#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
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#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
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#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
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#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
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#define DMA_STATUS_CH0_BUSY_OFFS 0
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#define DMA_STATUS_CH0_BUSY_MASK 0x1
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#define DMA_STATUS_CH0_BUSY(V) ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)
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#define DMA_STATUS_CH1_BUSY_OFFS 1
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#define DMA_STATUS_CH1_BUSY_MASK 0x1
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#define DMA_STATUS_CH1_BUSY(V) ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)
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#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
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#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
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#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
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#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
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#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
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#define DMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
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#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
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#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
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#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
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#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
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#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
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#define DMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
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#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
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#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
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#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
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#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
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#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
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#define DMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
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#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
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#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
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#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
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#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
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#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
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#define DMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
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#define DMA_CH0_EVENT_SELECT_OFFS 0
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#define DMA_CH0_EVENT_SELECT_MASK 0x1f
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#define DMA_CH0_EVENT_SELECT(V) ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)
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#define DMA_CH0_EVENT_COMBINE_OFFS 31
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#define DMA_CH0_EVENT_COMBINE_MASK 0x1
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#define DMA_CH0_EVENT_COMBINE(V) ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)
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#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
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#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
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#define DMA_CH0_TRANSFER_WIDTH(V) ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)
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#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
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#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
|
||||
#define DMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
|
||||
|
||||
#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
|
||||
#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
|
||||
#define DMA_CH0_TRANSFER_SEG_COUNT(V) ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)
|
||||
|
||||
#define DMA_CH0_SRC_START_ADDR_OFFS 0
|
||||
#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH0_SRC_START_ADDR(V) ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
|
||||
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
|
||||
|
||||
#define DMA_CH0_DST_START_ADDR_OFFS 0
|
||||
#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH0_DST_START_ADDR(V) ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
|
||||
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
|
||||
|
||||
#define DMA_CH1_EVENT_SELECT_OFFS 0
|
||||
#define DMA_CH1_EVENT_SELECT_MASK 0x1f
|
||||
#define DMA_CH1_EVENT_SELECT(V) ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)
|
||||
|
||||
#define DMA_CH1_EVENT_COMBINE_OFFS 31
|
||||
#define DMA_CH1_EVENT_COMBINE_MASK 0x1
|
||||
#define DMA_CH1_EVENT_COMBINE(V) ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)
|
||||
|
||||
#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
|
||||
#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
|
||||
#define DMA_CH1_TRANSFER_WIDTH(V) ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)
|
||||
|
||||
#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
|
||||
#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
|
||||
#define DMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
|
||||
|
||||
#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
|
||||
#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
|
||||
#define DMA_CH1_TRANSFER_SEG_COUNT(V) ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)
|
||||
|
||||
#define DMA_CH1_SRC_START_ADDR_OFFS 0
|
||||
#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH1_SRC_START_ADDR(V) ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
|
||||
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
|
||||
|
||||
#define DMA_CH1_DST_START_ADDR_OFFS 0
|
||||
#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
|
||||
#define DMA_CH1_DST_START_ADDR(V) ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)
|
||||
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
|
||||
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
|
||||
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
|
||||
|
||||
//DMA_CONTROL
|
||||
inline uint32_t get_dma_control(volatile dma_t* reg){
|
||||
return reg->CONTROL;
|
||||
}
|
||||
inline void set_dma_control(volatile dma_t* reg, uint32_t value){
|
||||
reg->CONTROL = value;
|
||||
}
|
||||
inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg){
|
||||
return (reg->CONTROL >> 0) & 0x1;
|
||||
}
|
||||
inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value){
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg){
|
||||
return (reg->CONTROL >> 1) & 0x1;
|
||||
}
|
||||
inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value){
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
//DMA_STATUS
|
||||
inline uint32_t get_dma_status(volatile dma_t* reg){
|
||||
return reg->STATUS;
|
||||
}
|
||||
inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg){
|
||||
return (reg->STATUS >> 0) & 0x1;
|
||||
}
|
||||
inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg){
|
||||
return (reg->STATUS >> 1) & 0x1;
|
||||
}
|
||||
|
||||
//DMA_IE
|
||||
inline uint32_t get_dma_ie(volatile dma_t* reg){
|
||||
return reg->IE;
|
||||
}
|
||||
inline void set_dma_ie(volatile dma_t* reg, uint32_t value){
|
||||
reg->IE = value;
|
||||
}
|
||||
inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg){
|
||||
return (reg->IE >> 0) & 0x1;
|
||||
}
|
||||
inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
|
||||
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg){
|
||||
return (reg->IE >> 1) & 0x1;
|
||||
}
|
||||
inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value){
|
||||
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg){
|
||||
return (reg->IE >> 2) & 0x1;
|
||||
}
|
||||
inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
|
||||
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
|
||||
}
|
||||
inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg){
|
||||
return (reg->IE >> 3) & 0x1;
|
||||
}
|
||||
inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value){
|
||||
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
|
||||
}
|
||||
|
||||
//DMA_IP
|
||||
inline uint32_t get_dma_ip(volatile dma_t* reg){
|
||||
return reg->IP;
|
||||
}
|
||||
inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg){
|
||||
return (reg->IP >> 0) & 0x1;
|
||||
}
|
||||
inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg){
|
||||
return (reg->IP >> 1) & 0x1;
|
||||
}
|
||||
inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg){
|
||||
return (reg->IP >> 2) & 0x1;
|
||||
}
|
||||
inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg){
|
||||
return (reg->IP >> 3) & 0x1;
|
||||
}
|
||||
|
||||
//DMA_CH0_EVENT
|
||||
inline uint32_t get_dma_ch0_event(volatile dma_t* reg){
|
||||
return reg->CH0_EVENT;
|
||||
}
|
||||
inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH0_EVENT = value;
|
||||
}
|
||||
inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg){
|
||||
return (reg->CH0_EVENT >> 0) & 0x1f;
|
||||
}
|
||||
inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value){
|
||||
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg){
|
||||
return (reg->CH0_EVENT >> 31) & 0x1;
|
||||
}
|
||||
inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value){
|
||||
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
|
||||
}
|
||||
|
||||
//DMA_CH0_TRANSFER
|
||||
inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg){
|
||||
return reg->CH0_TRANSFER;
|
||||
}
|
||||
inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH0_TRANSFER = value;
|
||||
}
|
||||
inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg){
|
||||
return (reg->CH0_TRANSFER >> 0) & 0x3;
|
||||
}
|
||||
inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value){
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg){
|
||||
return (reg->CH0_TRANSFER >> 2) & 0x3ff;
|
||||
}
|
||||
inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value){
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
|
||||
}
|
||||
inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg){
|
||||
return (reg->CH0_TRANSFER >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//DMA_CH0_SRC_START_ADDR
|
||||
inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg){
|
||||
return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//DMA_CH0_SRC_ADDR_INC
|
||||
inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg){
|
||||
return reg->CH0_SRC_ADDR_INC;
|
||||
}
|
||||
inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH0_SRC_ADDR_INC = value;
|
||||
}
|
||||
inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg){
|
||||
return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
|
||||
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg){
|
||||
return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//DMA_CH0_DST_START_ADDR
|
||||
inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg){
|
||||
return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//DMA_CH0_DST_ADDR_INC
|
||||
inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg){
|
||||
return reg->CH0_DST_ADDR_INC;
|
||||
}
|
||||
inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH0_DST_ADDR_INC = value;
|
||||
}
|
||||
inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg){
|
||||
return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
|
||||
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg){
|
||||
return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//DMA_CH1_EVENT
|
||||
inline uint32_t get_dma_ch1_event(volatile dma_t* reg){
|
||||
return reg->CH1_EVENT;
|
||||
}
|
||||
inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH1_EVENT = value;
|
||||
}
|
||||
inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg){
|
||||
return (reg->CH1_EVENT >> 0) & 0x1f;
|
||||
}
|
||||
inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value){
|
||||
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg){
|
||||
return (reg->CH1_EVENT >> 31) & 0x1;
|
||||
}
|
||||
inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value){
|
||||
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
|
||||
}
|
||||
|
||||
//DMA_CH1_TRANSFER
|
||||
inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg){
|
||||
return reg->CH1_TRANSFER;
|
||||
}
|
||||
inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH1_TRANSFER = value;
|
||||
}
|
||||
inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg){
|
||||
return (reg->CH1_TRANSFER >> 0) & 0x3;
|
||||
}
|
||||
inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value){
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg){
|
||||
return (reg->CH1_TRANSFER >> 2) & 0x3ff;
|
||||
}
|
||||
inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value){
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
|
||||
}
|
||||
inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg){
|
||||
return (reg->CH1_TRANSFER >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//DMA_CH1_SRC_START_ADDR
|
||||
inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg){
|
||||
return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//DMA_CH1_SRC_ADDR_INC
|
||||
inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg){
|
||||
return reg->CH1_SRC_ADDR_INC;
|
||||
}
|
||||
inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH1_SRC_ADDR_INC = value;
|
||||
}
|
||||
inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg){
|
||||
return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
|
||||
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg){
|
||||
return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//DMA_CH1_DST_START_ADDR
|
||||
inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg){
|
||||
return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//DMA_CH1_DST_ADDR_INC
|
||||
inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg){
|
||||
return reg->CH1_DST_ADDR_INC;
|
||||
}
|
||||
inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH1_DST_ADDR_INC = value;
|
||||
}
|
||||
inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg){
|
||||
return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
|
||||
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg){
|
||||
return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
|
||||
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
#endif /* _BSP_DMA_H */
|
||||
|
|
@ -3,8 +3,8 @@
|
|||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-06-08 13:20:02 UTC
|
||||
* by peakrdl_mnrs version 1.2.5
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_GPIO_H
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-07-13 07:46:30 UTC
|
||||
* by peakrdl_mnrs version 1.2.5
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_I2S_H
|
||||
|
|
@ -143,9 +143,6 @@ inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
|
|||
inline uint32_t get_i2s_status(volatile i2s_t* reg){
|
||||
return reg->STATUS;
|
||||
}
|
||||
inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){
|
||||
reg->STATUS = value;
|
||||
}
|
||||
inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
|
||||
return (reg->STATUS >> 0) & 0x1;
|
||||
}
|
||||
|
|
@ -161,17 +158,29 @@ inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
|
|||
|
||||
//I2S_I2S_CLOCK_CTRL
|
||||
inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
|
||||
return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
|
||||
return reg->I2S_CLOCK_CTRL;
|
||||
}
|
||||
inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
|
||||
reg->I2S_CLOCK_CTRL = value;
|
||||
}
|
||||
inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg){
|
||||
return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
|
||||
}
|
||||
inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value){
|
||||
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//I2S_PDM_CLOCK_CTRL
|
||||
inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
|
||||
return reg->PDM_CLOCK_CTRL;
|
||||
}
|
||||
inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
|
||||
reg->PDM_CLOCK_CTRL = value;
|
||||
}
|
||||
inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
|
||||
return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff;
|
||||
}
|
||||
inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint16_t value){
|
||||
inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint16_t value){
|
||||
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
|
|
@ -199,9 +208,6 @@ inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value)
|
|||
inline uint32_t get_i2s_ip(volatile i2s_t* reg){
|
||||
return reg->IP;
|
||||
}
|
||||
inline void set_i2s_ip(volatile i2s_t* reg, uint32_t value){
|
||||
reg->IP = value;
|
||||
}
|
||||
inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
|
||||
return (reg->IP >> 0) & 0x1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,460 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-07-13 07:46:30 UTC
|
||||
* by peakrdl_mnrs version 1.2.5
|
||||
*/
|
||||
|
||||
#ifndef _BSP_SIMPLEDMA_H
|
||||
#define _BSP_SIMPLEDMA_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint32_t CONTROL;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t IE;
|
||||
volatile uint32_t IP;
|
||||
volatile uint32_t CH0_EVENT;
|
||||
volatile uint32_t CH0_TRANSFER;
|
||||
volatile uint32_t CH0_SRC_START_ADDR;
|
||||
volatile uint32_t CH0_SRC_ADDR_INC;
|
||||
volatile uint32_t CH0_DST_START_ADDR;
|
||||
volatile uint32_t CH0_DST_ADDR_INC;
|
||||
volatile uint32_t CH1_EVENT;
|
||||
volatile uint32_t CH1_TRANSFER;
|
||||
volatile uint32_t CH1_SRC_START_ADDR;
|
||||
volatile uint32_t CH1_SRC_ADDR_INC;
|
||||
volatile uint32_t CH1_DST_START_ADDR;
|
||||
volatile uint32_t CH1_DST_ADDR_INC;
|
||||
}simpledma_t;
|
||||
|
||||
#define SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
|
||||
#define SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
|
||||
#define SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << SIMPLEDMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
|
||||
#define SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
|
||||
#define SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << SIMPLEDMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
|
||||
|
||||
#define SIMPLEDMA_STATUS_CH0_BUSY_OFFS 0
|
||||
#define SIMPLEDMA_STATUS_CH0_BUSY_MASK 0x1
|
||||
#define SIMPLEDMA_STATUS_CH0_BUSY(V) ((V & SIMPLEDMA_STATUS_CH0_BUSY_MASK) << SIMPLEDMA_STATUS_CH0_BUSY_OFFS)
|
||||
|
||||
#define SIMPLEDMA_STATUS_CH1_BUSY_OFFS 1
|
||||
#define SIMPLEDMA_STATUS_CH1_BUSY_MASK 0x1
|
||||
#define SIMPLEDMA_STATUS_CH1_BUSY(V) ((V & SIMPLEDMA_STATUS_CH1_BUSY_MASK) << SIMPLEDMA_STATUS_CH1_BUSY_OFFS)
|
||||
|
||||
#define SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
|
||||
#define SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
|
||||
#define SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
|
||||
#define SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
|
||||
#define SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
|
||||
#define SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
|
||||
#define SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
|
||||
#define SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
|
||||
#define SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
|
||||
#define SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
|
||||
#define SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
|
||||
#define SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
|
||||
#define SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
|
||||
#define SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_EVENT_SELECT_OFFS 0
|
||||
#define SIMPLEDMA_CH0_EVENT_SELECT_MASK 0x1f
|
||||
#define SIMPLEDMA_CH0_EVENT_SELECT(V) ((V & SIMPLEDMA_CH0_EVENT_SELECT_MASK) << SIMPLEDMA_CH0_EVENT_SELECT_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_EVENT_COMBINE_OFFS 31
|
||||
#define SIMPLEDMA_CH0_EVENT_COMBINE_MASK 0x1
|
||||
#define SIMPLEDMA_CH0_EVENT_COMBINE(V) ((V & SIMPLEDMA_CH0_EVENT_COMBINE_MASK) << SIMPLEDMA_CH0_EVENT_COMBINE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_TRANSFER_WIDTH_OFFS 0
|
||||
#define SIMPLEDMA_CH0_TRANSFER_WIDTH_MASK 0x3
|
||||
#define SIMPLEDMA_CH0_TRANSFER_WIDTH(V) ((V & SIMPLEDMA_CH0_TRANSFER_WIDTH_MASK) << SIMPLEDMA_CH0_TRANSFER_WIDTH_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
|
||||
#define SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
|
||||
#define SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH_MASK) << SIMPLEDMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
|
||||
#define SIMPLEDMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
|
||||
#define SIMPLEDMA_CH0_TRANSFER_SEG_COUNT(V) ((V & SIMPLEDMA_CH0_TRANSFER_SEG_COUNT_MASK) << SIMPLEDMA_CH0_TRANSFER_SEG_COUNT_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_SRC_START_ADDR_OFFS 0
|
||||
#define SIMPLEDMA_CH0_SRC_START_ADDR_MASK 0xffffffff
|
||||
#define SIMPLEDMA_CH0_SRC_START_ADDR(V) ((V & SIMPLEDMA_CH0_SRC_START_ADDR_MASK) << SIMPLEDMA_CH0_SRC_START_ADDR_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
|
||||
#define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
|
||||
#define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
|
||||
#define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
|
||||
#define SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << SIMPLEDMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_DST_START_ADDR_OFFS 0
|
||||
#define SIMPLEDMA_CH0_DST_START_ADDR_MASK 0xffffffff
|
||||
#define SIMPLEDMA_CH0_DST_START_ADDR(V) ((V & SIMPLEDMA_CH0_DST_START_ADDR_MASK) << SIMPLEDMA_CH0_DST_START_ADDR_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
|
||||
#define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
|
||||
#define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << SIMPLEDMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
|
||||
#define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
|
||||
#define SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << SIMPLEDMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_EVENT_SELECT_OFFS 0
|
||||
#define SIMPLEDMA_CH1_EVENT_SELECT_MASK 0x1f
|
||||
#define SIMPLEDMA_CH1_EVENT_SELECT(V) ((V & SIMPLEDMA_CH1_EVENT_SELECT_MASK) << SIMPLEDMA_CH1_EVENT_SELECT_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_EVENT_COMBINE_OFFS 31
|
||||
#define SIMPLEDMA_CH1_EVENT_COMBINE_MASK 0x1
|
||||
#define SIMPLEDMA_CH1_EVENT_COMBINE(V) ((V & SIMPLEDMA_CH1_EVENT_COMBINE_MASK) << SIMPLEDMA_CH1_EVENT_COMBINE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_TRANSFER_WIDTH_OFFS 0
|
||||
#define SIMPLEDMA_CH1_TRANSFER_WIDTH_MASK 0x3
|
||||
#define SIMPLEDMA_CH1_TRANSFER_WIDTH(V) ((V & SIMPLEDMA_CH1_TRANSFER_WIDTH_MASK) << SIMPLEDMA_CH1_TRANSFER_WIDTH_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
|
||||
#define SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
|
||||
#define SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH_MASK) << SIMPLEDMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
|
||||
#define SIMPLEDMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
|
||||
#define SIMPLEDMA_CH1_TRANSFER_SEG_COUNT(V) ((V & SIMPLEDMA_CH1_TRANSFER_SEG_COUNT_MASK) << SIMPLEDMA_CH1_TRANSFER_SEG_COUNT_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_SRC_START_ADDR_OFFS 0
|
||||
#define SIMPLEDMA_CH1_SRC_START_ADDR_MASK 0xffffffff
|
||||
#define SIMPLEDMA_CH1_SRC_START_ADDR(V) ((V & SIMPLEDMA_CH1_SRC_START_ADDR_MASK) << SIMPLEDMA_CH1_SRC_START_ADDR_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
|
||||
#define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
|
||||
#define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
|
||||
#define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
|
||||
#define SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << SIMPLEDMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_DST_START_ADDR_OFFS 0
|
||||
#define SIMPLEDMA_CH1_DST_START_ADDR_MASK 0xffffffff
|
||||
#define SIMPLEDMA_CH1_DST_START_ADDR(V) ((V & SIMPLEDMA_CH1_DST_START_ADDR_MASK) << SIMPLEDMA_CH1_DST_START_ADDR_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
|
||||
#define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
|
||||
#define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << SIMPLEDMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
|
||||
|
||||
#define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
|
||||
#define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
|
||||
#define SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << SIMPLEDMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
|
||||
|
||||
//SIMPLEDMA_CONTROL
|
||||
inline uint32_t get_simpledma_control(volatile simpledma_t* reg){
|
||||
return reg->CONTROL;
|
||||
}
|
||||
inline void set_simpledma_control(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CONTROL = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_control_ch0_enable_transfer(volatile simpledma_t* reg){
|
||||
return (reg->CONTROL >> 0) & 0x1;
|
||||
}
|
||||
inline void set_simpledma_control_ch0_enable_transfer(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_control_ch1_enable_transfer(volatile simpledma_t* reg){
|
||||
return (reg->CONTROL >> 1) & 0x1;
|
||||
}
|
||||
inline void set_simpledma_control_ch1_enable_transfer(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_STATUS
|
||||
inline uint32_t get_simpledma_status(volatile simpledma_t* reg){
|
||||
return reg->STATUS;
|
||||
}
|
||||
inline void set_simpledma_status(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->STATUS = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_status_ch0_busy(volatile simpledma_t* reg){
|
||||
return (reg->STATUS >> 0) & 0x1;
|
||||
}
|
||||
inline uint32_t get_simpledma_status_ch1_busy(volatile simpledma_t* reg){
|
||||
return (reg->STATUS >> 1) & 0x1;
|
||||
}
|
||||
|
||||
//SIMPLEDMA_IE
|
||||
inline uint32_t get_simpledma_ie(volatile simpledma_t* reg){
|
||||
return reg->IE;
|
||||
}
|
||||
inline void set_simpledma_ie(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->IE = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ie_ch0_ie_seg_transfer_done(volatile simpledma_t* reg){
|
||||
return (reg->IE >> 0) & 0x1;
|
||||
}
|
||||
inline void set_simpledma_ie_ch0_ie_seg_transfer_done(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_ie_ch0_ie_transfer_done(volatile simpledma_t* reg){
|
||||
return (reg->IE >> 1) & 0x1;
|
||||
}
|
||||
inline void set_simpledma_ie_ch0_ie_transfer_done(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
inline uint32_t get_simpledma_ie_ch1_ie_seg_transfer_done(volatile simpledma_t* reg){
|
||||
return (reg->IE >> 2) & 0x1;
|
||||
}
|
||||
inline void set_simpledma_ie_ch1_ie_seg_transfer_done(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
|
||||
}
|
||||
inline uint32_t get_simpledma_ie_ch1_ie_transfer_done(volatile simpledma_t* reg){
|
||||
return (reg->IE >> 3) & 0x1;
|
||||
}
|
||||
inline void set_simpledma_ie_ch1_ie_transfer_done(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_IP
|
||||
inline uint32_t get_simpledma_ip(volatile simpledma_t* reg){
|
||||
return reg->IP;
|
||||
}
|
||||
inline void set_simpledma_ip(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->IP = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ip_ch0_ip_seg_transfer_done(volatile simpledma_t* reg){
|
||||
return (reg->IP >> 0) & 0x1;
|
||||
}
|
||||
inline uint32_t get_simpledma_ip_ch0_ip_transfer_done(volatile simpledma_t* reg){
|
||||
return (reg->IP >> 1) & 0x1;
|
||||
}
|
||||
inline uint32_t get_simpledma_ip_ch1_ip_seg_transfer_done(volatile simpledma_t* reg){
|
||||
return (reg->IP >> 2) & 0x1;
|
||||
}
|
||||
inline uint32_t get_simpledma_ip_ch1_ip_transfer_done(volatile simpledma_t* reg){
|
||||
return (reg->IP >> 3) & 0x1;
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH0_EVENT
|
||||
inline uint32_t get_simpledma_ch0_event(volatile simpledma_t* reg){
|
||||
return reg->CH0_EVENT;
|
||||
}
|
||||
inline void set_simpledma_ch0_event(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH0_EVENT = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ch0_event_select(volatile simpledma_t* reg){
|
||||
return (reg->CH0_EVENT >> 0) & 0x1f;
|
||||
}
|
||||
inline void set_simpledma_ch0_event_select(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch0_event_combine(volatile simpledma_t* reg){
|
||||
return (reg->CH0_EVENT >> 31) & 0x1;
|
||||
}
|
||||
inline void set_simpledma_ch0_event_combine(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH0_TRANSFER
|
||||
inline uint32_t get_simpledma_ch0_transfer(volatile simpledma_t* reg){
|
||||
return reg->CH0_TRANSFER;
|
||||
}
|
||||
inline void set_simpledma_ch0_transfer(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH0_TRANSFER = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ch0_transfer_width(volatile simpledma_t* reg){
|
||||
return (reg->CH0_TRANSFER >> 0) & 0x3;
|
||||
}
|
||||
inline void set_simpledma_ch0_transfer_width(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch0_transfer_seg_length(volatile simpledma_t* reg){
|
||||
return (reg->CH0_TRANSFER >> 2) & 0x3ff;
|
||||
}
|
||||
inline void set_simpledma_ch0_transfer_seg_length(volatile simpledma_t* reg, uint16_t value){
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch0_transfer_seg_count(volatile simpledma_t* reg){
|
||||
return (reg->CH0_TRANSFER >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_simpledma_ch0_transfer_seg_count(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH0_SRC_START_ADDR
|
||||
inline uint32_t get_simpledma_ch0_src_start_addr(volatile simpledma_t* reg){
|
||||
return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_simpledma_ch0_src_start_addr(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH0_SRC_ADDR_INC
|
||||
inline uint32_t get_simpledma_ch0_src_addr_inc(volatile simpledma_t* reg){
|
||||
return reg->CH0_SRC_ADDR_INC;
|
||||
}
|
||||
inline void set_simpledma_ch0_src_addr_inc(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH0_SRC_ADDR_INC = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ch0_src_addr_inc_src_step(volatile simpledma_t* reg){
|
||||
return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_simpledma_ch0_src_addr_inc_src_step(volatile simpledma_t* reg, uint16_t value){
|
||||
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch0_src_addr_inc_src_stride(volatile simpledma_t* reg){
|
||||
return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_simpledma_ch0_src_addr_inc_src_stride(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH0_DST_START_ADDR
|
||||
inline uint32_t get_simpledma_ch0_dst_start_addr(volatile simpledma_t* reg){
|
||||
return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_simpledma_ch0_dst_start_addr(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH0_DST_ADDR_INC
|
||||
inline uint32_t get_simpledma_ch0_dst_addr_inc(volatile simpledma_t* reg){
|
||||
return reg->CH0_DST_ADDR_INC;
|
||||
}
|
||||
inline void set_simpledma_ch0_dst_addr_inc(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH0_DST_ADDR_INC = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ch0_dst_addr_inc_dst_step(volatile simpledma_t* reg){
|
||||
return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_simpledma_ch0_dst_addr_inc_dst_step(volatile simpledma_t* reg, uint16_t value){
|
||||
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch0_dst_addr_inc_dst_stride(volatile simpledma_t* reg){
|
||||
return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_simpledma_ch0_dst_addr_inc_dst_stride(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH1_EVENT
|
||||
inline uint32_t get_simpledma_ch1_event(volatile simpledma_t* reg){
|
||||
return reg->CH1_EVENT;
|
||||
}
|
||||
inline void set_simpledma_ch1_event(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH1_EVENT = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ch1_event_select(volatile simpledma_t* reg){
|
||||
return (reg->CH1_EVENT >> 0) & 0x1f;
|
||||
}
|
||||
inline void set_simpledma_ch1_event_select(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch1_event_combine(volatile simpledma_t* reg){
|
||||
return (reg->CH1_EVENT >> 31) & 0x1;
|
||||
}
|
||||
inline void set_simpledma_ch1_event_combine(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH1_TRANSFER
|
||||
inline uint32_t get_simpledma_ch1_transfer(volatile simpledma_t* reg){
|
||||
return reg->CH1_TRANSFER;
|
||||
}
|
||||
inline void set_simpledma_ch1_transfer(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH1_TRANSFER = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ch1_transfer_width(volatile simpledma_t* reg){
|
||||
return (reg->CH1_TRANSFER >> 0) & 0x3;
|
||||
}
|
||||
inline void set_simpledma_ch1_transfer_width(volatile simpledma_t* reg, uint8_t value){
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch1_transfer_seg_length(volatile simpledma_t* reg){
|
||||
return (reg->CH1_TRANSFER >> 2) & 0x3ff;
|
||||
}
|
||||
inline void set_simpledma_ch1_transfer_seg_length(volatile simpledma_t* reg, uint16_t value){
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch1_transfer_seg_count(volatile simpledma_t* reg){
|
||||
return (reg->CH1_TRANSFER >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_simpledma_ch1_transfer_seg_count(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH1_SRC_START_ADDR
|
||||
inline uint32_t get_simpledma_ch1_src_start_addr(volatile simpledma_t* reg){
|
||||
return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_simpledma_ch1_src_start_addr(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH1_SRC_ADDR_INC
|
||||
inline uint32_t get_simpledma_ch1_src_addr_inc(volatile simpledma_t* reg){
|
||||
return reg->CH1_SRC_ADDR_INC;
|
||||
}
|
||||
inline void set_simpledma_ch1_src_addr_inc(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH1_SRC_ADDR_INC = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ch1_src_addr_inc_src_step(volatile simpledma_t* reg){
|
||||
return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_simpledma_ch1_src_addr_inc_src_step(volatile simpledma_t* reg, uint16_t value){
|
||||
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch1_src_addr_inc_src_stride(volatile simpledma_t* reg){
|
||||
return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_simpledma_ch1_src_addr_inc_src_stride(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH1_DST_START_ADDR
|
||||
inline uint32_t get_simpledma_ch1_dst_start_addr(volatile simpledma_t* reg){
|
||||
return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_simpledma_ch1_dst_start_addr(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//SIMPLEDMA_CH1_DST_ADDR_INC
|
||||
inline uint32_t get_simpledma_ch1_dst_addr_inc(volatile simpledma_t* reg){
|
||||
return reg->CH1_DST_ADDR_INC;
|
||||
}
|
||||
inline void set_simpledma_ch1_dst_addr_inc(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH1_DST_ADDR_INC = value;
|
||||
}
|
||||
inline uint32_t get_simpledma_ch1_dst_addr_inc_dst_step(volatile simpledma_t* reg){
|
||||
return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_simpledma_ch1_dst_addr_inc_dst_step(volatile simpledma_t* reg, uint16_t value){
|
||||
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_simpledma_ch1_dst_addr_inc_dst_stride(volatile simpledma_t* reg){
|
||||
return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
|
||||
}
|
||||
inline void set_simpledma_ch1_dst_addr_inc_dst_stride(volatile simpledma_t* reg, uint32_t value){
|
||||
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
|
||||
}
|
||||
|
||||
#endif /* _BSP_SIMPLEDMA_H */
|
||||
|
|
@ -3,8 +3,8 @@
|
|||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-06-08 13:20:02 UTC
|
||||
* by peakrdl_mnrs version 1.2.5
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_TIMERCOUNTER_H
|
||||
|
|
@ -60,9 +60,15 @@ typedef struct __attribute((__packed__)) {
|
|||
|
||||
//TIMERCOUNTER_PRESCALER
|
||||
inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){
|
||||
return reg->PRESCALER;
|
||||
}
|
||||
inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value){
|
||||
reg->PRESCALER = value;
|
||||
}
|
||||
inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg){
|
||||
return (reg->PRESCALER >> 0) & 0xffff;
|
||||
}
|
||||
inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint16_t value){
|
||||
inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value){
|
||||
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-07-13 07:46:30 UTC
|
||||
* by peakrdl_mnrs version 1.2.5
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_UART_H
|
||||
|
|
@ -160,9 +160,15 @@ inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
|
|||
|
||||
//UART_CLK_DIVIDER_REG
|
||||
inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
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return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
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return reg->CLK_DIVIDER_REG;
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}
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inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
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reg->CLK_DIVIDER_REG = value;
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}
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inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
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return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
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}
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inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
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reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
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}
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||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue