support up to 15 words per message
This commit is contained in:
parent
546851f509
commit
30cebaa066
@ -36,6 +36,27 @@ static void send_msg(uint32_t cluster, uint32_t component, uint32_t msg_len, uin
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case 7:
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set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(msgif, words[i]);
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break;
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case 8:
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set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(msgif, words[i]);
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break;
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case 9:
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set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(msgif, words[i]);
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break;
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case 10:
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set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(msgif, words[i]);
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break;
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case 11:
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set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(msgif, words[i]);
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break;
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case 12:
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set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(msgif, words[i]);
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break;
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case 13:
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set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(msgif, words[i]);
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break;
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case 14:
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set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(msgif, words[i]);
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break;
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default:
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break;
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}
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@ -1,11 +1,11 @@
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/*
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* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2025-02-18 11:11:47 UTC
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* by peakrdl_mnrs version 1.2.9
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*/
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* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2025-05-05 14:06:05 UTC
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* by peakrdl_mnrs version 1.2.9
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*/
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#ifndef _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
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#define _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H
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@ -13,20 +13,28 @@
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#include <stdint.h>
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typedef struct {
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volatile uint32_t REG_SEND;
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volatile uint32_t REG_HEADER;
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volatile uint32_t REG_ACK;
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volatile uint32_t REG_RECV_ID;
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volatile uint32_t REG_RECV_PAYLOAD;
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uint8_t fill0[12];
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volatile uint32_t REG_PAYLOAD_0;
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volatile uint32_t REG_PAYLOAD_1;
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volatile uint32_t REG_PAYLOAD_2;
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volatile uint32_t REG_PAYLOAD_3;
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volatile uint32_t REG_PAYLOAD_4;
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volatile uint32_t REG_PAYLOAD_5;
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volatile uint32_t REG_PAYLOAD_6;
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volatile uint32_t REG_PAYLOAD_7;
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volatile uint32_t REG_SEND;
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volatile uint32_t REG_HEADER;
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volatile uint32_t REG_ACK;
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volatile uint32_t REG_RECV_ID;
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volatile uint32_t REG_RECV_PAYLOAD;
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uint8_t fill0[12];
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volatile uint32_t REG_PAYLOAD_0;
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volatile uint32_t REG_PAYLOAD_1;
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volatile uint32_t REG_PAYLOAD_2;
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volatile uint32_t REG_PAYLOAD_3;
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volatile uint32_t REG_PAYLOAD_4;
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volatile uint32_t REG_PAYLOAD_5;
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volatile uint32_t REG_PAYLOAD_6;
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volatile uint32_t REG_PAYLOAD_7;
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volatile uint32_t REG_PAYLOAD_8;
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volatile uint32_t REG_PAYLOAD_9;
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volatile uint32_t REG_PAYLOAD_10;
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volatile uint32_t REG_PAYLOAD_11;
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volatile uint32_t REG_PAYLOAD_12;
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volatile uint32_t REG_PAYLOAD_13;
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volatile uint32_t REG_PAYLOAD_14;
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volatile uint32_t REG_PAYLOAD_15;
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} mkcontrolclusterstreamcontroller_t;
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
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@ -46,186 +54,237 @@ typedef struct {
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) \
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<< MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) \
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<< MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) \
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((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
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// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS)
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS 0
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK 0xffffffff
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#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS)
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//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
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static inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
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reg->REG_SEND = value;
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reg->REG_SEND = value;
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}
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static inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
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reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
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reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
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}
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// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
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//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
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static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg) {
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return reg->REG_HEADER;
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return reg->REG_HEADER;
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}
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static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
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reg->REG_HEADER = value;
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reg->REG_HEADER = value;
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}
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static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
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return (reg->REG_HEADER >> 0) & 0xf;
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return (reg->REG_HEADER >> 0) & 0xf;
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}
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static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg,
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uint8_t value) {
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reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
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static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
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reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
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}
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static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg) {
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return (reg->REG_HEADER >> 4) & 0xf;
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return (reg->REG_HEADER >> 4) & 0xf;
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}
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static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg,
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uint8_t value) {
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reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
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static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
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reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
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}
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static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(
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volatile mkcontrolclusterstreamcontroller_t* reg) {
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return (reg->REG_HEADER >> 8) & 0x7;
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static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg) {
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return (reg->REG_HEADER >> 8) & 0x7;
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}
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static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg,
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uint8_t value) {
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reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
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static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
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reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
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}
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static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg) {
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return (reg->REG_HEADER >> 11) & 0x3;
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return (reg->REG_HEADER >> 11) & 0x3;
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}
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static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg,
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uint8_t value) {
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reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
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static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
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reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
|
||||
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg) {
|
||||
return reg->REG_ACK;
|
||||
return reg->REG_ACK;
|
||||
}
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_ACK = value;
|
||||
reg->REG_ACK = value;
|
||||
}
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
|
||||
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
|
||||
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg) {
|
||||
return (reg->REG_ACK >> 1) & 0x1;
|
||||
return (reg->REG_ACK >> 1) & 0x1;
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
|
||||
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
|
||||
return reg->REG_RECV_ID;
|
||||
return reg->REG_RECV_ID;
|
||||
}
|
||||
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
|
||||
return (reg->REG_RECV_ID >> 0) & 0xf;
|
||||
return (reg->REG_RECV_ID >> 0) & 0xf;
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
|
||||
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg) {
|
||||
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
|
||||
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_8 = (reg->REG_PAYLOAD_8 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_9 = (reg->REG_PAYLOAD_9 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_10 = (reg->REG_PAYLOAD_10 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_11 = (reg->REG_PAYLOAD_11 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_12 = (reg->REG_PAYLOAD_12 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_13 = (reg->REG_PAYLOAD_13 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_14 = (reg->REG_PAYLOAD_14 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15
|
||||
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_15(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
|
||||
reg->REG_PAYLOAD_15 = (reg->REG_PAYLOAD_15 & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */
|
||||
Loading…
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Reference in New Issue
Block a user