Firmware/MNRS-BM-BSP
9
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

update address map

Browse Source
This commit is contained in:
Johannes Wirth 2025-04-10 13:05:58 +02:00
parent 263d7d9074
commit 2ab28cf7f7
1 changed files with 101 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

160
include/ehrenberg/devices/fki_cluster_info.h
View File

@ -9,12 +9,14 @@ static uint8_t fki_stream2axi(uint8_t cluster);
static uint8_t fki_dma_adapter(uint8_t cluster);
static uint64_t fki_addr_ccc_peMapping(uint8_t cluster);
static uint64_t fki_addr_sram1(uint8_t cluster);
static uint64_t fki_addr_ccc_configMem(uint8_t cluster);
static uint64_t fki_addr_sram2(uint8_t cluster);
static uint64_t fki_addr_cntrl_cva5(uint8_t cluster);
static uint64_t fki_addr_cntrl_tgc(uint8_t cluster);
static uint64_t fki_addr_ccc_idxTasks(uint8_t cluster);
static uint64_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster);
static uint64_t fki_addr_ccc_idxJobs(uint8_t cluster);
static uint64_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster);
static uint64_t fki_addr_ccc_configMem(uint8_t cluster);
static uint64_t fki_addr_aes_adapter(uint8_t cluster);
static uint64_t fki_addr_ut_adapter(uint8_t cluster);
static uint64_t fki_addr_sram0(uint8_t cluster);
@ -41,27 +43,33 @@ static uint64_t fki_addr_sram3(uint8_t cluster);
#define ADDR_Compute0_aes_adapter 0x80007000
#define BYTES_Compute0_aes_adapter 4096
#define HIGH_Compute0_aes_adapter 0x80007fff
#define ADDR_Compute0_cntrl_cva5_clusterReg 0x8000a000
#define BYTES_Compute0_cntrl_cva5_clusterReg 4096
#define HIGH_Compute0_cntrl_cva5_clusterReg 0x8000afff
#define ADDR_Compute0_cntrl_cva5 0x80008000
#define BYTES_Compute0_cntrl_cva5 16384
#define HIGH_Compute0_cntrl_cva5 0x8000bfff
#define ADDR_Compute0_cntrl_tgc 0x8000c000
#define BYTES_Compute0_cntrl_tgc 16384
#define HIGH_Compute0_cntrl_tgc 0x8000ffff
#define ADDR_Compute0_ut_adapter 0x80010000
#define BYTES_Compute0_ut_adapter 4096
#define HIGH_Compute0_ut_adapter 0x80010fff
#define ADDR_Compute0_sram0 0x80011000
#define BYTES_Compute0_cntrl_cva5 8192
#define HIGH_Compute0_cntrl_cva5 0x80009fff
#define ADDR_Compute0_cntrl_tgc_clusterReg 0x8000d000
#define BYTES_Compute0_cntrl_tgc_clusterReg 4096
#define HIGH_Compute0_cntrl_tgc_clusterReg 0x8000dfff
#define ADDR_Compute0_cntrl_tgc 0x8000b000
#define BYTES_Compute0_cntrl_tgc 8192
#define HIGH_Compute0_cntrl_tgc 0x8000cfff
#define ADDR_Compute0_ut_adapter 0x8000e000
#define BYTES_Compute0_ut_adapter 8192
#define HIGH_Compute0_ut_adapter 0x8000ffff
#define ADDR_Compute0_sram0 0x80010000
#define BYTES_Compute0_sram0 524288
#define HIGH_Compute0_sram0 0x80090fff
#define ADDR_Compute0_sram1 0x80091000
#define HIGH_Compute0_sram0 0x8008ffff
#define ADDR_Compute0_sram1 0x80090000
#define BYTES_Compute0_sram1 262144
#define HIGH_Compute0_sram1 0x800d0fff
#define ADDR_Compute0_sram2 0x800d1000
#define HIGH_Compute0_sram1 0x800cffff
#define ADDR_Compute0_sram2 0x800d0000
#define BYTES_Compute0_sram2 262144
#define HIGH_Compute0_sram2 0x80110fff
#define ADDR_Compute0_sram3 0x80111000
#define HIGH_Compute0_sram2 0x8010ffff
#define ADDR_Compute0_sram3 0x80110000
#define BYTES_Compute0_sram3 262144
#define HIGH_Compute0_sram3 0x80150fff
#define HIGH_Compute0_sram3 0x8014ffff
#define Compute1 3
#define Compute1_ccc 3,0
#define Compute1_stream2axi 3,1
@ -83,27 +91,33 @@ static uint64_t fki_addr_sram3(uint8_t cluster);
#define ADDR_Compute1_aes_adapter 0x90007000
#define BYTES_Compute1_aes_adapter 4096
#define HIGH_Compute1_aes_adapter 0x90007fff
#define ADDR_Compute1_cntrl_cva5_clusterReg 0x8000a000
#define BYTES_Compute1_cntrl_cva5_clusterReg 4096
#define HIGH_Compute1_cntrl_cva5_clusterReg 0x8000afff
#define ADDR_Compute1_cntrl_cva5 0x90008000
#define BYTES_Compute1_cntrl_cva5 16384
#define HIGH_Compute1_cntrl_cva5 0x9000bfff
#define ADDR_Compute1_cntrl_tgc 0x9000c000
#define BYTES_Compute1_cntrl_tgc 16384
#define HIGH_Compute1_cntrl_tgc 0x9000ffff
#define ADDR_Compute1_ut_adapter 0x90010000
#define BYTES_Compute1_ut_adapter 4096
#define HIGH_Compute1_ut_adapter 0x90010fff
#define ADDR_Compute1_sram0 0x90011000
#define BYTES_Compute1_cntrl_cva5 12288
#define HIGH_Compute1_cntrl_cva5 0x9000afff
#define ADDR_Compute1_cntrl_tgc_clusterReg 0x8000d000
#define BYTES_Compute1_cntrl_tgc_clusterReg 4096
#define HIGH_Compute1_cntrl_tgc_clusterReg 0x8000dfff
#define ADDR_Compute1_cntrl_tgc 0x9000b000
#define BYTES_Compute1_cntrl_tgc 12288
#define HIGH_Compute1_cntrl_tgc 0x9000dfff
#define ADDR_Compute1_ut_adapter 0x9000e000
#define BYTES_Compute1_ut_adapter 8192
#define HIGH_Compute1_ut_adapter 0x9000ffff
#define ADDR_Compute1_sram0 0x90010000
#define BYTES_Compute1_sram0 524288
#define HIGH_Compute1_sram0 0x90090fff
#define ADDR_Compute1_sram1 0x90091000
#define HIGH_Compute1_sram0 0x9008ffff
#define ADDR_Compute1_sram1 0x90090000
#define BYTES_Compute1_sram1 262144
#define HIGH_Compute1_sram1 0x900d0fff
#define ADDR_Compute1_sram2 0x900d1000
#define HIGH_Compute1_sram1 0x900cffff
#define ADDR_Compute1_sram2 0x900d0000
#define BYTES_Compute1_sram2 262144
#define HIGH_Compute1_sram2 0x90110fff
#define ADDR_Compute1_sram3 0x90111000
#define HIGH_Compute1_sram2 0x9010ffff
#define ADDR_Compute1_sram3 0x90110000
#define BYTES_Compute1_sram3 262144
#define HIGH_Compute1_sram3 0x90150fff
#define HIGH_Compute1_sram3 0x9014ffff
static uint8_t fki_ccc(uint8_t cluster) {
switch(cluster) {
@ -192,24 +206,10 @@ static uint64_t fki_addr_ccc_peMapping(uint8_t cluster) {
static uint64_t fki_addr_sram1(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x90091000;
return 0x90090000;
}
case 2: {
return 0x80091000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_ccc_configMem(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x90000000;
}
case 2: {
return 0x80000000;
return 0x80090000;
}
default: {
return -1;
@ -220,10 +220,10 @@ static uint64_t fki_addr_ccc_configMem(uint8_t cluster) {
static uint64_t fki_addr_sram2(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x800d1000;
return 0x800d0000;
}
case 3: {
return 0x900d1000;
return 0x900d0000;
}
default: {
return -1;
@ -248,10 +248,10 @@ static uint64_t fki_addr_cntrl_cva5(uint8_t cluster) {
static uint64_t fki_addr_cntrl_tgc(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8000c000;
return 0x8000b000;
}
case 3: {
return 0x9000c000;
return 0x9000b000;
}
default: {
return -1;
@ -273,6 +273,20 @@ static uint64_t fki_addr_ccc_idxTasks(uint8_t cluster) {
}
}
static uint64_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x8000d000;
}
case 2: {
return 0x8000d000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_ccc_idxJobs(uint8_t cluster) {
switch(cluster) {
case 2: {
@ -287,6 +301,34 @@ static uint64_t fki_addr_ccc_idxJobs(uint8_t cluster) {
}
}
static uint64_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8000a000;
}
case 3: {
return 0x8000a000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_ccc_configMem(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x90000000;
}
case 2: {
return 0x80000000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_aes_adapter(uint8_t cluster) {
switch(cluster) {
case 2: {
@ -304,10 +346,10 @@ static uint64_t fki_addr_aes_adapter(uint8_t cluster) {
static uint64_t fki_addr_ut_adapter(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x90010000;
return 0x9000e000;
}
case 2: {
return 0x80010000;
return 0x8000e000;
}
default: {
return -1;
@ -318,10 +360,10 @@ static uint64_t fki_addr_ut_adapter(uint8_t cluster) {
static uint64_t fki_addr_sram0(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80011000;
return 0x80010000;
}
case 3: {
return 0x90011000;
return 0x90010000;
}
default: {
return -1;
@ -332,10 +374,10 @@ static uint64_t fki_addr_sram0(uint8_t cluster) {
static uint64_t fki_addr_sram3(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80111000;
return 0x80110000;
}
case 3: {
return 0x90111000;
return 0x90110000;
}
default: {
return -1;