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updates ehrenberg dma device to support dual channel

This commit is contained in:
Eyck Jentzsch 2024-07-11 22:36:41 +02:00
parent 9d607e932a
commit 1f4b4d2bb9
1 changed files with 341 additions and 126 deletions
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467
include/ehrenberg/devices/gen/simpledma.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-06-16 13:56:44 UTC
* Generated at 2024-07-11 21:56:10 UTC
* by peakrdl_mnrs version 1.2.5
*/
@ -15,31 +15,37 @@
typedef struct __attribute((__packed__)) {
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t EVENT;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t TRANSFER;
volatile uint32_t SRC_START_ADDR;
volatile uint32_t SRC_ADDR_INC;
volatile uint32_t DST_START_ADDR;
volatile uint32_t DST_ADDR_INC;
volatile uint32_t EVENT_CH0;
volatile uint32_t TRANSFER_CH0;
volatile uint32_t SRC_START_ADDR_CH0;
volatile uint32_t SRC_ADDR_INC_CH0;
volatile uint32_t DST_START_ADDR_CH0;
volatile uint32_t DST_ADDR_INC_CH0;
volatile uint32_t EVENT_CH1;
volatile uint32_t TRANSFER_CH1;
volatile uint32_t SRC_START_ADDR_CH1;
volatile uint32_t SRC_ADDR_INC_CH1;
volatile uint32_t DST_START_ADDR_CH1;
volatile uint32_t DST_ADDR_INC_CH1;
}simpledma_t;
#define SIMPLEDMA_CONTROL_OFFS 0
#define SIMPLEDMA_CONTROL_MASK 0x1
#define SIMPLEDMA_CONTROL(V) ((V & SIMPLEDMA_CONTROL_MASK) << SIMPLEDMA_CONTROL_OFFS)
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER_OFFS 0
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER_MASK 0x1
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER(V) ((V & SIMPLEDMA_CONTROL_ENABLE_TRANSFER_MASK) << SIMPLEDMA_CONTROL_ENABLE_TRANSFER_OFFS)
#define SIMPLEDMA_STATUS_OFFS 0
#define SIMPLEDMA_STATUS_MASK 0x1
#define SIMPLEDMA_STATUS(V) ((V & SIMPLEDMA_STATUS_MASK) << SIMPLEDMA_STATUS_OFFS)
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER1_OFFS 1
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER1_MASK 0x1
#define SIMPLEDMA_CONTROL_ENABLE_TRANSFER1(V) ((V & SIMPLEDMA_CONTROL_ENABLE_TRANSFER1_MASK) << SIMPLEDMA_CONTROL_ENABLE_TRANSFER1_OFFS)
#define SIMPLEDMA_EVENT_SELECT_OFFS 0
#define SIMPLEDMA_EVENT_SELECT_MASK 0x1f
#define SIMPLEDMA_EVENT_SELECT(V) ((V & SIMPLEDMA_EVENT_SELECT_MASK) << SIMPLEDMA_EVENT_SELECT_OFFS)
#define SIMPLEDMA_STATUS_BUSY_OFFS 0
#define SIMPLEDMA_STATUS_BUSY_MASK 0x1
#define SIMPLEDMA_STATUS_BUSY(V) ((V & SIMPLEDMA_STATUS_BUSY_MASK) << SIMPLEDMA_STATUS_BUSY_OFFS)
#define SIMPLEDMA_EVENT_COMBINE_OFFS 31
#define SIMPLEDMA_EVENT_COMBINE_MASK 0x1
#define SIMPLEDMA_EVENT_COMBINE(V) ((V & SIMPLEDMA_EVENT_COMBINE_MASK) << SIMPLEDMA_EVENT_COMBINE_OFFS)
#define SIMPLEDMA_STATUS_BUSY1_OFFS 1
#define SIMPLEDMA_STATUS_BUSY1_MASK 0x1
#define SIMPLEDMA_STATUS_BUSY1(V) ((V & SIMPLEDMA_STATUS_BUSY1_MASK) << SIMPLEDMA_STATUS_BUSY1_OFFS)
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS 0
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK 0x1
@ -49,6 +55,14 @@ typedef struct __attribute((__packed__)) {
#define SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IE_EN_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_EN_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1_OFFS 2
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1_MASK 0x1
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1(V) ((V & SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1_MASK) << SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE1_OFFS)
#define SIMPLEDMA_IE_EN_TRANSFER_DONE1_OFFS 3
#define SIMPLEDMA_IE_EN_TRANSFER_DONE1_MASK 0x1
#define SIMPLEDMA_IE_EN_TRANSFER_DONE1(V) ((V & SIMPLEDMA_IE_EN_TRANSFER_DONE1_MASK) << SIMPLEDMA_IE_EN_TRANSFER_DONE1_OFFS)
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS 0
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS)
@ -57,73 +71,134 @@ typedef struct __attribute((__packed__)) {
#define SIMPLEDMA_IP_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_TRANSFER_WIDTH_OFFS 0
#define SIMPLEDMA_TRANSFER_WIDTH_MASK 0x3
#define SIMPLEDMA_TRANSFER_WIDTH(V) ((V & SIMPLEDMA_TRANSFER_WIDTH_MASK) << SIMPLEDMA_TRANSFER_WIDTH_OFFS)
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE1_OFFS 2
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE1_MASK 0x1
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE1(V) ((V & SIMPLEDMA_IP_SEG_TRANSFER_DONE1_MASK) << SIMPLEDMA_IP_SEG_TRANSFER_DONE1_OFFS)
#define SIMPLEDMA_TRANSFER_SEG_LENGTH_OFFS 2
#define SIMPLEDMA_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define SIMPLEDMA_TRANSFER_SEG_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_SEG_LENGTH_MASK) << SIMPLEDMA_TRANSFER_SEG_LENGTH_OFFS)
#define SIMPLEDMA_IP_TRANSFER_DONE1_OFFS 3
#define SIMPLEDMA_IP_TRANSFER_DONE1_MASK 0x1
#define SIMPLEDMA_IP_TRANSFER_DONE1(V) ((V & SIMPLEDMA_IP_TRANSFER_DONE1_MASK) << SIMPLEDMA_IP_TRANSFER_DONE1_OFFS)
#define SIMPLEDMA_TRANSFER_SEG_COUNT_OFFS 12
#define SIMPLEDMA_TRANSFER_SEG_COUNT_MASK 0xfffff
#define SIMPLEDMA_TRANSFER_SEG_COUNT(V) ((V & SIMPLEDMA_TRANSFER_SEG_COUNT_MASK) << SIMPLEDMA_TRANSFER_SEG_COUNT_OFFS)
#define SIMPLEDMA_EVENT_CH0_SELECT_OFFS 0
#define SIMPLEDMA_EVENT_CH0_SELECT_MASK 0x1f
#define SIMPLEDMA_EVENT_CH0_SELECT(V) ((V & SIMPLEDMA_EVENT_CH0_SELECT_MASK) << SIMPLEDMA_EVENT_CH0_SELECT_OFFS)
#define SIMPLEDMA_SRC_START_ADDR_OFFS 0
#define SIMPLEDMA_SRC_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_SRC_START_ADDR(V) ((V & SIMPLEDMA_SRC_START_ADDR_MASK) << SIMPLEDMA_SRC_START_ADDR_OFFS)
#define SIMPLEDMA_EVENT_CH0_COMBINE_OFFS 31
#define SIMPLEDMA_EVENT_CH0_COMBINE_MASK 0x1
#define SIMPLEDMA_EVENT_CH0_COMBINE(V) ((V & SIMPLEDMA_EVENT_CH0_COMBINE_MASK) << SIMPLEDMA_EVENT_CH0_COMBINE_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STEP(V) ((V & SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_MASK) << SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_OFFS)
#define SIMPLEDMA_TRANSFER_CH0_WIDTH_OFFS 0
#define SIMPLEDMA_TRANSFER_CH0_WIDTH_MASK 0x3
#define SIMPLEDMA_TRANSFER_CH0_WIDTH(V) ((V & SIMPLEDMA_TRANSFER_CH0_WIDTH_MASK) << SIMPLEDMA_TRANSFER_CH0_WIDTH_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH_OFFS 2
#define SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH_MASK 0x3ff
#define SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH_MASK) << SIMPLEDMA_TRANSFER_CH0_SEG_LENGTH_OFFS)
#define SIMPLEDMA_DST_START_ADDR_OFFS 0
#define SIMPLEDMA_DST_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_DST_START_ADDR(V) ((V & SIMPLEDMA_DST_START_ADDR_MASK) << SIMPLEDMA_DST_START_ADDR_OFFS)
#define SIMPLEDMA_TRANSFER_CH0_SEG_COUNT_OFFS 12
#define SIMPLEDMA_TRANSFER_CH0_SEG_COUNT_MASK 0xfffff
#define SIMPLEDMA_TRANSFER_CH0_SEG_COUNT(V) ((V & SIMPLEDMA_TRANSFER_CH0_SEG_COUNT_MASK) << SIMPLEDMA_TRANSFER_CH0_SEG_COUNT_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_DST_STEP_OFFS 0
#define SIMPLEDMA_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define SIMPLEDMA_DST_ADDR_INC_DST_STEP(V) ((V & SIMPLEDMA_DST_ADDR_INC_DST_STEP_MASK) << SIMPLEDMA_DST_ADDR_INC_DST_STEP_OFFS)
#define SIMPLEDMA_SRC_START_ADDR_CH0_OFFS 0
#define SIMPLEDMA_SRC_START_ADDR_CH0_MASK 0xffffffff
#define SIMPLEDMA_SRC_START_ADDR_CH0(V) ((V & SIMPLEDMA_SRC_START_ADDR_CH0_MASK) << SIMPLEDMA_SRC_START_ADDR_CH0_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define SIMPLEDMA_DST_ADDR_INC_DST_STRIDE(V) ((V & SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_MASK) << SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP_OFFS 0
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP_MASK 0xfff
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP(V) ((V & SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP_MASK) << SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STEP_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE_OFFS 12
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE_MASK 0xfffff
#define SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_ADDR_INC_CH0_SRC_STRIDE_OFFS)
#define SIMPLEDMA_DST_START_ADDR_CH0_OFFS 0
#define SIMPLEDMA_DST_START_ADDR_CH0_MASK 0xffffffff
#define SIMPLEDMA_DST_START_ADDR_CH0(V) ((V & SIMPLEDMA_DST_START_ADDR_CH0_MASK) << SIMPLEDMA_DST_START_ADDR_CH0_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP_OFFS 0
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP_MASK 0xfff
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP(V) ((V & SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP_MASK) << SIMPLEDMA_DST_ADDR_INC_CH0_DST_STEP_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE_OFFS 12
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE_MASK 0xfffff
#define SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE(V) ((V & SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE_MASK) << SIMPLEDMA_DST_ADDR_INC_CH0_DST_STRIDE_OFFS)
#define SIMPLEDMA_EVENT_CH1_SELECT_OFFS 0
#define SIMPLEDMA_EVENT_CH1_SELECT_MASK 0x1f
#define SIMPLEDMA_EVENT_CH1_SELECT(V) ((V & SIMPLEDMA_EVENT_CH1_SELECT_MASK) << SIMPLEDMA_EVENT_CH1_SELECT_OFFS)
#define SIMPLEDMA_EVENT_CH1_COMBINE_OFFS 31
#define SIMPLEDMA_EVENT_CH1_COMBINE_MASK 0x1
#define SIMPLEDMA_EVENT_CH1_COMBINE(V) ((V & SIMPLEDMA_EVENT_CH1_COMBINE_MASK) << SIMPLEDMA_EVENT_CH1_COMBINE_OFFS)
#define SIMPLEDMA_TRANSFER_CH1_WIDTH_OFFS 0
#define SIMPLEDMA_TRANSFER_CH1_WIDTH_MASK 0x3
#define SIMPLEDMA_TRANSFER_CH1_WIDTH(V) ((V & SIMPLEDMA_TRANSFER_CH1_WIDTH_MASK) << SIMPLEDMA_TRANSFER_CH1_WIDTH_OFFS)
#define SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH_OFFS 2
#define SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH_MASK 0x3ff
#define SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH_MASK) << SIMPLEDMA_TRANSFER_CH1_SEG_LENGTH_OFFS)
#define SIMPLEDMA_TRANSFER_CH1_SEG_COUNT_OFFS 12
#define SIMPLEDMA_TRANSFER_CH1_SEG_COUNT_MASK 0xfffff
#define SIMPLEDMA_TRANSFER_CH1_SEG_COUNT(V) ((V & SIMPLEDMA_TRANSFER_CH1_SEG_COUNT_MASK) << SIMPLEDMA_TRANSFER_CH1_SEG_COUNT_OFFS)
#define SIMPLEDMA_SRC_START_ADDR_CH1_OFFS 0
#define SIMPLEDMA_SRC_START_ADDR_CH1_MASK 0xffffffff
#define SIMPLEDMA_SRC_START_ADDR_CH1(V) ((V & SIMPLEDMA_SRC_START_ADDR_CH1_MASK) << SIMPLEDMA_SRC_START_ADDR_CH1_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP_OFFS 0
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP_MASK 0xfff
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP(V) ((V & SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP_MASK) << SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STEP_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE_OFFS 12
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE_MASK 0xfffff
#define SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_ADDR_INC_CH1_SRC_STRIDE_OFFS)
#define SIMPLEDMA_DST_START_ADDR_CH1_OFFS 0
#define SIMPLEDMA_DST_START_ADDR_CH1_MASK 0xffffffff
#define SIMPLEDMA_DST_START_ADDR_CH1(V) ((V & SIMPLEDMA_DST_START_ADDR_CH1_MASK) << SIMPLEDMA_DST_START_ADDR_CH1_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP_OFFS 0
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP_MASK 0xfff
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP(V) ((V & SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP_MASK) << SIMPLEDMA_DST_ADDR_INC_CH1_DST_STEP_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE_OFFS 12
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE_MASK 0xfffff
#define SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE(V) ((V & SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE_MASK) << SIMPLEDMA_DST_ADDR_INC_CH1_DST_STRIDE_OFFS)
//SIMPLEDMA_CONTROL
inline uint32_t get_simpledma_control(volatile simpledma_t* reg){
return reg->CONTROL;
}
inline void set_simpledma_control(volatile simpledma_t* reg, uint32_t value){
reg->CONTROL = value;
}
inline uint32_t get_simpledma_control_enable_transfer(volatile simpledma_t* reg){
return (reg->CONTROL >> 0) & 0x1;
}
inline void set_simpledma_control(volatile simpledma_t* reg, uint8_t value){
inline void set_simpledma_control_enable_transfer(volatile simpledma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_simpledma_control_enable_transfer1(volatile simpledma_t* reg){
return (reg->CONTROL >> 1) & 0x1;
}
inline void set_simpledma_control_enable_transfer1(volatile simpledma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
}
//SIMPLEDMA_STATUS
inline uint32_t get_simpledma_status(volatile simpledma_t* reg){
return reg->STATUS;
}
inline void set_simpledma_status(volatile simpledma_t* reg, uint32_t value){
reg->STATUS = value;
}
inline uint32_t get_simpledma_status_busy(volatile simpledma_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
//SIMPLEDMA_EVENT
inline uint32_t get_simpledma_event(volatile simpledma_t* reg){
return reg->EVENT;
}
inline void set_simpledma_event(volatile simpledma_t* reg, uint32_t value){
reg->EVENT = value;
}
inline uint32_t get_simpledma_event_select(volatile simpledma_t* reg){
return (reg->EVENT >> 0) & 0x1f;
}
inline void set_simpledma_event_select(volatile simpledma_t* reg, uint8_t value){
reg->EVENT = (reg->EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_event_combine(volatile simpledma_t* reg){
return (reg->EVENT >> 31) & 0x1;
}
inline void set_simpledma_event_combine(volatile simpledma_t* reg, uint8_t value){
reg->EVENT = (reg->EVENT & ~(0x1U << 31)) | (value << 31);
inline uint32_t get_simpledma_status_busy1(volatile simpledma_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
//SIMPLEDMA_IE
@ -145,6 +220,18 @@ inline uint32_t get_simpledma_ie_en_transfer_done(volatile simpledma_t* reg){
inline void set_simpledma_ie_en_transfer_done(volatile simpledma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_simpledma_ie_en_seg_transfer_done1(volatile simpledma_t* reg){
return (reg->IE >> 2) & 0x1;
}
inline void set_simpledma_ie_en_seg_transfer_done1(volatile simpledma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_simpledma_ie_en_transfer_done1(volatile simpledma_t* reg){
return (reg->IE >> 3) & 0x1;
}
inline void set_simpledma_ie_en_transfer_done1(volatile simpledma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
}
//SIMPLEDMA_IP
inline uint32_t get_simpledma_ip(volatile simpledma_t* reg){
@ -159,87 +246,215 @@ inline uint32_t get_simpledma_ip_seg_transfer_done(volatile simpledma_t* reg){
inline uint32_t get_simpledma_ip_transfer_done(volatile simpledma_t* reg){
return (reg->IP >> 1) & 0x1;
}
//SIMPLEDMA_TRANSFER
inline uint32_t get_simpledma_transfer(volatile simpledma_t* reg){
return reg->TRANSFER;
inline uint32_t get_simpledma_ip_seg_transfer_done1(volatile simpledma_t* reg){
return (reg->IP >> 2) & 0x1;
}
inline void set_simpledma_transfer(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER = value;
}
inline uint32_t get_simpledma_transfer_width(volatile simpledma_t* reg){
return (reg->TRANSFER >> 0) & 0x3;
}
inline void set_simpledma_transfer_width(volatile simpledma_t* reg, uint8_t value){
reg->TRANSFER = (reg->TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_simpledma_transfer_seg_length(volatile simpledma_t* reg){
return (reg->TRANSFER >> 2) & 0x3ff;
}
inline void set_simpledma_transfer_seg_length(volatile simpledma_t* reg, uint16_t value){
reg->TRANSFER = (reg->TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_simpledma_transfer_seg_count(volatile simpledma_t* reg){
return (reg->TRANSFER >> 12) & 0xfffff;
}
inline void set_simpledma_transfer_seg_count(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER = (reg->TRANSFER & ~(0xfffffU << 12)) | (value << 12);
inline uint32_t get_simpledma_ip_transfer_done1(volatile simpledma_t* reg){
return (reg->IP >> 3) & 0x1;
}
//SIMPLEDMA_SRC_START_ADDR
inline uint32_t get_simpledma_src_start_addr(volatile simpledma_t* reg){
return (reg->SRC_START_ADDR >> 0) & 0xffffffff;
//SIMPLEDMA_EVENT_CH0
inline uint32_t get_simpledma_event_ch0(volatile simpledma_t* reg){
return reg->EVENT_CH0;
}
inline void set_simpledma_src_start_addr(volatile simpledma_t* reg, uint32_t value){
reg->SRC_START_ADDR = (reg->SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
inline void set_simpledma_event_ch0(volatile simpledma_t* reg, uint32_t value){
reg->EVENT_CH0 = value;
}
inline uint32_t get_simpledma_event_ch0_select(volatile simpledma_t* reg){
return (reg->EVENT_CH0 >> 0) & 0x1f;
}
inline void set_simpledma_event_ch0_select(volatile simpledma_t* reg, uint8_t value){
reg->EVENT_CH0 = (reg->EVENT_CH0 & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_event_ch0_combine(volatile simpledma_t* reg){
return (reg->EVENT_CH0 >> 31) & 0x1;
}
inline void set_simpledma_event_ch0_combine(volatile simpledma_t* reg, uint8_t value){
reg->EVENT_CH0 = (reg->EVENT_CH0 & ~(0x1U << 31)) | (value << 31);
}
//SIMPLEDMA_SRC_ADDR_INC
inline uint32_t get_simpledma_src_addr_inc(volatile simpledma_t* reg){
return reg->SRC_ADDR_INC;
//SIMPLEDMA_TRANSFER_CH0
inline uint32_t get_simpledma_transfer_ch0(volatile simpledma_t* reg){
return reg->TRANSFER_CH0;
}
inline void set_simpledma_src_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC = value;
inline void set_simpledma_transfer_ch0(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER_CH0 = value;
}
inline uint32_t get_simpledma_src_addr_inc_src_step(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC >> 0) & 0xfff;
inline uint32_t get_simpledma_transfer_ch0_width(volatile simpledma_t* reg){
return (reg->TRANSFER_CH0 >> 0) & 0x3;
}
inline void set_simpledma_src_addr_inc_src_step(volatile simpledma_t* reg, uint16_t value){
reg->SRC_ADDR_INC = (reg->SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
inline void set_simpledma_transfer_ch0_width(volatile simpledma_t* reg, uint8_t value){
reg->TRANSFER_CH0 = (reg->TRANSFER_CH0 & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_simpledma_src_addr_inc_src_stride(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC >> 12) & 0xfffff;
inline uint32_t get_simpledma_transfer_ch0_seg_length(volatile simpledma_t* reg){
return (reg->TRANSFER_CH0 >> 2) & 0x3ff;
}
inline void set_simpledma_src_addr_inc_src_stride(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC = (reg->SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
inline void set_simpledma_transfer_ch0_seg_length(volatile simpledma_t* reg, uint16_t value){
reg->TRANSFER_CH0 = (reg->TRANSFER_CH0 & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_simpledma_transfer_ch0_seg_count(volatile simpledma_t* reg){
return (reg->TRANSFER_CH0 >> 12) & 0xfffff;
}
inline void set_simpledma_transfer_ch0_seg_count(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER_CH0 = (reg->TRANSFER_CH0 & ~(0xfffffU << 12)) | (value << 12);
}
//SIMPLEDMA_DST_START_ADDR
inline uint32_t get_simpledma_dst_start_addr(volatile simpledma_t* reg){
return (reg->DST_START_ADDR >> 0) & 0xffffffff;
//SIMPLEDMA_SRC_START_ADDR_CH0
inline uint32_t get_simpledma_src_start_addr_ch0(volatile simpledma_t* reg){
return (reg->SRC_START_ADDR_CH0 >> 0) & 0xffffffff;
}
inline void set_simpledma_dst_start_addr(volatile simpledma_t* reg, uint32_t value){
reg->DST_START_ADDR = (reg->DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
inline void set_simpledma_src_start_addr_ch0(volatile simpledma_t* reg, uint32_t value){
reg->SRC_START_ADDR_CH0 = (reg->SRC_START_ADDR_CH0 & ~(0xffffffffU << 0)) | (value << 0);
}
//SIMPLEDMA_DST_ADDR_INC
inline uint32_t get_simpledma_dst_addr_inc(volatile simpledma_t* reg){
return reg->DST_ADDR_INC;
//SIMPLEDMA_SRC_ADDR_INC_CH0
inline uint32_t get_simpledma_src_addr_inc_ch0(volatile simpledma_t* reg){
return reg->SRC_ADDR_INC_CH0;
}
inline void set_simpledma_dst_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC = value;
inline void set_simpledma_src_addr_inc_ch0(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC_CH0 = value;
}
inline uint32_t get_simpledma_dst_addr_inc_dst_step(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC >> 0) & 0xfff;
inline uint32_t get_simpledma_src_addr_inc_ch0_src_step(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC_CH0 >> 0) & 0xfff;
}
inline void set_simpledma_dst_addr_inc_dst_step(volatile simpledma_t* reg, uint16_t value){
reg->DST_ADDR_INC = (reg->DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
inline void set_simpledma_src_addr_inc_ch0_src_step(volatile simpledma_t* reg, uint16_t value){
reg->SRC_ADDR_INC_CH0 = (reg->SRC_ADDR_INC_CH0 & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_dst_addr_inc_dst_stride(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC >> 12) & 0xfffff;
inline uint32_t get_simpledma_src_addr_inc_ch0_src_stride(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC_CH0 >> 12) & 0xfffff;
}
inline void set_simpledma_dst_addr_inc_dst_stride(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC = (reg->DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
inline void set_simpledma_src_addr_inc_ch0_src_stride(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC_CH0 = (reg->SRC_ADDR_INC_CH0 & ~(0xfffffU << 12)) | (value << 12);
}
//SIMPLEDMA_DST_START_ADDR_CH0
inline uint32_t get_simpledma_dst_start_addr_ch0(volatile simpledma_t* reg){
return (reg->DST_START_ADDR_CH0 >> 0) & 0xffffffff;
}
inline void set_simpledma_dst_start_addr_ch0(volatile simpledma_t* reg, uint32_t value){
reg->DST_START_ADDR_CH0 = (reg->DST_START_ADDR_CH0 & ~(0xffffffffU << 0)) | (value << 0);
}
//SIMPLEDMA_DST_ADDR_INC_CH0
inline uint32_t get_simpledma_dst_addr_inc_ch0(volatile simpledma_t* reg){
return reg->DST_ADDR_INC_CH0;
}
inline void set_simpledma_dst_addr_inc_ch0(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC_CH0 = value;
}
inline uint32_t get_simpledma_dst_addr_inc_ch0_dst_step(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC_CH0 >> 0) & 0xfff;
}
inline void set_simpledma_dst_addr_inc_ch0_dst_step(volatile simpledma_t* reg, uint16_t value){
reg->DST_ADDR_INC_CH0 = (reg->DST_ADDR_INC_CH0 & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_dst_addr_inc_ch0_dst_stride(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC_CH0 >> 12) & 0xfffff;
}
inline void set_simpledma_dst_addr_inc_ch0_dst_stride(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC_CH0 = (reg->DST_ADDR_INC_CH0 & ~(0xfffffU << 12)) | (value << 12);
}
//SIMPLEDMA_EVENT_CH1
inline uint32_t get_simpledma_event_ch1(volatile simpledma_t* reg){
return reg->EVENT_CH1;
}
inline void set_simpledma_event_ch1(volatile simpledma_t* reg, uint32_t value){
reg->EVENT_CH1 = value;
}
inline uint32_t get_simpledma_event_ch1_select(volatile simpledma_t* reg){
return (reg->EVENT_CH1 >> 0) & 0x1f;
}
inline void set_simpledma_event_ch1_select(volatile simpledma_t* reg, uint8_t value){
reg->EVENT_CH1 = (reg->EVENT_CH1 & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_event_ch1_combine(volatile simpledma_t* reg){
return (reg->EVENT_CH1 >> 31) & 0x1;
}
inline void set_simpledma_event_ch1_combine(volatile simpledma_t* reg, uint8_t value){
reg->EVENT_CH1 = (reg->EVENT_CH1 & ~(0x1U << 31)) | (value << 31);
}
//SIMPLEDMA_TRANSFER_CH1
inline uint32_t get_simpledma_transfer_ch1(volatile simpledma_t* reg){
return reg->TRANSFER_CH1;
}
inline void set_simpledma_transfer_ch1(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER_CH1 = value;
}
inline uint32_t get_simpledma_transfer_ch1_width(volatile simpledma_t* reg){
return (reg->TRANSFER_CH1 >> 0) & 0x3;
}
inline void set_simpledma_transfer_ch1_width(volatile simpledma_t* reg, uint8_t value){
reg->TRANSFER_CH1 = (reg->TRANSFER_CH1 & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_simpledma_transfer_ch1_seg_length(volatile simpledma_t* reg){
return (reg->TRANSFER_CH1 >> 2) & 0x3ff;
}
inline void set_simpledma_transfer_ch1_seg_length(volatile simpledma_t* reg, uint16_t value){
reg->TRANSFER_CH1 = (reg->TRANSFER_CH1 & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_simpledma_transfer_ch1_seg_count(volatile simpledma_t* reg){
return (reg->TRANSFER_CH1 >> 12) & 0xfffff;
}
inline void set_simpledma_transfer_ch1_seg_count(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER_CH1 = (reg->TRANSFER_CH1 & ~(0xfffffU << 12)) | (value << 12);
}
//SIMPLEDMA_SRC_START_ADDR_CH1
inline uint32_t get_simpledma_src_start_addr_ch1(volatile simpledma_t* reg){
return (reg->SRC_START_ADDR_CH1 >> 0) & 0xffffffff;
}
inline void set_simpledma_src_start_addr_ch1(volatile simpledma_t* reg, uint32_t value){
reg->SRC_START_ADDR_CH1 = (reg->SRC_START_ADDR_CH1 & ~(0xffffffffU << 0)) | (value << 0);
}
//SIMPLEDMA_SRC_ADDR_INC_CH1
inline uint32_t get_simpledma_src_addr_inc_ch1(volatile simpledma_t* reg){
return reg->SRC_ADDR_INC_CH1;
}
inline void set_simpledma_src_addr_inc_ch1(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC_CH1 = value;
}
inline uint32_t get_simpledma_src_addr_inc_ch1_src_step(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC_CH1 >> 0) & 0xfff;
}
inline void set_simpledma_src_addr_inc_ch1_src_step(volatile simpledma_t* reg, uint16_t value){
reg->SRC_ADDR_INC_CH1 = (reg->SRC_ADDR_INC_CH1 & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_src_addr_inc_ch1_src_stride(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC_CH1 >> 12) & 0xfffff;
}
inline void set_simpledma_src_addr_inc_ch1_src_stride(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC_CH1 = (reg->SRC_ADDR_INC_CH1 & ~(0xfffffU << 12)) | (value << 12);
}
//SIMPLEDMA_DST_START_ADDR_CH1
inline uint32_t get_simpledma_dst_start_addr_ch1(volatile simpledma_t* reg){
return (reg->DST_START_ADDR_CH1 >> 0) & 0xffffffff;
}
inline void set_simpledma_dst_start_addr_ch1(volatile simpledma_t* reg, uint32_t value){
reg->DST_START_ADDR_CH1 = (reg->DST_START_ADDR_CH1 & ~(0xffffffffU << 0)) | (value << 0);
}
//SIMPLEDMA_DST_ADDR_INC_CH1
inline uint32_t get_simpledma_dst_addr_inc_ch1(volatile simpledma_t* reg){
return reg->DST_ADDR_INC_CH1;
}
inline void set_simpledma_dst_addr_inc_ch1(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC_CH1 = value;
}
inline uint32_t get_simpledma_dst_addr_inc_ch1_dst_step(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC_CH1 >> 0) & 0xfff;
}
inline void set_simpledma_dst_addr_inc_ch1_dst_step(volatile simpledma_t* reg, uint16_t value){
reg->DST_ADDR_INC_CH1 = (reg->DST_ADDR_INC_CH1 & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_dst_addr_inc_ch1_dst_stride(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC_CH1 >> 12) & 0xfffff;
}
inline void set_simpledma_dst_addr_inc_ch1_dst_stride(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC_CH1 = (reg->DST_ADDR_INC_CH1 & ~(0xfffffU << 12)) | (value << 12);
}
#endif /* _BSP_SIMPLEDMA_H */