 Eyck Jentzsch
|
0b5de90fb1
|
changes [m|u]cause rd/wr handling
|
2023-06-11 18:29:58 +02:00 |
 Eyck-Alexander Jentzsch
|
15cd36dcd4
|
adds fix for compressed instructions and reads
|
2023-06-05 17:57:38 +02:00 |
|
Eyck-Alexander Jentzsch
|
2281ec4144
|
corrects errors and adds new backend and
|
2023-06-05 15:18:27 +02:00 |
|
Eyck-Alexander Jentzsch
|
11c481cec2
|
adds verbosity to error
|
2023-06-05 15:17:16 +02:00 |
|
Eyck Jentzsch
|
60d07f2eb6
|
changes default loglevel to info for tgc-sim
|
2023-06-01 06:55:21 +02:00 |
|
Eyck Jentzsch
|
a123beb301
|
fixes duplicate variable declaration and templates
|
2023-05-27 10:20:49 +02:00 |
|
Eyck Jentzsch
|
ee6218279e
|
adapts to latest code gen changes
|
2023-05-25 12:52:30 +02:00 |
|
Eyck-Alexander Jentzsch
|
6ed7eafc5d
|
adds inital version of tcc backend
|
2023-05-16 21:51:35 +02:00 |
|
Eyck Jentzsch
|
32848ec396
|
fixes build system and typo in wt_cache
|
2023-05-13 16:57:01 +02:00 |
|
Eyck Jentzsch
|
6789cf4c32
|
fixes case of unavailable backend
|
2023-05-12 15:45:53 +02:00 |
|
Eyck Jentzsch
|
afdf8fb97f
|
adds missing namespaces
|
2023-05-11 23:11:04 +02:00 |
|
Eyck Jentzsch
|
cfa7b72363
|
changes time handling at sockets
|
2023-05-06 19:57:29 +02:00 |
|
Eyck Jentzsch
|
d330307ed5
|
splits bus into 2 sockets for i/dbus
|
2023-05-04 21:59:31 +02:00 |
|
Eyck Jentzsch
|
aa70d8a54a
|
fixes CLIC to match clicinfo description in CLIC spec 11.04.2023
|
2023-05-02 17:22:13 +02:00 |
|
Eyck Jentzsch
|
b493745cd7
|
sets reset start time to 0
|
2023-05-02 11:21:42 +02:00 |
|
Eyck Jentzsch
|
f9e8e1d857
|
fixes core_complex wrt. tlm quantum and DMI
|
2023-05-02 11:13:25 +02:00 |
|
Eyck Jentzsch
|
d990f1cf5d
|
fixes reading of 64bit CSR register
|
2023-05-01 22:23:35 +02:00 |
|
Eyck Jentzsch
|
1672b01e62
|
adds WT cache functionality as mixin
|
2023-04-28 20:38:07 +02:00 |
|
Eyck Jentzsch
|
00b0f101ac
|
adapts to changes of instrumentation interface in dbt-rise-core
|
2023-04-28 20:38:07 +02:00 |
|
Eyck Jentzsch
|
8ff55d7b92
|
updates CWR dependent core_complex definition
|
2023-04-14 19:34:41 +02:00 |
|
Eyck Jentzsch
|
f626ee2684
|
fixes privilege wrapper for M/U to cope with 64bit
|
2023-04-05 15:38:25 +02:00 |
|
Eyck Jentzsch
|
a8a2782329
|
adds changes from latest CoreDSL description
|
2023-04-04 16:10:12 +02:00 |
|
Eyck Jentzsch
|
98dd329833
|
fixes CSR access rights
|
2023-04-04 09:23:08 +02:00 |
|
Eyck Jentzsch
|
6213445bc4
|
fixes 64bit behavior of CSR regs
|
2023-03-27 12:04:43 +02:00 |
|
Eyck Jentzsch
|
c5465bf9e2
|
fixes according to fixed generator
|
2023-03-26 14:44:15 +02:00 |
|
Eyck Jentzsch
|
2e4faa4d50
|
fixes mstatus mask
|
2023-03-25 09:14:56 +01:00 |
|
Eyck Jentzsch
|
8e1951f298
|
adds 64bit mstatus
|
2023-03-23 07:47:21 +01:00 |
|
Eyck Jentzsch
|
7efa924510
|
fixes m/uintstatus read
|
2023-03-17 10:51:39 +01:00 |
|
Eyck Jentzsch
|
febbc4fff0
|
fixes m/uintstatus read
|
2023-03-17 10:23:05 +01:00 |
|
Eyck Jentzsch
|
39b2788b7e
|
implements and fixes CLIC CSR behavior
|
2023-03-17 09:09:09 +01:00 |
|
Eyck Jentzsch
|
a943dd3bdf
|
fixes wrong array size which led to unintended CSR definitions
|
2023-03-15 14:16:08 +01:00 |
|
Eyck Jentzsch
|
fedbff5971
|
fixes xcause and u-mode clic CSRs
|
2023-03-15 12:27:39 +01:00 |
|
Eyck Jentzsch
|
c2758e8321
|
removes mscratchcsw from CLIC feature
|
2023-03-15 09:07:00 +01:00 |
|
Eyck Jentzsch
|
8be5fe71df
|
fixes template name typo
|
2023-03-12 07:42:09 +01:00 |
|
Eyck Jentzsch
|
3f7ce41b9d
|
fixes CLIC mtvt register behavior
|
2023-03-11 14:03:03 +01:00 |
|
Eyck Jentzsch
|
ad1cbedf00
|
adds back missing max irq functions
|
2023-03-11 12:47:10 +01:00 |
|
Eyck Jentzsch
|
83f54b5074
|
fixes CLICCFG settings
|
2023-03-11 08:48:03 +01:00 |
|
Eyck Jentzsch
|
a83928fd8c
|
fixes CSR/CLIC implementation
|
2023-03-10 20:40:21 +01:00 |
|
Eyck Jentzsch
|
ec55efd322
|
adds generator changed files
|
2023-02-17 06:36:34 +01:00 |
|
Eyck Jentzsch
|
8c3709f92a
|
adds generator changed files
|
2023-02-17 06:29:27 +01:00 |
|
Eyck Jentzsch
|
62c118e501
|
fixes CSR to match latest fast interrupts spec
|
2023-01-20 16:21:04 +01:00 |
|
Eyck Jentzsch
|
65dca13b42
|
fixes WFI miss of interrupt
|
2023-01-14 17:40:21 +01:00 |
|
Eyck Jentzsch
|
8c701d55c1
|
adapt to latest changes in SCC
|
2022-12-05 09:15:48 +01:00 |
|
Eyck Jentzsch
|
f585489ff5
|
fixes pin naming
|
2022-10-26 17:21:44 +02:00 |
|
Eyck Jentzsch
|
7113683ee0
|
moves pending interrupt check before handling trap thus saving 1 cycle
|
2022-10-15 10:47:35 +02:00 |
|
Eyck Jentzsch
|
1a0fc4bd5d
|
fixes wrong mcounteren in M-mode only priv wrapper
|
2022-10-10 08:59:27 +02:00 |
|
Eyck Jentzsch
|
40d1966e9a
|
fixes pending irq within irq hander behavior
|
2022-10-08 11:20:52 +02:00 |
|
Eyck Jentzsch
|
a977200284
|
cleans up priv wrappers
|
2022-10-05 08:58:57 +02:00 |
|
Eyck Jentzsch
|
6ba7c82f80
|
fixes wrapper definitions for hwl cores
|
2022-09-26 13:31:46 +02:00 |
|
Eyck Jentzsch
|
ad7bb28b4c
|
fixes write mask of clic memory mapped registers
|
2022-09-17 12:15:19 +02:00 |
|
Eyck Jentzsch
|
fa7eda0889
|
fixes wrong check for exception
|
2022-08-31 11:45:53 +02:00 |
|
Eyck Jentzsch
|
00e02bf565
|
adds support for different branch types in tracing
|
2022-08-08 06:30:37 +02:00 |
|
Eyck Jentzsch
|
1ad66a71d8
|
extends supported break point types
|
2022-08-06 09:53:24 +02:00 |
|
Eyck Jentzsch
|
e60fa3d5e6
|
adaptes to changes in dbt-rise-core
|
2022-08-06 09:49:32 +02:00 |
|
Eyck Jentzsch
|
8407f6287f
|
replaces core_complex socket
|
2022-07-24 20:52:28 +02:00 |
|
Eyck Jentzsch
|
57347ae4d9
|
fixes cppcheck flagged issues
|
2022-07-23 13:49:10 +02:00 |
|
Eyck Jentzsch
|
4876f18ba9
|
adds windows compatibility fixes
|
2022-07-18 11:43:42 +02:00 |
|
Eyck Jentzsch
|
a53ee42e13
|
updates TGC_C according to CoreDSL description update
|
2022-07-12 22:34:22 +02:00 |
|
Eyck Jentzsch
|
12ccfc055a
|
updates generate tgc_c definition
|
2022-07-11 22:58:10 +02:00 |
|
Eyck Jentzsch
|
feaa49d367
|
removes decoder again as there is some issue
|
2022-06-20 00:39:11 +02:00 |
|
Eyck Jentzsch
|
f096b15dbd
|
factors decoder into separate component
|
2022-06-19 13:17:31 +02:00 |
|
Eyck Jentzsch
|
076b5a39ad
|
fix class naming
|
2022-06-02 08:30:49 +02:00 |
|
Eyck Jentzsch
|
f40ab41899
|
fix left-over from layout refactoring
|
2022-06-02 08:30:02 +02:00 |
|
Eyck Jentzsch
|
31fb51de95
|
update tgc_c generated code
|
2022-05-30 22:15:44 +02:00 |
|
Eyck Jentzsch
|
1c90fe765d
|
Merge remote-tracking branch 'origin/Trace_enhancement' into develop
|
2022-05-30 14:18:09 +02:00 |
|
Eyck Jentzsch
|
52ed8b81a6
|
fixed template to work with previous code generator
|
2022-05-30 14:08:02 +02:00 |
|
Eyck Jentzsch
|
0703a0a845
|
update tgc-mapper
|
2022-05-30 07:45:32 +02:00 |
|
Eyck Jentzsch
|
0c542d42aa
|
separate generated sources
|
2022-05-21 12:48:28 +02:00 |
|
Eyck Jentzsch
|
966d1616c5
|
change source code to unified layout
|
2022-05-21 11:55:24 +02:00 |
|
Eyck-Alexander Jentzsch
|
1720bd4aaa
|
adds support for compressed instructions
|
2022-05-20 15:17:58 +02:00 |
|
Eyck Jentzsch
|
df16378605
|
update template for changed code generator
|
2022-05-18 19:10:34 +02:00 |
|
Eyck Jentzsch
|
1438f0f373
|
add backannotation to pc trace plugin
|
2022-05-17 15:29:04 +02:00 |
|
Eyck Jentzsch
|
766f3ba9ee
|
fix assertion in compressed pctrace writer
|
2022-05-13 12:38:12 +02:00 |
|
Eyck Jentzsch
|
e382217e04
|
update vm_tgc_c due reworked CoreDSL generator
|
2022-05-11 18:52:15 +02:00 |
|
Eyck Jentzsch
|
9db4e3fd87
|
fix assertion
|
2022-05-10 16:13:21 +02:00 |
|
Eyck-Alexander Jentzsch
|
bb658be3b4
|
Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
|
2022-05-08 15:25:56 +02:00 |
|
Eyck-Alexander Jentzsch
|
6579780dc9
|
add call column in output
|
2022-05-08 15:24:26 +02:00 |
|
Eyck Jentzsch
|
e56bc12788
|
fix non-lz4 build of plugin
|
2022-05-07 17:27:11 +02:00 |
|
Eyck Jentzsch
|
e88f309ea2
|
add lz4 compression to pctrace
|
2022-05-07 17:22:06 +02:00 |
|
Eyck Jentzsch
|
03bec27376
|
implement extended instrumentation interface
|
2022-04-26 17:14:33 +02:00 |
|
Eyck Jentzsch
|
9d9008a3a2
|
fix pointer mess
|
2022-04-26 15:35:17 +02:00 |
 Stanislaw Kaushanski
|
5f6d462973
|
check that no interrupts are pending before entering the wfi wait
|
2022-04-26 13:58:20 +02:00 |
|
Eyck Jentzsch
|
a92b84bef4
|
add code word access for ISS plugins
|
2022-04-25 14:18:19 +02:00 |
|
Eyck Jentzsch
|
c054d75717
|
update to latest coredsl description
|
2022-04-10 18:55:44 +02:00 |
|
Eyck Jentzsch
|
8e4e702cb9
|
Merge remote-tracking branch 'origin/feature/reduced_output' into develop
|
2022-03-28 14:09:06 +02:00 |
|
Eyck-Alexander Jentzsch
|
58311b37db
|
Merge branch 'feature/reduced_output' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into
feature/reduced_output
|
2022-03-28 11:16:09 +02:00 |
|
Eyck Jentzsch
|
b0cb997009
|
add TGC_X with DMR
|
2022-03-26 10:48:21 +01:00 |
|
Eyck Jentzsch
|
30ae743361
|
add pctrace plugin to iss
|
2022-03-20 17:41:54 +01:00 |
|
Eyck Jentzsch
|
d91f5f9df4
|
fix compiler warning for reduced number of registers
|
2022-03-14 15:38:05 +01:00 |
|
Eyck Jentzsch
|
2e670c4d03
|
change interpreter structure
|
2022-03-06 15:11:38 +01:00 |
|
Eyck Jentzsch
|
521f40a3d6
|
refactored interpreter backend structure
|
2022-03-05 20:59:17 +01:00 |
|
Eyck-Alexander Jentzsch
|
2bba5645c3
|
adds functionality to reduce the output
|
2022-02-16 10:13:29 +01:00 |
|
Eyck-Alexander Jentzsch
|
4c363f4073
|
adds additional functionality by fetching delay information
|
2022-02-11 11:28:00 +01:00 |
|
Eyck Jentzsch
|
ac86f14a54
|
add tgc_c_xrb_nn to tgc-sim
|
2022-02-02 21:33:42 +01:00 |
|
Eyck Jentzsch
|
09b0f0d0c8
|
fix cycle estimation plugin
|
2022-02-01 21:14:50 +01:00 |
|
Eyck Jentzsch
|
98b418ff43
|
fix JSON reading
|
2022-02-01 19:28:11 +01:00 |
|
Eyck Jentzsch
|
059bd0d371
|
rework cycle estimation
|
2022-02-01 19:03:45 +01:00 |
|
Eyck-Alexander Jentzsch
|
7578906310
|
adds coverage plugin
|
2022-01-31 21:38:18 +01:00 |
|
Eyck Jentzsch
|
afe8905ac9
|
fix else-ambiguity in CoreDSL description
|
2022-01-31 20:30:46 +01:00 |
|
Eyck-Alexander Jentzsch
|
ecc6091d1e
|
cleans up source code to remove clang compiler warnings
|
2022-01-19 08:01:15 +01:00 |