Commit Graph

313 Commits

Author SHA1 Message Date
Eyck-Alexander Jentzsch 3ff59ba45d small refactor, adds baisc functionality 2024-01-10 10:15:05 +01:00
Eyck-Alexander Jentzsch 075e04249a adds semihosting skeleton 2024-01-09 12:50:41 +01:00
Eyck-Alexander Jentzsch 207f778ee6 adds initial semihosting host capabilities 2024-01-08 17:17:59 +01:00
Eyck Jentzsch bc4ea30815 apply clang-format 10 fixes 2023-12-01 14:50:54 +01:00
Eyck Jentzsch e921201f7b applies clang-format fixes 2023-11-30 11:51:49 +01:00
Eyck Jentzsch e6aa6e5842 adds handling of variable number of clic interrupts 2023-11-22 11:47:31 +01:00
Eyck Jentzsch 4418fa7e4f fixes include path of asmjit helpers 2023-11-20 16:07:01 +01:00
Eyck-Alexander Jentzsch 0eb1db0e7e adds functionality, adds working asmjit 2023-11-20 11:45:52 +01:00
Eyck Jentzsch e48597b2b7 adds formatting fixes 2023-11-05 17:19:43 +01:00
Eyck Jentzsch b3f40f9b15 build fixes due to dependencies 2023-11-04 13:05:30 +01:00
Eyck Jentzsch 759061b569 applies clang-format changes 2023-10-29 17:06:56 +01:00
Eyck Jentzsch 2bea95c1a7 adds option to disable DMI use 2023-10-28 17:06:50 +02:00
Eyck Jentzsch 7001b693ae updates templates for SystemC registration 2023-10-27 22:14:11 +02:00
Eyck Jentzsch e6f11081eb fixes quantum and quantum break handling 2023-10-27 21:12:49 +02:00
Eyck Jentzsch 09db0cd35d fixes LLVM backend registration for SystemC 2023-10-26 06:50:54 +02:00
Eyck Jentzsch 980c8031c3 fixes tohost behavior of SC wrapper and cycle-estimate plugin 2023-10-25 20:37:10 +02:00
Eyck Jentzsch b86d7a517d adds dynamic cycle estimation 2023-10-25 17:13:52 +02:00
Eyck Jentzsch b7478965ab adds asmjit backend registration for SystemC 2023-10-23 10:18:25 +02:00
Eyck Jentzsch bf4a6deb86 fixes dump-ir handling 2023-10-22 23:19:09 +02:00
Eyck-Alexander Jentzsch ffe730219d merge commit 2023-10-22 15:13:25 +02:00
Eyck-Alexander Jentzsch 60c926c921 adds asmjit 2023-10-22 15:11:20 +02:00
Eyck Jentzsch 4c3a7386b0 updates generated files 2023-10-22 08:51:08 +02:00
Eyck Jentzsch 74ff1d455a fixes install routine 2023-10-20 20:38:59 +02:00
Eyck Jentzsch ae4322c1b9 „src/main.cpp“ ändern 2023-10-15 09:03:31 +02:00
Stanislaw Kaushanski 9180ad1f9c debugger memory accesses should never lead to traps 2023-10-06 21:39:48 +02:00
Eyck Jentzsch ee6a068b06 streamlines backends and reporting 2023-10-01 18:33:14 +02:00
Eyck Jentzsch b97853ff5a update plugins to read YAML file 2023-09-30 22:10:24 +02:00
Eyck Jentzsch b7f023756e fixes constructor calls of derived riscv_hart classes 2023-09-27 07:51:49 +02:00
Eyck Jentzsch 2095ac985b fixes forgotten removal of pctrace in core_complex 2023-09-27 06:19:59 +02:00
Eyck Jentzsch 3fb8fe765a aligns riscv_hart_msu_vp with riscv_hart_m_p 2023-09-26 20:17:26 +02:00
Eyck-Alexander Jentzsch 5fd226b670 moves pctrace 2023-09-25 09:44:51 +02:00
Eyck-Alexander Jentzsch 417076f8e6 stops jit block creation in case of ECALL and EBREAK 2023-09-23 11:30:58 +02:00
Eyck-Alexander Jentzsch 70839bbbf2 changes templates for correct plugin callback in case of trap 2023-09-23 10:35:21 +02:00
Eyck-Alexander Jentzsch 8db0cc5d05 removes clutter 2023-09-23 10:34:58 +02:00
Eyck-Alexander Jentzsch 212fb1c8ff adds tracing functionality 2023-09-22 12:40:35 +02:00
Eyck-Alexander Jentzsch f74f98f361 improves readability 2023-09-22 12:40:12 +02:00
Eyck-Alexander Jentzsch 633c0d21a0 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-09-20 15:17:43 +02:00
Eyck-Alexander Jentzsch 51f6fbe0dd applies newest CoreDSL changes 2023-09-20 15:12:03 +02:00
Eyck-Alexander Jentzsch de45d06878 adds initial working version of llvm backend 2023-09-19 16:26:07 +02:00
Eyck-Alexander Jentzsch b360fc2c75 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-09-05 10:08:49 +02:00
Eyck-Alexander Jentzsch e21f8dc379 allows functions in interp and updates generated 2023-09-05 10:08:00 +02:00
Eyck Jentzsch 8ee3ac90f7 adapts name changes 2023-09-04 12:45:45 +02:00
Eyck Jentzsch b5d915f389 fixes compile issues from merge 2023-08-30 15:49:28 +02:00
Eyck Jentzsch 813b40409d Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
2023-08-30 10:05:42 +02:00
Eyck Jentzsch c8a4a4c736 renames core(s) 2023-08-28 07:09:55 +02:00
Eyck Jentzsch 20e920338c removes v2p function 2023-08-04 13:08:10 +02:00
Eyck Jentzsch e151416f58 fixes systemc factory registration 2023-07-31 12:55:09 +02:00
Eyck Jentzsch 24de2bbdf5 purge build system 2023-07-30 13:55:57 +02:00
Eyck Jentzsch e68f9c573f Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
2023-07-30 09:14:58 +02:00
Eyck Jentzsch f38cc7d8b9 updates LLVM build 2023-07-29 17:55:37 +02:00
Eyck-Alexander Jentzsch 7af7e040da Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-07-29 11:47:25 +02:00
Eyck-Alexander Jentzsch 6e52af168b adds faster decoding to tcc and cleans up others 2023-07-29 11:42:46 +02:00
Eyck-Alexander Jentzsch bd0d15f3a2 updates template for faster instruction decoding 2023-07-23 08:10:57 +02:00
Eyck-Alexander Jentzsch c78026b720 adds faster instruction decoding 2023-07-23 08:05:15 +02:00
Eyck Jentzsch a0ca3cdfa5 revive LLVM support (WIP) 2023-07-14 12:55:34 +02:00
Eyck Jentzsch 720236ec3f add generated core registration 2023-07-14 12:51:51 +02:00
Eyck Jentzsch 957145ca84 add SystemC ISS factory 2023-07-14 11:11:03 +02:00
Eyck Jentzsch 0b719a4b57 fixes literal type 2023-07-10 20:39:02 +02:00
Eyck Jentzsch b4b03f7850 fixes build system to handle TCC properly 2023-07-09 22:20:50 +02:00
Eyck Jentzsch 145a0cf68b updates registration of cores for sysc 2023-07-09 20:24:45 +02:00
Eyck Jentzsch 1cef7de8c7 fixes missing namespaces 2023-07-09 20:16:16 +02:00
Eyck Jentzsch e95f422aab cleans vm implementation up 2023-07-09 20:13:26 +02:00
Eyck Jentzsch 250ea3c980 extends factory to support SystemC core wrapper 2023-07-09 18:19:59 +02:00
Eyck-Alexander Jentzsch 7b31b8ca8e adds updated generated files 2023-07-09 16:58:47 +02:00
Eyck-Alexander Jentzsch 91a23a4a18 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-07-09 16:55:06 +02:00
Eyck Jentzsch a32c83e1be fixes CLI handling of plugin paramters in ISS 2023-07-05 08:32:05 +02:00
Eyck-Alexander Jentzsch 87b4082633 Merge branch 'tmp' into develop 2023-07-03 14:22:50 +02:00
Eyck Jentzsch 4dbc7433a5 fixes cause CSR handling 2023-06-12 17:38:56 +02:00
Eyck Jentzsch 99a9970ddd fixes sysc compile issues 2023-06-12 09:58:24 +02:00
Eyck Jentzsch 0b5de90fb1 changes [m|u]cause rd/wr handling 2023-06-11 18:29:58 +02:00
Eyck-Alexander Jentzsch 15cd36dcd4 adds fix for compressed instructions and reads 2023-06-05 17:57:38 +02:00
Eyck-Alexander Jentzsch 2281ec4144 corrects errors and adds new backend and 2023-06-05 15:18:27 +02:00
Eyck-Alexander Jentzsch 11c481cec2 adds verbosity to error 2023-06-05 15:17:16 +02:00
Eyck Jentzsch 60d07f2eb6 changes default loglevel to info for tgc-sim 2023-06-01 06:55:21 +02:00
Eyck Jentzsch a123beb301 fixes duplicate variable declaration and templates 2023-05-27 10:20:49 +02:00
Eyck Jentzsch ee6218279e adapts to latest code gen changes 2023-05-25 12:52:30 +02:00
Eyck-Alexander Jentzsch 6ed7eafc5d adds inital version of tcc backend 2023-05-16 21:51:35 +02:00
Eyck Jentzsch 32848ec396 fixes build system and typo in wt_cache 2023-05-13 16:57:01 +02:00
Eyck Jentzsch 6789cf4c32 fixes case of unavailable backend 2023-05-12 15:45:53 +02:00
Eyck Jentzsch afdf8fb97f adds missing namespaces 2023-05-11 23:11:04 +02:00
Eyck Jentzsch cfa7b72363 changes time handling at sockets 2023-05-06 19:57:29 +02:00
Eyck Jentzsch d330307ed5 splits bus into 2 sockets for i/dbus 2023-05-04 21:59:31 +02:00
Eyck Jentzsch aa70d8a54a fixes CLIC to match clicinfo description in CLIC spec 11.04.2023 2023-05-02 17:22:13 +02:00
Eyck Jentzsch b493745cd7 sets reset start time to 0 2023-05-02 11:21:42 +02:00
Eyck Jentzsch f9e8e1d857 fixes core_complex wrt. tlm quantum and DMI 2023-05-02 11:13:25 +02:00
Eyck Jentzsch d990f1cf5d fixes reading of 64bit CSR register 2023-05-01 22:23:35 +02:00
Eyck Jentzsch 1672b01e62 adds WT cache functionality as mixin 2023-04-28 20:38:07 +02:00
Eyck Jentzsch 00b0f101ac adapts to changes of instrumentation interface in dbt-rise-core 2023-04-28 20:38:07 +02:00
Eyck Jentzsch 8ff55d7b92 updates CWR dependent core_complex definition 2023-04-14 19:34:41 +02:00
Eyck Jentzsch f626ee2684 fixes privilege wrapper for M/U to cope with 64bit 2023-04-05 15:38:25 +02:00
Eyck Jentzsch a8a2782329 adds changes from latest CoreDSL description 2023-04-04 16:10:12 +02:00
Eyck Jentzsch 98dd329833 fixes CSR access rights 2023-04-04 09:23:08 +02:00
Eyck Jentzsch 6213445bc4 fixes 64bit behavior of CSR regs 2023-03-27 12:04:43 +02:00
Eyck Jentzsch c5465bf9e2 fixes according to fixed generator 2023-03-26 14:44:15 +02:00
Eyck Jentzsch 2e4faa4d50 fixes mstatus mask 2023-03-25 09:14:56 +01:00
Eyck Jentzsch 8e1951f298 adds 64bit mstatus 2023-03-23 07:47:21 +01:00
Eyck Jentzsch 7efa924510 fixes m/uintstatus read 2023-03-17 10:51:39 +01:00
Eyck Jentzsch febbc4fff0 fixes m/uintstatus read 2023-03-17 10:23:05 +01:00
Eyck Jentzsch 39b2788b7e implements and fixes CLIC CSR behavior 2023-03-17 09:09:09 +01:00
Eyck Jentzsch a943dd3bdf fixes wrong array size which led to unintended CSR definitions 2023-03-15 14:16:08 +01:00