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ee6e1d4092
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Merge remote-tracking branch 'origin/msvc_compat' into develop
Conflicts:
src/sysc/core_complex.cpp
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2021-10-11 09:42:40 +02:00 |
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f0ada1ba8c
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add MSVC 16 compatibility
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2021-10-10 19:06:41 +02:00 |
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2f15d9676e
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fix unaligned instr fetch behavior
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2021-09-30 19:27:46 +02:00 |
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d78fcc48e5
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use marchid in platform
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2021-09-30 19:27:03 +02:00 |
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438e598a4a
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remove clutter from core descriptions, added instr alignment setting
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2021-09-29 00:03:11 +02:00 |
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174259155d
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add support for non-compressed ISA
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2021-09-23 21:09:52 +02:00 |
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ba9339a50d
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fix MPP reset value, PMP inactive in U-mode handling and MRET in U-mode
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2021-09-21 16:52:40 +02:00 |
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65b4db5eca
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remove mcounteren in M-mode only platform
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2021-09-18 11:40:00 +02:00 |
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09b01af3fa
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fix find_package use and debug access alignment check
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2021-08-26 22:10:27 +02:00 |
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9c8b72693e
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correct trap ids of access faults
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2021-08-20 09:02:56 +02:00 |
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2f05083cf0
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fix elf loader and pmp check for debug accesses
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2021-08-19 10:50:25 +02:00 |
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836ba269e3
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fix clic reset values
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2021-08-16 15:05:05 +02:00 |
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adeffe47ad
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fix behavior of riscv_hart_mu_p to match TGC_D
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2021-08-12 20:34:10 +02:00 |
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d95846a849
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fix trap handling if illegal fetch (PMP) and U-mode CSRs
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2021-08-01 17:23:22 +02:00 |
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af887c286f
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fix for #2
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2021-07-28 09:09:08 +02:00 |
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d7bddd825c
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add clic CSRs
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2021-07-27 10:47:48 +02:00 |
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d0f3a120fd
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fix naming in MU wrapper
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2021-07-19 16:26:23 +02:00 |
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c592a26346
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fix mepc mask
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2021-07-09 13:01:22 +02:00 |
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e68918c2e8
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fix instruction decode
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2021-07-09 07:37:12 +02:00 |
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473f8a5a17
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fix privilege behavior
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2021-07-07 11:30:00 +02:00 |
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2f4b5bd9b2
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fix detailed behavior of TGC_C
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2021-07-06 21:19:36 +02:00 |
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23b9741adf
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refine and fix TGC_C iss to becoem compliant
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2021-06-29 11:51:30 +02:00 |
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5d8da08ce5
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fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
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2021-06-26 14:30:36 +02:00 |
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e432dd8208
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fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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d41e1d816a
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add factory for ISS and use it in main.cpp
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2021-05-16 16:44:14 +02:00 |
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a35974c9f5
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make cpu type in core_complex configurable
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2021-05-16 15:06:42 +02:00 |
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9c456ba8f2
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initial version of MU hart
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2021-05-14 13:29:39 +02:00 |
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cf7b62a3f9
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update names
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2021-05-13 15:54:48 +02:00 |
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391f9bb808
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remove unneeded constants
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2021-05-08 15:14:19 +02:00 |
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ef02dba8c5
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add read misa callback
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2021-04-09 11:20:51 +02:00 |
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7009943106
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fix wait for interrupt. Adapt for new SCC structure
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2021-04-07 17:42:08 +02:00 |
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0a76ccbdac
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make RSP register response independend of register definition
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2021-03-31 07:48:46 +00:00 |
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f4ec21007b
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fix signedness issues
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2021-03-11 16:12:28 +00:00 |
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40db74ce02
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remove tgf_b code generation
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2021-03-07 16:26:14 +00:00 |
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c251fe15d5
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fix desscriptions to conform to ISA spec version 20191213 and TGF-C
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2021-03-07 10:51:00 +00:00 |
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dae8acb8a3
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checkpoint before refactor
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2021-03-06 07:17:42 +00:00 |
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be0e7db185
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fix templates to comply with CoreDSL2
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2021-03-01 21:07:20 +00:00 |
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4aa26b85a0
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adapt to change in SCC
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2021-03-01 06:36:27 +00:00 |
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9534d58d01
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regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
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2021-03-01 06:26:33 +00:00 |
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1668df0531
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regenerated sources and and add opcode enum to headers
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2021-02-23 08:29:31 +00:00 |
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d07c8679ed
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update core definition
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2021-02-15 18:14:52 +00:00 |
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72b09472d5
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update RISC-V descriptions
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2021-02-15 18:01:33 +00:00 |
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34bb8e62ae
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generate working ISS from CoreDSL 2.0
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2021-02-06 14:47:06 +00:00 |
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da7e29fbb7
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update definitions of derived constants
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2021-01-01 09:19:48 +00:00 |
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c4da47cedd
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integrate code generation into build process (first attempt)
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2020-12-30 07:29:52 +00:00 |
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ab554539e3
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first version of tgf_c based on CoreDSL 2.0
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2020-12-29 08:48:22 +00:00 |
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43488676dd
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Update TGF naming convention
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2020-09-11 10:45:44 +02:00 |
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f3d578f050
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Remove 64bit support
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2020-09-07 14:30:19 +02:00 |
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293c396a0d
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update core wrapper: remove virtual memory support
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2020-09-07 13:29:45 +02:00 |
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