 Eyck-Alexander Jentzsch
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51f6fbe0dd
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applies newest CoreDSL changes
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2023-09-20 15:12:03 +02:00 |
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Eyck-Alexander Jentzsch
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de45d06878
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adds initial working version of llvm backend
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2023-09-19 16:26:07 +02:00 |
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Eyck-Alexander Jentzsch
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e21f8dc379
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allows functions in interp and updates generated
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2023-09-05 10:08:00 +02:00 |
 Eyck Jentzsch
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813b40409d
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Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
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2023-08-30 10:05:42 +02:00 |
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Eyck Jentzsch
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c8a4a4c736
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renames core(s)
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2023-08-28 07:09:55 +02:00 |
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Eyck Jentzsch
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18e08cfc50
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fixes missing template updates
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2023-08-08 06:23:38 +02:00 |
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Eyck Jentzsch
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20e920338c
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removes v2p function
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2023-08-04 13:08:10 +02:00 |
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Eyck Jentzsch
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e151416f58
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fixes systemc factory registration
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2023-07-31 12:55:09 +02:00 |
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Eyck Jentzsch
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e68f9c573f
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Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
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2023-07-30 09:14:58 +02:00 |
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Eyck Jentzsch
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f38cc7d8b9
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updates LLVM build
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2023-07-29 17:55:37 +02:00 |
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Eyck-Alexander Jentzsch
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7af7e040da
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Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
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2023-07-29 11:47:25 +02:00 |
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Eyck-Alexander Jentzsch
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6e52af168b
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adds faster decoding to tcc and cleans up others
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2023-07-29 11:42:46 +02:00 |
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Eyck-Alexander Jentzsch
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bd0d15f3a2
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updates template for faster instruction decoding
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2023-07-23 08:10:57 +02:00 |
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Eyck Jentzsch
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720236ec3f
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add generated core registration
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2023-07-14 12:51:51 +02:00 |
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Eyck Jentzsch
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957145ca84
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add SystemC ISS factory
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2023-07-14 11:11:03 +02:00 |
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Eyck Jentzsch
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0b719a4b57
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fixes literal type
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2023-07-10 20:39:02 +02:00 |
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Eyck Jentzsch
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b4b03f7850
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fixes build system to handle TCC properly
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2023-07-09 22:20:50 +02:00 |
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Eyck Jentzsch
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e95f422aab
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cleans vm implementation up
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2023-07-09 20:13:26 +02:00 |
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Eyck Jentzsch
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250ea3c980
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extends factory to support SystemC core wrapper
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2023-07-09 18:19:59 +02:00 |
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Eyck-Alexander Jentzsch
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21d3250e1a
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changes templates
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2023-07-09 16:53:59 +02:00 |
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Eyck-Alexander Jentzsch
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87b4082633
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Merge branch 'tmp' into develop
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2023-07-03 14:22:50 +02:00 |
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Eyck Jentzsch
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99a9970ddd
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fixes sysc compile issues
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2023-06-12 09:58:24 +02:00 |
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Eyck-Alexander Jentzsch
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15cd36dcd4
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adds fix for compressed instructions and reads
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2023-06-05 17:57:38 +02:00 |
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Eyck Jentzsch
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a123beb301
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fixes duplicate variable declaration and templates
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2023-05-27 10:20:49 +02:00 |
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Eyck-Alexander Jentzsch
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ce5b2e60b9
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amends template to fix branching instructions
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2023-05-22 17:00:36 +02:00 |
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Eyck-Alexander Jentzsch
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6ed7eafc5d
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adds inital version of tcc backend
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2023-05-16 21:51:35 +02:00 |
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Eyck-Alexander Jentzsch
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ee2ded931d
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adds remaining register offsets
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2023-05-14 17:16:42 +02:00 |
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Eyck Jentzsch
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95ba5c901a
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re-introduces last_branch register
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2023-05-14 17:00:37 +02:00 |
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Eyck Jentzsch
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00b0f101ac
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adapts to changes of instrumentation interface in dbt-rise-core
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2023-04-28 20:38:07 +02:00 |
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Eyck Jentzsch
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d881cb6e63
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fix data width of generated code
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2023-03-26 12:12:34 +02:00 |
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Eyck Jentzsch
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207dbf1071
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fixes out of range access for register alias names
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2023-02-17 06:28:30 +01:00 |
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Eyck Jentzsch
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65dca13b42
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fixes WFI miss of interrupt
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2023-01-14 17:40:21 +01:00 |
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Eyck Jentzsch
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7113683ee0
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moves pending interrupt check before handling trap thus saving 1 cycle
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2022-10-15 10:47:35 +02:00 |
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Eyck Jentzsch
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00e02bf565
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adds support for different branch types in tracing
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2022-08-08 06:30:37 +02:00 |
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Eyck Jentzsch
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0833198d34
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aads missing windows compat firx to template
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2022-07-23 14:36:23 +02:00 |
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Eyck Jentzsch
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4876f18ba9
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adds windows compatibility fixes
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2022-07-18 11:43:42 +02:00 |
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Eyck Jentzsch
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feaa49d367
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removes decoder again as there is some issue
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2022-06-20 00:39:11 +02:00 |
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Eyck Jentzsch
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18f33b4a68
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fixes ordering of instructions for decoding
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2022-06-19 16:52:29 +02:00 |
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Eyck Jentzsch
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f096b15dbd
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factors decoder into separate component
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2022-06-19 13:17:31 +02:00 |
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Eyck Jentzsch
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5d481eb79d
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fix generation of non-exception code
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2022-05-30 22:04:16 +02:00 |
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Eyck Jentzsch
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52ed8b81a6
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fixed template to work with previous code generator
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2022-05-30 14:08:02 +02:00 |
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Eyck Jentzsch
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0c542d42aa
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separate generated sources
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2022-05-21 12:48:28 +02:00 |
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Eyck Jentzsch
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df16378605
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update template for changed code generator
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2022-05-18 19:10:34 +02:00 |
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Eyck Jentzsch
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e88f309ea2
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add lz4 compression to pctrace
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2022-05-07 17:22:06 +02:00 |
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Eyck Jentzsch
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9d9008a3a2
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fix pointer mess
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2022-04-26 15:35:17 +02:00 |
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Eyck Jentzsch
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a92b84bef4
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add code word access for ISS plugins
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2022-04-25 14:18:19 +02:00 |
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Eyck Jentzsch
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2e670c4d03
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change interpreter structure
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2022-03-06 15:11:38 +01:00 |
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Eyck Jentzsch
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3d32c33333
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update gitignore
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2022-03-05 20:59:45 +01:00 |
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Eyck Jentzsch
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521f40a3d6
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refactored interpreter backend structure
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2022-03-05 20:59:17 +01:00 |
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Eyck Jentzsch
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b8fa5fbbda
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adapt to extended instrumentation interface
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2022-02-09 21:01:17 +01:00 |
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Eyck Jentzsch
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68b5697c8f
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Fix cycles JSON template
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2022-02-01 21:48:56 +01:00 |
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Eyck Jentzsch
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059bd0d371
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rework cycle estimation
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2022-02-01 19:03:45 +01:00 |
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Eyck Jentzsch
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ef2a4df925
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simplify spawn block handling
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2022-01-31 23:40:31 +01:00 |
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Eyck Jentzsch
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afe8905ac9
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fix else-ambiguity in CoreDSL description
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2022-01-31 20:30:46 +01:00 |
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Eyck Jentzsch
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3563ba80d0
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add spawn blocks
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2022-01-12 07:21:16 +01:00 |
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Eyck Jentzsch
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07d5af1dde
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fix stand-alone ISS compilation to include all generated cores
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2021-11-26 17:56:40 +01:00 |
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Eyck Jentzsch
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965929d1eb
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remove descriptions
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2021-11-15 09:30:16 +01:00 |
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Eyck Jentzsch
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d31b4ef5a8
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fix MISA val
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2021-11-11 12:58:57 +01:00 |
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Eyck Jentzsch
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7452c5df43
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add TGC_D_XRB_NN definition
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2021-11-11 12:16:35 +01:00 |
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Eyck Jentzsch
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fd98ad95f6
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rework PMP check and fix MISA for TGC_D
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2021-11-09 15:55:22 +01:00 |
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Eyck Jentzsch
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c42e336509
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fix proper debug mode handling (#267 & #268)
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2021-11-07 17:48:44 +01:00 |
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Eyck Jentzsch
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8b6e3abd23
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fix hard-code arch in templates
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2021-10-30 13:37:17 +02:00 |
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Eyck Jentzsch
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1616f0ac90
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remove deprecated functions
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2021-10-30 12:57:08 +02:00 |
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Eyck Jentzsch
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a20f39e847
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update core definitions to include Zicsr and Zifencei (#276)
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2021-10-30 12:56:31 +02:00 |
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Eyck Jentzsch
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334d3fb296
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adapt to SCC changes
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2021-10-21 22:53:16 +02:00 |
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Eyck Jentzsch
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1d13c8196e
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fix wrong PGMASK usage
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2021-10-11 10:40:01 +02:00 |
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Eyck Jentzsch
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b17682e50e
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fix YAML template
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2021-10-01 23:49:04 +02:00 |
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Eyck Jentzsch
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6acf73a40f
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add template to generate instruction YAML
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2021-10-01 13:05:36 +02:00 |
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Eyck Jentzsch
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2f15d9676e
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fix unaligned instr fetch behavior
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2021-09-30 19:27:46 +02:00 |
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Eyck Jentzsch
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4186723d37
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add marchid setting to CoreDSL description
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2021-09-30 19:26:21 +02:00 |
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Eyck Jentzsch
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aa84a27a5b
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fix JALR alignment in description
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2021-09-29 00:43:42 +02:00 |
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Eyck Jentzsch
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438e598a4a
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remove clutter from core descriptions, added instr alignment setting
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2021-09-29 00:03:11 +02:00 |
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Eyck Jentzsch
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174259155d
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add support for non-compressed ISA
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2021-09-23 21:09:52 +02:00 |
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Eyck Jentzsch
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a3084456fd
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rework core definitions
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2021-09-04 12:47:07 +02:00 |
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Eyck Jentzsch
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adeffe47ad
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fix behavior of riscv_hart_mu_p to match TGC_D
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2021-08-12 20:34:10 +02:00 |
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Eyck Jentzsch
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d95846a849
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fix trap handling if illegal fetch (PMP) and U-mode CSRs
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2021-08-01 17:23:22 +02:00 |
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Eyck Jentzsch
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e68918c2e8
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fix instruction decode
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2021-07-09 07:37:12 +02:00 |
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Eyck Jentzsch
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2f4b5bd9b2
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fix detailed behavior of TGC_C
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2021-07-06 21:19:36 +02:00 |
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Eyck Jentzsch
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23b9741adf
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refine and fix TGC_C iss to becoem compliant
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2021-06-29 11:51:30 +02:00 |
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Eyck Jentzsch
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e432dd8208
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fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
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Eyck Jentzsch
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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Eyck Jentzsch
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cf7b62a3f9
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update names
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2021-05-13 15:54:48 +02:00 |
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Eyck Jentzsch
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32e4aa83b8
|
use extracted variables
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2021-03-27 09:36:52 +00:00 |
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Eyck Jentzsch
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78c7064295
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update groovy template to extract used registers
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2021-03-26 08:24:45 +00:00 |
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Eyck Jentzsch
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b0bcb7febb
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small fixes for robustness and readability
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2021-03-22 22:47:30 +00:00 |
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Eyck Jentzsch
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4e0f20eba0
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rework abort conditions
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2021-03-17 19:32:57 +00:00 |
|
Eyck Jentzsch
|
ff3fa19208
|
fix RVM description bugs
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2021-03-13 10:46:41 +00:00 |
|
Eyck Jentzsch
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80057eef32
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fix RVC description bugs, remove paged fetch
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2021-03-13 10:46:41 +00:00 |
|
Eyck Jentzsch
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f4ec21007b
|
fix signedness issues
|
2021-03-11 16:12:28 +00:00 |
|
Eyck Jentzsch
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ac8eab6e25
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update RISC-V desciptions
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2021-03-10 17:31:10 +00:00 |
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Eyck Jentzsch
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bea0dcc387
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update missing XLEN
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2021-03-09 11:03:37 +00:00 |
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Eyck Jentzsch
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a6691bcd3c
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update generated code with correct sign extension
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2021-03-09 10:21:36 +00:00 |
|
Eyck Jentzsch
|
c171e3c1ba
|
update CoreDSL descriptions
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2021-03-07 10:51:15 +00:00 |
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Eyck Jentzsch
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c251fe15d5
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fix desscriptions to conform to ISA spec version 20191213 and TGF-C
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2021-03-07 10:51:00 +00:00 |
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Eyck Jentzsch
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dae8acb8a3
|
checkpoint before refactor
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2021-03-06 07:17:42 +00:00 |
|
Eyck Jentzsch
|
be0e7db185
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fix templates to comply with CoreDSL2
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2021-03-01 21:07:20 +00:00 |
|
Eyck Jentzsch
|
9534d58d01
|
regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
|
Eyck Jentzsch
|
1668df0531
|
regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
|
Eyck Jentzsch
|
d8e009c72b
|
update CoreDSL decriptions
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2021-02-15 18:15:13 +00:00 |
|
Eyck Jentzsch
|
72b09472d5
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update RISC-V descriptions
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2021-02-15 18:01:33 +00:00 |