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b0cb997009
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add TGC_X with DMR
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2022-03-26 10:48:21 +01:00 |
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9dfca612b7
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add hardware loop CSR access
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2022-03-25 11:33:44 +01:00 |
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d91f5f9df4
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fix compiler warning for reduced number of registers
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2022-03-14 15:38:05 +01:00 |
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b37ef973de
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clean up
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2022-02-14 20:36:12 +01:00 |
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4c363f4073
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adds additional functionality by fetching delay information
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2022-02-11 11:28:00 +01:00 |
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b8fa5fbbda
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adapt to extended instrumentation interface
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2022-02-09 21:01:17 +01:00 |
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09b0f0d0c8
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fix cycle estimation plugin
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2022-02-01 21:14:50 +01:00 |
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98b418ff43
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fix JSON reading
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2022-02-01 19:28:11 +01:00 |
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059bd0d371
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rework cycle estimation
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2022-02-01 19:03:45 +01:00 |
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7578906310
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adds coverage plugin
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2022-01-31 21:38:18 +01:00 |
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afe8905ac9
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fix else-ambiguity in CoreDSL description
|
2022-01-31 20:30:46 +01:00 |
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ecc6091d1e
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cleans up source code to remove clang compiler warnings
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2022-01-19 08:01:15 +01:00 |
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dd4c19a15c
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add option to configure number of irq
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2021-12-01 12:56:36 +01:00 |
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86da31033c
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correct size usage in pmp addr checks
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2021-11-22 15:15:47 +01:00 |
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974d103381
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fix pmpcfg register write
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2021-11-22 10:49:29 +01:00 |
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309758b994
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fix clic_cfg access scheme
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2021-11-17 07:59:02 +01:00 |
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d47375a70e
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fix ebreak CSR update
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2021-11-13 12:47:23 +01:00 |
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43d7b99905
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revert pmp check implementation
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2021-11-11 09:58:19 +01:00 |
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2d7973520b
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fix mip handling
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2021-11-09 19:47:34 +01:00 |
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fd98ad95f6
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rework PMP check and fix MISA for TGC_D
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2021-11-09 15:55:22 +01:00 |
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bfa8166223
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fix wrong template class name
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2021-11-08 10:44:33 +01:00 |
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c42e336509
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fix proper debug mode handling (#267 & #268)
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2021-11-07 17:48:44 +01:00 |
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49d09a05d7
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fix access rights to debug CSR register (#268)
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2021-11-07 16:45:10 +01:00 |
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459794b863
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add proper handling of store access fault (hart_mu_p)
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2021-11-06 13:29:11 +01:00 |
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039746112b
|
fix exception behavior
|
2021-11-02 15:10:20 +01:00 |
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ac6d7ea5d4
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add debug feature to platform
|
2021-11-02 11:13:29 +01:00 |
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1616f0ac90
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remove deprecated functions
|
2021-10-30 12:57:08 +02:00 |
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334d3fb296
|
adapt to SCC changes
|
2021-10-21 22:53:16 +02:00 |
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0ea4cba1ca
|
add dynamic plugin loading
|
2021-10-12 14:24:55 +02:00 |
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ee6e1d4092
|
Merge remote-tracking branch 'origin/msvc_compat' into develop
Conflicts:
src/sysc/core_complex.cpp
|
2021-10-11 09:42:40 +02:00 |
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f0ada1ba8c
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add MSVC 16 compatibility
|
2021-10-10 19:06:41 +02:00 |
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2f15d9676e
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fix unaligned instr fetch behavior
|
2021-09-30 19:27:46 +02:00 |
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d78fcc48e5
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use marchid in platform
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2021-09-30 19:27:03 +02:00 |
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438e598a4a
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remove clutter from core descriptions, added instr alignment setting
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2021-09-29 00:03:11 +02:00 |
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174259155d
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add support for non-compressed ISA
|
2021-09-23 21:09:52 +02:00 |
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ba9339a50d
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fix MPP reset value, PMP inactive in U-mode handling and MRET in U-mode
|
2021-09-21 16:52:40 +02:00 |
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65b4db5eca
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remove mcounteren in M-mode only platform
|
2021-09-18 11:40:00 +02:00 |
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09b01af3fa
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fix find_package use and debug access alignment check
|
2021-08-26 22:10:27 +02:00 |
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9c8b72693e
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correct trap ids of access faults
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2021-08-20 09:02:56 +02:00 |
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2f05083cf0
|
fix elf loader and pmp check for debug accesses
|
2021-08-19 10:50:25 +02:00 |
|
Eyck Jentzsch
|
94f796ebdb
|
add install target and PA compatibility
|
2021-08-16 17:02:31 +02:00 |
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836ba269e3
|
fix clic reset values
|
2021-08-16 15:05:05 +02:00 |
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adeffe47ad
|
fix behavior of riscv_hart_mu_p to match TGC_D
|
2021-08-12 20:34:10 +02:00 |
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d95846a849
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fix trap handling if illegal fetch (PMP) and U-mode CSRs
|
2021-08-01 17:23:22 +02:00 |
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af887c286f
|
fix for #2
|
2021-07-28 09:09:08 +02:00 |
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5ef5d57d30
|
Merge branch 'tmp' into develop
|
2021-07-27 10:49:35 +02:00 |
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d7bddd825c
|
add clic CSRs
|
2021-07-27 10:47:48 +02:00 |
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15f46a87db
|
adapt core_complex to use scv-tr (scc commit id a3cde47)
|
2021-07-27 09:38:05 +02:00 |
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d0f3a120fd
|
fix naming in MU wrapper
|
2021-07-19 16:26:23 +02:00 |
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c592a26346
|
fix mepc mask
|
2021-07-09 13:01:22 +02:00 |
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