DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

add MSVC 16 compatibility

Browse Source
This commit is contained in:
Eyck Jentzsch
2021-10-10 19:06:41 +02:00
parent 09b01af3fa
commit f0ada1ba8c
8 changed files with 54 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
incl/iss/arch/riscv_hart_m_p.h
View File

@ -397,7 +397,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
traits<BASE>::MEM, pseg->get_physical_address(),
fsize, reinterpret_cast<const uint8_t *const>(seg_data));
if (res != iss::Ok)
LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
<< pseg->get_physical_address();
}
}
@ -948,7 +948,11 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
this->reg.PRIV = PRIV_M;
this->reg.trap_state = 0;
std::array<char, 32> buffer;
#if defined(_MSC_VER)
sprintf(buffer.data(), "0x%016llx", addr);
#else
sprintf(buffer.data(), "0x%016lx", addr);
#endif
if((flags&0xffffffff) != 0xffffffff)
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"