add install target and PA compatibility
This commit is contained in:
@ -1,5 +1,5 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* Copyright (C) 2017-2021 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -30,18 +30,23 @@
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _SYSC_SIFIVE_FE310_H_
|
||||
#define _SYSC_SIFIVE_FE310_H_
|
||||
#ifndef _SYSC_CORE_COMPLEX_H_
|
||||
#define _SYSC_CORE_COMPLEX_H_
|
||||
|
||||
#include "tlm/scc/initiator_mixin.h"
|
||||
#include "scc/traceable.h"
|
||||
#include "scc/utilities.h"
|
||||
#include "tlm/scc/scv/tlm_rec_initiator_socket.h"
|
||||
#include <tlm/scc/initiator_mixin.h>
|
||||
#include <scc/traceable.h>
|
||||
#include <scc/tick2time.h>
|
||||
#include <scc/utilities.h>
|
||||
#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
|
||||
#ifdef CWR_SYSTEMC
|
||||
#include <scmlinc/scml_property.h>
|
||||
#else
|
||||
#include <cci_configuration>
|
||||
#endif
|
||||
#include <tlm>
|
||||
#include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
|
||||
#include <tlm_utils/tlm_quantumkeeper.h>
|
||||
#include <util/range_lut.h>
|
||||
#include <memory>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
@ -63,8 +68,6 @@ class core_complex : public sc_core::sc_module, public scc::traceable {
|
||||
public:
|
||||
tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
|
||||
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
|
||||
|
||||
sc_core::sc_in<bool> rst_i{"rst_i"};
|
||||
|
||||
sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
|
||||
@ -75,6 +78,9 @@ public:
|
||||
|
||||
sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i{"local_irq_i", 16};
|
||||
|
||||
#ifndef CWR_SYSTEMC
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
|
||||
|
||||
sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
|
||||
|
||||
cci::cci_param<std::string> elf_file{"elf_file", ""};
|
||||
@ -93,7 +99,47 @@ public:
|
||||
|
||||
cci::cci_param<uint32_t> mhartid{"mhartid", 0};
|
||||
|
||||
core_complex(sc_core::sc_module_name name);
|
||||
core_complex(sc_core::sc_module_name const& name);
|
||||
|
||||
#else
|
||||
sc_core::sc_in<bool> clk_i{"clk_i"};
|
||||
|
||||
sc_core::sc_in<uint64_t> mtime_i{"mtime_i"};
|
||||
|
||||
scml_property<std::string> elf_file{"elf_file", ""};
|
||||
|
||||
scml_property<bool> enable_disass{"enable_disass", false};
|
||||
|
||||
scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
|
||||
|
||||
scml_property<std::string> core_type{"core_type", "tgc_c"};
|
||||
|
||||
scml_property<std::string> backend{"backend", "interp"};
|
||||
|
||||
scml_property<unsigned> gdb_server_port{"gdb_server_port", 0};
|
||||
|
||||
scml_property<bool> dump_ir{"dump_ir", false};
|
||||
|
||||
scml_property<uint32_t> mhartid{"mhartid", 0};
|
||||
|
||||
core_complex(sc_core::sc_module_name const& name)
|
||||
: sc_module(name)
|
||||
, local_irq_i{"local_irq_i", 16}
|
||||
, elf_file{"elf_file", ""}
|
||||
, enable_disass{"enable_disass", false}
|
||||
, reset_address{"reset_address", 0ULL}
|
||||
, core_type{"core_type", "tgc_c"}
|
||||
, backend{"backend", "interp"}
|
||||
, gdb_server_port{"gdb_server_port", 0}
|
||||
, dump_ir{"dump_ir", false}
|
||||
, mhartid{"mhartid", 0}
|
||||
, read_lut(tlm_dmi_ext())
|
||||
, write_lut(tlm_dmi_ext())
|
||||
{
|
||||
init();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
~core_complex();
|
||||
|
||||
@ -119,11 +165,12 @@ public:
|
||||
|
||||
bool disass_output(uint64_t pc, const std::string instr);
|
||||
|
||||
void set_clock_period(sc_core::sc_time period);
|
||||
protected:
|
||||
void before_end_of_elaboration() override;
|
||||
void start_of_simulation() override;
|
||||
void forward();
|
||||
void run();
|
||||
void clk_cb();
|
||||
void rst_cb();
|
||||
void sw_irq_cb();
|
||||
void timer_irq_cb();
|
||||
@ -132,12 +179,14 @@ protected:
|
||||
util::range_lut<tlm_dmi_ext> read_lut, write_lut;
|
||||
tlm_utils::tlm_quantumkeeper quantum_keeper;
|
||||
std::vector<uint8_t> write_buf;
|
||||
std::unique_ptr<core_wrapper> cpu;
|
||||
sc_core::sc_time curr_clk;
|
||||
std::unique_ptr<core_trace> trc;
|
||||
core_wrapper* cpu{nullptr};
|
||||
sc_core::sc_signal<sc_core::sc_time> curr_clk;
|
||||
core_trace* trc{nullptr};
|
||||
std::unique_ptr<scc::tick2time> t2t;
|
||||
private:
|
||||
void init();
|
||||
};
|
||||
|
||||
} /* namespace SiFive */
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* _SYSC_SIFIVE_FE310_H_ */
|
||||
#endif /* _SYSC_CORE_COMPLEX_H_ */
|
||||
|
Reference in New Issue
Block a user