Commit Graph

424 Commits

Author SHA1 Message Date
Eyck Jentzsch a20eab0c2b Merge branch 'feature/update_coredsl' into develop 2023-07-05 15:15:06 +02:00
Eyck Jentzsch a32c83e1be fixes CLI handling of plugin paramters in ISS 2023-07-05 08:32:05 +02:00
Eyck Jentzsch 7e45a25218 adds a instr yaml for TGC 2023-07-05 08:28:42 +02:00
Eyck Jentzsch f796c24a26 prepares templates for CoreDSL 2.0.9 drop 2023-07-03 20:59:16 +02:00
Eyck Jentzsch 4dbc7433a5 fixes cause CSR handling 2023-06-12 17:38:56 +02:00
Eyck Jentzsch 99a9970ddd fixes sysc compile issues 2023-06-12 09:58:24 +02:00
Eyck Jentzsch 0b5de90fb1 changes [m|u]cause rd/wr handling 2023-06-11 18:29:58 +02:00
Eyck Jentzsch 60d07f2eb6 changes default loglevel to info for tgc-sim 2023-06-01 06:55:21 +02:00
Eyck Jentzsch a123beb301 fixes duplicate variable declaration and templates 2023-05-27 10:20:49 +02:00
Eyck Jentzsch ee6218279e adapts to latest code gen changes 2023-05-25 12:52:30 +02:00
Eyck-Alexander Jentzsch ce5b2e60b9 amends template to fix branching instructions 2023-05-22 17:00:36 +02:00
Eyck-Alexander Jentzsch c792f50427 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-05-16 21:57:32 +02:00
Eyck-Alexander Jentzsch 6ed7eafc5d adds inital version of tcc backend 2023-05-16 21:51:35 +02:00
Eyck Jentzsch 8a5fe58d51 adds needed arch state members for TCC to tgc_c 2023-05-16 08:56:18 +02:00
Eyck Jentzsch 16cd6d5ff5 fixes core name deduction in cmake build script 2023-05-16 08:54:08 +02:00
Eyck-Alexander Jentzsch ee2ded931d adds remaining register offsets 2023-05-14 17:16:42 +02:00
Eyck Jentzsch 95ba5c901a re-introduces last_branch register 2023-05-14 17:00:37 +02:00
Eyck Jentzsch 32848ec396 fixes build system and typo in wt_cache 2023-05-13 16:57:01 +02:00
Eyck Jentzsch 6789cf4c32 fixes case of unavailable backend 2023-05-12 15:45:53 +02:00
Eyck Jentzsch 3bc4884a9d remove unneeded cmake include 2023-05-12 09:28:43 +02:00
Eyck Jentzsch fd6b738168 changes compile dependencies 2023-05-11 23:43:12 +02:00
Eyck Jentzsch afdf8fb97f adds missing namespaces 2023-05-11 23:11:04 +02:00
Eyck Jentzsch cfa7b72363 changes time handling at sockets 2023-05-06 19:57:29 +02:00
Eyck Jentzsch d330307ed5 splits bus into 2 sockets for i/dbus 2023-05-04 21:59:31 +02:00
Eyck Jentzsch 916de2a26d changes build setup to compile specific files if a core is specified 2023-05-04 16:08:33 +02:00
Eyck Jentzsch aa70d8a54a fixes CLIC to match clicinfo description in CLIC spec 11.04.2023 2023-05-02 17:22:13 +02:00
Eyck Jentzsch b493745cd7 sets reset start time to 0 2023-05-02 11:21:42 +02:00
Eyck Jentzsch f9e8e1d857 fixes core_complex wrt. tlm quantum and DMI 2023-05-02 11:13:25 +02:00
Eyck Jentzsch 974d64a627 adds logo to imported instance 2023-05-02 08:17:17 +02:00
Eyck Jentzsch d70489cbb8 update import script to initialize broker 2023-05-02 07:58:48 +02:00
Eyck Jentzsch d990f1cf5d fixes reading of 64bit CSR register 2023-05-01 22:23:35 +02:00
Eyck Jentzsch 1672b01e62 adds WT cache functionality as mixin 2023-04-28 20:38:07 +02:00
Eyck Jentzsch 00b0f101ac adapts to changes of instrumentation interface in dbt-rise-core 2023-04-28 20:38:07 +02:00
Rocco Jonack 54f75f92ea improved testbench import; added prebuild FW for testing 2023-04-24 08:44:12 -07:00
Rocco Jonack 0304aac9e5 fixed some issues in import script; added README for reference; added initial testbench script(to be improved) 2023-04-19 05:20:58 -07:00
Eyck Jentzsch 8ff55d7b92 updates CWR dependent core_complex definition 2023-04-14 19:34:41 +02:00
Eyck Jentzsch f626ee2684 fixes privilege wrapper for M/U to cope with 64bit 2023-04-05 15:38:25 +02:00
Eyck Jentzsch a8a2782329 adds changes from latest CoreDSL description 2023-04-04 16:10:12 +02:00
Eyck Jentzsch 98dd329833 fixes CSR access rights 2023-04-04 09:23:08 +02:00
Eyck Jentzsch 6213445bc4 fixes 64bit behavior of CSR regs 2023-03-27 12:04:43 +02:00
Eyck Jentzsch c5465bf9e2 fixes according to fixed generator 2023-03-26 14:44:15 +02:00
Eyck Jentzsch d881cb6e63 fix data width of generated code 2023-03-26 12:12:34 +02:00
Eyck Jentzsch 2e4faa4d50 fixes mstatus mask 2023-03-25 09:14:56 +01:00
Eyck Jentzsch 8e1951f298 adds 64bit mstatus 2023-03-23 07:47:21 +01:00
Eyck Jentzsch 7efa924510 fixes m/uintstatus read 2023-03-17 10:51:39 +01:00
Eyck Jentzsch febbc4fff0 fixes m/uintstatus read 2023-03-17 10:23:05 +01:00
Eyck Jentzsch 39b2788b7e implements and fixes CLIC CSR behavior 2023-03-17 09:09:09 +01:00
Eyck Jentzsch a943dd3bdf fixes wrong array size which led to unintended CSR definitions 2023-03-15 14:16:08 +01:00
Eyck Jentzsch fedbff5971 fixes xcause and u-mode clic CSRs 2023-03-15 12:27:39 +01:00
Eyck Jentzsch c2758e8321 removes mscratchcsw from CLIC feature 2023-03-15 09:07:00 +01:00