 Eyck Jentzsch
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5da4e6b424
|
fix alignment check for unaligned debugger accesses
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2022-05-13 12:37:47 +02:00 |
|
Eyck Jentzsch
|
e88f309ea2
|
add lz4 compression to pctrace
|
2022-05-07 17:22:06 +02:00 |
|
Eyck Jentzsch
|
03bec27376
|
implement extended instrumentation interface
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2022-04-26 17:14:33 +02:00 |
|
Eyck Jentzsch
|
9d9008a3a2
|
fix pointer mess
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2022-04-26 15:35:17 +02:00 |
|
Eyck Jentzsch
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a92b84bef4
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add code word access for ISS plugins
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2022-04-25 14:18:19 +02:00 |
|
Eyck Jentzsch
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477c530847
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extend debug mode handling
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2022-04-13 11:41:01 +02:00 |
|
Eyck Jentzsch
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c054d75717
|
update to latest coredsl description
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2022-04-10 18:55:44 +02:00 |
|
Eyck Jentzsch
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00d2d06cbd
|
adapt to privileged spec
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2022-03-31 20:33:12 +02:00 |
|
Eyck Jentzsch
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8e4e702cb9
|
Merge remote-tracking branch 'origin/feature/reduced_output' into develop
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2022-03-28 14:09:06 +02:00 |
|
Eyck Jentzsch
|
49be143588
|
make features configurable
|
2022-03-27 17:54:08 +02:00 |
|
Eyck Jentzsch
|
0aea1d0177
|
remove mcounteren in M-mode only wrapper
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2022-03-27 17:21:46 +02:00 |
|
Eyck Jentzsch
|
6ea7721961
|
add TCM
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2022-03-27 15:38:18 +02:00 |
|
Eyck Jentzsch
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b0cb997009
|
add TGC_X with DMR
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2022-03-26 10:48:21 +01:00 |
|
Eyck Jentzsch
|
9dfca612b7
|
add hardware loop CSR access
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2022-03-25 11:33:44 +01:00 |
|
Eyck Jentzsch
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d91f5f9df4
|
fix compiler warning for reduced number of registers
|
2022-03-14 15:38:05 +01:00 |
 Eyck-Alexander Jentzsch
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2bba5645c3
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adds functionality to reduce the output
|
2022-02-16 10:13:29 +01:00 |
|
Eyck Jentzsch
|
b37ef973de
|
clean up
|
2022-02-14 20:36:12 +01:00 |
|
Eyck-Alexander Jentzsch
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4c363f4073
|
adds additional functionality by fetching delay information
|
2022-02-11 11:28:00 +01:00 |
|
Eyck Jentzsch
|
b8fa5fbbda
|
adapt to extended instrumentation interface
|
2022-02-09 21:01:17 +01:00 |
|
Eyck Jentzsch
|
09b0f0d0c8
|
fix cycle estimation plugin
|
2022-02-01 21:14:50 +01:00 |
|
Eyck Jentzsch
|
98b418ff43
|
fix JSON reading
|
2022-02-01 19:28:11 +01:00 |
|
Eyck Jentzsch
|
059bd0d371
|
rework cycle estimation
|
2022-02-01 19:03:45 +01:00 |
|
Eyck-Alexander Jentzsch
|
7578906310
|
adds coverage plugin
|
2022-01-31 21:38:18 +01:00 |
|
Eyck Jentzsch
|
afe8905ac9
|
fix else-ambiguity in CoreDSL description
|
2022-01-31 20:30:46 +01:00 |
|
Eyck-Alexander Jentzsch
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ecc6091d1e
|
cleans up source code to remove clang compiler warnings
|
2022-01-19 08:01:15 +01:00 |
|
Eyck Jentzsch
|
dd4c19a15c
|
add option to configure number of irq
|
2021-12-01 12:56:36 +01:00 |
 Maribel Gomez
|
86da31033c
|
correct size usage in pmp addr checks
|
2021-11-22 15:15:47 +01:00 |
|
Maribel Gomez
|
974d103381
|
fix pmpcfg register write
|
2021-11-22 10:49:29 +01:00 |
|
Eyck Jentzsch
|
309758b994
|
fix clic_cfg access scheme
|
2021-11-17 07:59:02 +01:00 |
|
Eyck Jentzsch
|
d47375a70e
|
fix ebreak CSR update
|
2021-11-13 12:47:23 +01:00 |
|
Eyck Jentzsch
|
43d7b99905
|
revert pmp check implementation
|
2021-11-11 09:58:19 +01:00 |
|
Eyck Jentzsch
|
2d7973520b
|
fix mip handling
|
2021-11-09 19:47:34 +01:00 |
|
Eyck Jentzsch
|
fd98ad95f6
|
rework PMP check and fix MISA for TGC_D
|
2021-11-09 15:55:22 +01:00 |
|
Eyck Jentzsch
|
bfa8166223
|
fix wrong template class name
|
2021-11-08 10:44:33 +01:00 |
|
Eyck Jentzsch
|
c42e336509
|
fix proper debug mode handling (#267 & #268)
|
2021-11-07 17:48:44 +01:00 |
|
Eyck Jentzsch
|
49d09a05d7
|
fix access rights to debug CSR register (#268)
|
2021-11-07 16:45:10 +01:00 |
|
Eyck Jentzsch
|
459794b863
|
add proper handling of store access fault (hart_mu_p)
|
2021-11-06 13:29:11 +01:00 |
|
Eyck Jentzsch
|
039746112b
|
fix exception behavior
|
2021-11-02 15:10:20 +01:00 |
|
Eyck Jentzsch
|
ac6d7ea5d4
|
add debug feature to platform
|
2021-11-02 11:13:29 +01:00 |
|
Eyck Jentzsch
|
1616f0ac90
|
remove deprecated functions
|
2021-10-30 12:57:08 +02:00 |
|
Eyck Jentzsch
|
334d3fb296
|
adapt to SCC changes
|
2021-10-21 22:53:16 +02:00 |
|
Eyck Jentzsch
|
0ea4cba1ca
|
add dynamic plugin loading
|
2021-10-12 14:24:55 +02:00 |
|
Eyck Jentzsch
|
ee6e1d4092
|
Merge remote-tracking branch 'origin/msvc_compat' into develop
Conflicts:
src/sysc/core_complex.cpp
|
2021-10-11 09:42:40 +02:00 |
|
Eyck Jentzsch
|
f0ada1ba8c
|
add MSVC 16 compatibility
|
2021-10-10 19:06:41 +02:00 |
|
Eyck Jentzsch
|
2f15d9676e
|
fix unaligned instr fetch behavior
|
2021-09-30 19:27:46 +02:00 |
|
Eyck Jentzsch
|
d78fcc48e5
|
use marchid in platform
|
2021-09-30 19:27:03 +02:00 |
|
Eyck Jentzsch
|
438e598a4a
|
remove clutter from core descriptions, added instr alignment setting
|
2021-09-29 00:03:11 +02:00 |
|
Eyck Jentzsch
|
174259155d
|
add support for non-compressed ISA
|
2021-09-23 21:09:52 +02:00 |
|
Eyck Jentzsch
|
ba9339a50d
|
fix MPP reset value, PMP inactive in U-mode handling and MRET in U-mode
|
2021-09-21 16:52:40 +02:00 |
|
Eyck Jentzsch
|
65b4db5eca
|
remove mcounteren in M-mode only platform
|
2021-09-18 11:40:00 +02:00 |