DBT-RISE/DBT-RISE-TGC
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add code word access for ISS plugins

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This commit is contained in:
Eyck Jentzsch
2022-04-25 14:18:19 +02:00
parent 477c530847
commit a92b84bef4
9 changed files with 42 additions and 33 deletions
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8
incl/iss/arch/riscv_hart_m_p.h
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@ -235,9 +235,11 @@ protected:
*/
const std::string core_type_name() const override { return traits<BASE>::core_type; }
uint64_t get_pc() override { return arch.get_pc(); };
uint64_t get_pc() override { return arch.reg.PC; };
uint64_t get_next_pc() override { return arch.get_next_pc(); };
uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
uint64_t get_instr_word() override { return arch.reg.instruction; }
uint64_t get_instr_count() { return arch.reg.icount; }
@ -249,8 +251,6 @@ protected:
};
friend struct riscv_instrumentation_if;
addr_t get_pc() { return this->reg.PC; }
addr_t get_next_pc() { return this->reg.NEXT_PC; }
virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);

14
incl/iss/arch/tgc_c.h
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@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
static constexpr std::array<const char*, 36> reg_aliases{
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, INSTR_ALIGNMENT=2, XLEN=32, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0;
@ -63,7 +63,8 @@ template <> struct traits<tgc_c> {
PENDING_TRAP,
ICOUNT,
CYCLE,
INSTRET
INSTRET,
INSTRUCTION
};
using reg_t = uint32_t;
@ -76,11 +77,11 @@ template <> struct traits<tgc_c> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 41> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64}};
static constexpr std::array<const uint32_t, 42> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32}};
static constexpr std::array<const uint32_t, 41> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165}};
static constexpr std::array<const uint32_t, 42> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
@ -259,6 +260,7 @@ struct tgc_c: public arch_if {
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t instret = 0;
uint32_t instruction = 0;
uint32_t last_branch;
} reg;
#pragma pack(pop)