DBT-RISE
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DBT-RISE-TGC
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Commit Graph

106 Commits

Author SHA1 Message Date
Eyck Jentzsch 0aea1d0177 remove mcounteren in M-mode only wrapper 2022-03-27 17:21:46 +02:00
Eyck Jentzsch 6ea7721961 add TCM 2022-03-27 15:38:18 +02:00
Eyck Jentzsch b0cb997009 add TGC_X with DMR 2022-03-26 10:48:21 +01:00
Eyck Jentzsch 9dfca612b7 add hardware loop CSR access 2022-03-25 11:33:44 +01:00
Eyck Jentzsch d91f5f9df4 fix compiler warning for reduced number of registers 2022-03-14 15:38:05 +01:00
Eyck Jentzsch b37ef973de clean up 2022-02-14 20:36:12 +01:00
Eyck-Alexander Jentzsch 4c363f4073 adds additional functionality by fetching delay information 2022-02-11 11:28:00 +01:00
Eyck Jentzsch b8fa5fbbda adapt to extended instrumentation interface 2022-02-09 21:01:17 +01:00
Eyck Jentzsch 09b0f0d0c8 fix cycle estimation plugin 2022-02-01 21:14:50 +01:00
Eyck Jentzsch 98b418ff43 fix JSON reading 2022-02-01 19:28:11 +01:00
Eyck Jentzsch 059bd0d371 rework cycle estimation 2022-02-01 19:03:45 +01:00
Eyck-Alexander Jentzsch 7578906310 adds coverage plugin 2022-01-31 21:38:18 +01:00
Eyck Jentzsch afe8905ac9 fix else-ambiguity in CoreDSL description 2022-01-31 20:30:46 +01:00
Eyck-Alexander Jentzsch ecc6091d1e cleans up source code to remove clang compiler warnings 2022-01-19 08:01:15 +01:00
Eyck Jentzsch dd4c19a15c add option to configure number of irq 2021-12-01 12:56:36 +01:00
Maribel Gomez 86da31033c correct size usage in pmp addr checks 2021-11-22 15:15:47 +01:00
Maribel Gomez 974d103381 fix pmpcfg register write 2021-11-22 10:49:29 +01:00
Eyck Jentzsch 309758b994 fix clic_cfg access scheme 2021-11-17 07:59:02 +01:00
Eyck Jentzsch d47375a70e fix ebreak CSR update 2021-11-13 12:47:23 +01:00
Eyck Jentzsch 43d7b99905 revert pmp check implementation 2021-11-11 09:58:19 +01:00
Eyck Jentzsch 2d7973520b fix mip handling 2021-11-09 19:47:34 +01:00
Eyck Jentzsch fd98ad95f6 rework PMP check and fix MISA for TGC_D 2021-11-09 15:55:22 +01:00
Eyck Jentzsch bfa8166223 fix wrong template class name 2021-11-08 10:44:33 +01:00
Eyck Jentzsch c42e336509 fix proper debug mode handling (#267 & #268) 2021-11-07 17:48:44 +01:00
Eyck Jentzsch 49d09a05d7 fix access rights to debug CSR register (#268) 2021-11-07 16:45:10 +01:00
Eyck Jentzsch 459794b863 add proper handling of store access fault (hart_mu_p) 2021-11-06 13:29:11 +01:00
Eyck Jentzsch 039746112b fix exception behavior 2021-11-02 15:10:20 +01:00
Eyck Jentzsch ac6d7ea5d4 add debug feature to platform 2021-11-02 11:13:29 +01:00
Eyck Jentzsch 1616f0ac90 remove deprecated functions 2021-10-30 12:57:08 +02:00
Eyck Jentzsch 334d3fb296 adapt to SCC changes 2021-10-21 22:53:16 +02:00
Eyck Jentzsch 0ea4cba1ca add dynamic plugin loading 2021-10-12 14:24:55 +02:00
Eyck Jentzsch ee6e1d4092 Merge remote-tracking branch 'origin/msvc_compat' into develop 
Conflicts:
	src/sysc/core_complex.cpp
 2021-10-11 09:42:40 +02:00
Eyck Jentzsch f0ada1ba8c add MSVC 16 compatibility 2021-10-10 19:06:41 +02:00
Eyck Jentzsch 2f15d9676e fix unaligned instr fetch behavior 2021-09-30 19:27:46 +02:00
Eyck Jentzsch d78fcc48e5 use marchid in platform 2021-09-30 19:27:03 +02:00
Eyck Jentzsch 438e598a4a remove clutter from core descriptions, added instr alignment setting 2021-09-29 00:03:11 +02:00
Eyck Jentzsch 174259155d add support for non-compressed ISA 2021-09-23 21:09:52 +02:00
Eyck Jentzsch ba9339a50d fix MPP reset value, PMP inactive in U-mode handling and MRET in U-mode 2021-09-21 16:52:40 +02:00
Eyck Jentzsch 65b4db5eca remove mcounteren in M-mode only platform 2021-09-18 11:40:00 +02:00
Eyck Jentzsch 09b01af3fa fix find_package use and debug access alignment check 2021-08-26 22:10:27 +02:00
Eyck Jentzsch 9c8b72693e correct trap ids of access faults 2021-08-20 09:02:56 +02:00
Eyck Jentzsch 2f05083cf0 fix elf loader and pmp check for debug accesses 2021-08-19 10:50:25 +02:00
Eyck Jentzsch 94f796ebdb add install target and PA compatibility 2021-08-16 17:02:31 +02:00
Eyck Jentzsch 836ba269e3 fix clic reset values 2021-08-16 15:05:05 +02:00
Eyck Jentzsch adeffe47ad fix behavior of riscv_hart_mu_p to match TGC_D 2021-08-12 20:34:10 +02:00
Eyck Jentzsch d95846a849 fix trap handling if illegal fetch (PMP) and U-mode CSRs 2021-08-01 17:23:22 +02:00
Eyck Jentzsch af887c286f fix for #2 2021-07-28 09:09:08 +02:00
Eyck Jentzsch 5ef5d57d30 Merge branch 'tmp' into develop 2021-07-27 10:49:35 +02:00
Eyck Jentzsch d7bddd825c add clic CSRs 2021-07-27 10:47:48 +02:00
Eyck Jentzsch 15f46a87db adapt core_complex to use scv-tr (scc commit id a3cde47) 2021-07-27 09:38:05 +02:00