 Eyck Jentzsch
|
813b40409d
|
Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
|
2023-08-30 10:05:42 +02:00 |
|
Eyck Jentzsch
|
c8a4a4c736
|
renames core(s)
|
2023-08-28 07:09:55 +02:00 |
|
Eyck Jentzsch
|
18e08cfc50
|
fixes missing template updates
|
2023-08-08 06:23:38 +02:00 |
|
Eyck Jentzsch
|
20e920338c
|
removes v2p function
|
2023-08-04 13:08:10 +02:00 |
|
Eyck Jentzsch
|
e151416f58
|
fixes systemc factory registration
|
2023-07-31 12:55:09 +02:00 |
|
Eyck Jentzsch
|
e68f9c573f
|
Merge branch 'develop' of
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into develop
|
2023-07-30 09:14:58 +02:00 |
|
Eyck Jentzsch
|
f38cc7d8b9
|
updates LLVM build
|
2023-07-29 17:55:37 +02:00 |
 Eyck-Alexander Jentzsch
|
7af7e040da
|
Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
|
2023-07-29 11:47:25 +02:00 |
|
Eyck-Alexander Jentzsch
|
6e52af168b
|
adds faster decoding to tcc and cleans up others
|
2023-07-29 11:42:46 +02:00 |
|
Eyck-Alexander Jentzsch
|
bd0d15f3a2
|
updates template for faster instruction decoding
|
2023-07-23 08:10:57 +02:00 |
|
Eyck Jentzsch
|
720236ec3f
|
add generated core registration
|
2023-07-14 12:51:51 +02:00 |
|
Eyck Jentzsch
|
957145ca84
|
add SystemC ISS factory
|
2023-07-14 11:11:03 +02:00 |
|
Eyck Jentzsch
|
0b719a4b57
|
fixes literal type
|
2023-07-10 20:39:02 +02:00 |
|
Eyck Jentzsch
|
b4b03f7850
|
fixes build system to handle TCC properly
|
2023-07-09 22:20:50 +02:00 |
|
Eyck Jentzsch
|
e95f422aab
|
cleans vm implementation up
|
2023-07-09 20:13:26 +02:00 |
|
Eyck Jentzsch
|
250ea3c980
|
extends factory to support SystemC core wrapper
|
2023-07-09 18:19:59 +02:00 |
|
Eyck-Alexander Jentzsch
|
21d3250e1a
|
changes templates
|
2023-07-09 16:53:59 +02:00 |
|
Eyck-Alexander Jentzsch
|
87b4082633
|
Merge branch 'tmp' into develop
|
2023-07-03 14:22:50 +02:00 |
|
Eyck Jentzsch
|
99a9970ddd
|
fixes sysc compile issues
|
2023-06-12 09:58:24 +02:00 |
|
Eyck-Alexander Jentzsch
|
15cd36dcd4
|
adds fix for compressed instructions and reads
|
2023-06-05 17:57:38 +02:00 |
|
Eyck Jentzsch
|
a123beb301
|
fixes duplicate variable declaration and templates
|
2023-05-27 10:20:49 +02:00 |
|
Eyck-Alexander Jentzsch
|
ce5b2e60b9
|
amends template to fix branching instructions
|
2023-05-22 17:00:36 +02:00 |
|
Eyck-Alexander Jentzsch
|
6ed7eafc5d
|
adds inital version of tcc backend
|
2023-05-16 21:51:35 +02:00 |
|
Eyck-Alexander Jentzsch
|
ee2ded931d
|
adds remaining register offsets
|
2023-05-14 17:16:42 +02:00 |
|
Eyck Jentzsch
|
95ba5c901a
|
re-introduces last_branch register
|
2023-05-14 17:00:37 +02:00 |
|
Eyck Jentzsch
|
00b0f101ac
|
adapts to changes of instrumentation interface in dbt-rise-core
|
2023-04-28 20:38:07 +02:00 |
|
Eyck Jentzsch
|
d881cb6e63
|
fix data width of generated code
|
2023-03-26 12:12:34 +02:00 |
|
Eyck Jentzsch
|
207dbf1071
|
fixes out of range access for register alias names
|
2023-02-17 06:28:30 +01:00 |
|
Eyck Jentzsch
|
65dca13b42
|
fixes WFI miss of interrupt
|
2023-01-14 17:40:21 +01:00 |
|
Eyck Jentzsch
|
7113683ee0
|
moves pending interrupt check before handling trap thus saving 1 cycle
|
2022-10-15 10:47:35 +02:00 |
|
Eyck Jentzsch
|
00e02bf565
|
adds support for different branch types in tracing
|
2022-08-08 06:30:37 +02:00 |
|
Eyck Jentzsch
|
0833198d34
|
aads missing windows compat firx to template
|
2022-07-23 14:36:23 +02:00 |
|
Eyck Jentzsch
|
4876f18ba9
|
adds windows compatibility fixes
|
2022-07-18 11:43:42 +02:00 |
|
Eyck Jentzsch
|
feaa49d367
|
removes decoder again as there is some issue
|
2022-06-20 00:39:11 +02:00 |
|
Eyck Jentzsch
|
18f33b4a68
|
fixes ordering of instructions for decoding
|
2022-06-19 16:52:29 +02:00 |
|
Eyck Jentzsch
|
f096b15dbd
|
factors decoder into separate component
|
2022-06-19 13:17:31 +02:00 |
|
Eyck Jentzsch
|
5d481eb79d
|
fix generation of non-exception code
|
2022-05-30 22:04:16 +02:00 |
|
Eyck Jentzsch
|
52ed8b81a6
|
fixed template to work with previous code generator
|
2022-05-30 14:08:02 +02:00 |
|
Eyck Jentzsch
|
0c542d42aa
|
separate generated sources
|
2022-05-21 12:48:28 +02:00 |
|
Eyck Jentzsch
|
df16378605
|
update template for changed code generator
|
2022-05-18 19:10:34 +02:00 |
|
Eyck Jentzsch
|
e88f309ea2
|
add lz4 compression to pctrace
|
2022-05-07 17:22:06 +02:00 |
|
Eyck Jentzsch
|
9d9008a3a2
|
fix pointer mess
|
2022-04-26 15:35:17 +02:00 |
|
Eyck Jentzsch
|
a92b84bef4
|
add code word access for ISS plugins
|
2022-04-25 14:18:19 +02:00 |
|
Eyck Jentzsch
|
2e670c4d03
|
change interpreter structure
|
2022-03-06 15:11:38 +01:00 |
|
Eyck Jentzsch
|
3d32c33333
|
update gitignore
|
2022-03-05 20:59:45 +01:00 |
|
Eyck Jentzsch
|
521f40a3d6
|
refactored interpreter backend structure
|
2022-03-05 20:59:17 +01:00 |
|
Eyck Jentzsch
|
b8fa5fbbda
|
adapt to extended instrumentation interface
|
2022-02-09 21:01:17 +01:00 |
|
Eyck Jentzsch
|
68b5697c8f
|
Fix cycles JSON template
|
2022-02-01 21:48:56 +01:00 |
|
Eyck Jentzsch
|
059bd0d371
|
rework cycle estimation
|
2022-02-01 19:03:45 +01:00 |
|
Eyck Jentzsch
|
ef2a4df925
|
simplify spawn block handling
|
2022-01-31 23:40:31 +01:00 |
|
Eyck Jentzsch
|
afe8905ac9
|
fix else-ambiguity in CoreDSL description
|
2022-01-31 20:30:46 +01:00 |
|
Eyck Jentzsch
|
3563ba80d0
|
add spawn blocks
|
2022-01-12 07:21:16 +01:00 |
|
Eyck Jentzsch
|
07d5af1dde
|
fix stand-alone ISS compilation to include all generated cores
|
2021-11-26 17:56:40 +01:00 |
|
Eyck Jentzsch
|
965929d1eb
|
remove descriptions
|
2021-11-15 09:30:16 +01:00 |
|
Eyck Jentzsch
|
d31b4ef5a8
|
fix MISA val
|
2021-11-11 12:58:57 +01:00 |
|
Eyck Jentzsch
|
7452c5df43
|
add TGC_D_XRB_NN definition
|
2021-11-11 12:16:35 +01:00 |
|
Eyck Jentzsch
|
fd98ad95f6
|
rework PMP check and fix MISA for TGC_D
|
2021-11-09 15:55:22 +01:00 |
|
Eyck Jentzsch
|
c42e336509
|
fix proper debug mode handling (#267 & #268)
|
2021-11-07 17:48:44 +01:00 |
|
Eyck Jentzsch
|
8b6e3abd23
|
fix hard-code arch in templates
|
2021-10-30 13:37:17 +02:00 |
|
Eyck Jentzsch
|
1616f0ac90
|
remove deprecated functions
|
2021-10-30 12:57:08 +02:00 |
|
Eyck Jentzsch
|
a20f39e847
|
update core definitions to include Zicsr and Zifencei (#276)
|
2021-10-30 12:56:31 +02:00 |
|
Eyck Jentzsch
|
334d3fb296
|
adapt to SCC changes
|
2021-10-21 22:53:16 +02:00 |
|
Eyck Jentzsch
|
1d13c8196e
|
fix wrong PGMASK usage
|
2021-10-11 10:40:01 +02:00 |
|
Eyck Jentzsch
|
b17682e50e
|
fix YAML template
|
2021-10-01 23:49:04 +02:00 |
|
Eyck Jentzsch
|
6acf73a40f
|
add template to generate instruction YAML
|
2021-10-01 13:05:36 +02:00 |
|
Eyck Jentzsch
|
2f15d9676e
|
fix unaligned instr fetch behavior
|
2021-09-30 19:27:46 +02:00 |
|
Eyck Jentzsch
|
4186723d37
|
add marchid setting to CoreDSL description
|
2021-09-30 19:26:21 +02:00 |
|
Eyck Jentzsch
|
aa84a27a5b
|
fix JALR alignment in description
|
2021-09-29 00:43:42 +02:00 |
|
Eyck Jentzsch
|
438e598a4a
|
remove clutter from core descriptions, added instr alignment setting
|
2021-09-29 00:03:11 +02:00 |
|
Eyck Jentzsch
|
174259155d
|
add support for non-compressed ISA
|
2021-09-23 21:09:52 +02:00 |
|
Eyck Jentzsch
|
a3084456fd
|
rework core definitions
|
2021-09-04 12:47:07 +02:00 |
|
Eyck Jentzsch
|
adeffe47ad
|
fix behavior of riscv_hart_mu_p to match TGC_D
|
2021-08-12 20:34:10 +02:00 |
|
Eyck Jentzsch
|
d95846a849
|
fix trap handling if illegal fetch (PMP) and U-mode CSRs
|
2021-08-01 17:23:22 +02:00 |
|
Eyck Jentzsch
|
e68918c2e8
|
fix instruction decode
|
2021-07-09 07:37:12 +02:00 |
|
Eyck Jentzsch
|
2f4b5bd9b2
|
fix detailed behavior of TGC_C
|
2021-07-06 21:19:36 +02:00 |
|
Eyck Jentzsch
|
23b9741adf
|
refine and fix TGC_C iss to becoem compliant
|
2021-06-29 11:51:30 +02:00 |
|
Eyck Jentzsch
|
e432dd8208
|
fix handling of exceptions while accessing address spaces
|
2021-06-07 22:22:36 +02:00 |
|
Eyck Jentzsch
|
aaceecd5dc
|
fix mu_p platform features and CSRs
|
2021-05-17 09:20:09 +02:00 |
|
Eyck Jentzsch
|
cf7b62a3f9
|
update names
|
2021-05-13 15:54:48 +02:00 |
|
Eyck Jentzsch
|
32e4aa83b8
|
use extracted variables
|
2021-03-27 09:36:52 +00:00 |
|
Eyck Jentzsch
|
78c7064295
|
update groovy template to extract used registers
|
2021-03-26 08:24:45 +00:00 |
|
Eyck Jentzsch
|
b0bcb7febb
|
small fixes for robustness and readability
|
2021-03-22 22:47:30 +00:00 |
|
Eyck Jentzsch
|
4e0f20eba0
|
rework abort conditions
|
2021-03-17 19:32:57 +00:00 |
|
Eyck Jentzsch
|
ff3fa19208
|
fix RVM description bugs
|
2021-03-13 10:46:41 +00:00 |
|
Eyck Jentzsch
|
80057eef32
|
fix RVC description bugs, remove paged fetch
|
2021-03-13 10:46:41 +00:00 |
|
Eyck Jentzsch
|
f4ec21007b
|
fix signedness issues
|
2021-03-11 16:12:28 +00:00 |
|
Eyck Jentzsch
|
ac8eab6e25
|
update RISC-V desciptions
|
2021-03-10 17:31:10 +00:00 |
|
Eyck Jentzsch
|
bea0dcc387
|
update missing XLEN
|
2021-03-09 11:03:37 +00:00 |
|
Eyck Jentzsch
|
a6691bcd3c
|
update generated code with correct sign extension
|
2021-03-09 10:21:36 +00:00 |
|
Eyck Jentzsch
|
c171e3c1ba
|
update CoreDSL descriptions
|
2021-03-07 10:51:15 +00:00 |
|
Eyck Jentzsch
|
c251fe15d5
|
fix desscriptions to conform to ISA spec version 20191213 and TGF-C
|
2021-03-07 10:51:00 +00:00 |
|
Eyck Jentzsch
|
dae8acb8a3
|
checkpoint before refactor
|
2021-03-06 07:17:42 +00:00 |
|
Eyck Jentzsch
|
be0e7db185
|
fix templates to comply with CoreDSL2
|
2021-03-01 21:07:20 +00:00 |
|
Eyck Jentzsch
|
9534d58d01
|
regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
|
2021-03-01 06:26:33 +00:00 |
|
Eyck Jentzsch
|
1668df0531
|
regenerated sources and and add opcode enum to headers
|
2021-02-23 08:29:31 +00:00 |
|
Eyck Jentzsch
|
d8e009c72b
|
update CoreDSL decriptions
|
2021-02-15 18:15:13 +00:00 |
|
Eyck Jentzsch
|
72b09472d5
|
update RISC-V descriptions
|
2021-02-15 18:01:33 +00:00 |
|
Eyck Jentzsch
|
3261055871
|
update description to latest CoreDSL2
|
2021-02-15 11:35:56 +00:00 |
|
Eyck Jentzsch
|
34bb8e62ae
|
generate working ISS from CoreDSL 2.0
|
2021-02-06 14:47:06 +00:00 |
|
Eyck Jentzsch
|
da7e29fbb7
|
update definitions of derived constants
|
2021-01-01 09:19:48 +00:00 |