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d330307ed5
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splits bus into 2 sockets for i/dbus
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2023-05-04 21:59:31 +02:00 |
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916de2a26d
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changes build setup to compile specific files if a core is specified
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2023-05-04 16:08:33 +02:00 |
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aa70d8a54a
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fixes CLIC to match clicinfo description in CLIC spec 11.04.2023
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2023-05-02 17:22:13 +02:00 |
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b493745cd7
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sets reset start time to 0
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2023-05-02 11:21:42 +02:00 |
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f9e8e1d857
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fixes core_complex wrt. tlm quantum and DMI
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2023-05-02 11:13:25 +02:00 |
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974d64a627
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adds logo to imported instance
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2023-05-02 08:17:17 +02:00 |
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d70489cbb8
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update import script to initialize broker
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2023-05-02 07:58:48 +02:00 |
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d990f1cf5d
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fixes reading of 64bit CSR register
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2023-05-01 22:23:35 +02:00 |
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1672b01e62
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adds WT cache functionality as mixin
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2023-04-28 20:38:07 +02:00 |
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00b0f101ac
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adapts to changes of instrumentation interface in dbt-rise-core
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2023-04-28 20:38:07 +02:00 |
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Rocco Jonack
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54f75f92ea
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improved testbench import; added prebuild FW for testing
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2023-04-24 08:44:12 -07:00 |
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Rocco Jonack
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0304aac9e5
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fixed some issues in import script; added README for reference; added initial testbench script(to be improved)
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2023-04-19 05:20:58 -07:00 |
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8ff55d7b92
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updates CWR dependent core_complex definition
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2023-04-14 19:34:41 +02:00 |
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f626ee2684
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fixes privilege wrapper for M/U to cope with 64bit
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2023-04-05 15:38:25 +02:00 |
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a8a2782329
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adds changes from latest CoreDSL description
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2023-04-04 16:10:12 +02:00 |
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98dd329833
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fixes CSR access rights
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2023-04-04 09:23:08 +02:00 |
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6213445bc4
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fixes 64bit behavior of CSR regs
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2023-03-27 12:04:43 +02:00 |
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c5465bf9e2
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fixes according to fixed generator
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2023-03-26 14:44:15 +02:00 |
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d881cb6e63
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fix data width of generated code
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2023-03-26 12:12:34 +02:00 |
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2e4faa4d50
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fixes mstatus mask
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2023-03-25 09:14:56 +01:00 |
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8e1951f298
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adds 64bit mstatus
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2023-03-23 07:47:21 +01:00 |
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7efa924510
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fixes m/uintstatus read
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2023-03-17 10:51:39 +01:00 |
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febbc4fff0
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fixes m/uintstatus read
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2023-03-17 10:23:05 +01:00 |
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39b2788b7e
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implements and fixes CLIC CSR behavior
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2023-03-17 09:09:09 +01:00 |
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a943dd3bdf
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fixes wrong array size which led to unintended CSR definitions
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2023-03-15 14:16:08 +01:00 |
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fedbff5971
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fixes xcause and u-mode clic CSRs
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2023-03-15 12:27:39 +01:00 |
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c2758e8321
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removes mscratchcsw from CLIC feature
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2023-03-15 09:07:00 +01:00 |
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8be5fe71df
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fixes template name typo
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2023-03-12 07:42:09 +01:00 |
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3f7ce41b9d
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fixes CLIC mtvt register behavior
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2023-03-11 14:03:03 +01:00 |
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ad1cbedf00
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adds back missing max irq functions
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2023-03-11 12:47:10 +01:00 |
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83f54b5074
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fixes CLICCFG settings
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2023-03-11 08:48:03 +01:00 |
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a83928fd8c
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fixes CSR/CLIC implementation
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2023-03-10 20:40:21 +01:00 |
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ec55efd322
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adds generator changed files
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2023-02-17 06:36:34 +01:00 |
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8c3709f92a
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adds generator changed files
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2023-02-17 06:29:27 +01:00 |
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207dbf1071
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fixes out of range access for register alias names
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2023-02-17 06:28:30 +01:00 |
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62c118e501
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fixes CSR to match latest fast interrupts spec
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2023-01-20 16:21:04 +01:00 |
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65dca13b42
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fixes WFI miss of interrupt
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2023-01-14 17:40:21 +01:00 |
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3187cbdfe2
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removes CONAN_PKG from build system
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2022-12-12 02:55:44 +01:00 |
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8c701d55c1
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adapt to latest changes in SCC
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2022-12-05 09:15:48 +01:00 |
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f585489ff5
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fixes pin naming
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2022-10-26 17:21:44 +02:00 |
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7113683ee0
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moves pending interrupt check before handling trap thus saving 1 cycle
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2022-10-15 10:47:35 +02:00 |
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1a0fc4bd5d
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fixes wrong mcounteren in M-mode only priv wrapper
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2022-10-10 08:59:27 +02:00 |
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40d1966e9a
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fixes pending irq within irq hander behavior
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2022-10-08 11:20:52 +02:00 |
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a977200284
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cleans up priv wrappers
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2022-10-05 08:58:57 +02:00 |
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b20fd3eba5
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fix static build
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2022-09-28 19:37:47 +02:00 |
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b20daa1ac2
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fixes wrong path in install
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2022-09-27 09:11:41 +02:00 |
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b1a18459e7
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adds more flexible use of availabel targets
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2022-09-26 13:57:24 +02:00 |
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6ba7c82f80
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fixes wrapper definitions for hwl cores
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2022-09-26 13:31:46 +02:00 |
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ad7bb28b4c
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fixes write mask of clic memory mapped registers
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2022-09-17 12:15:19 +02:00 |
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fa7eda0889
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fixes wrong check for exception
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2022-08-31 11:45:53 +02:00 |
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